signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0);
signal dhcp_done, link_ok, soft_rst : std_logic;
+
+signal dum_busy, dum_read, dum_dataready, dum_rd_en, dum_frame_ready : std_logic;
+signal dum_data, dum_frame_size : std_logic_vector(15 downto 0);
+signal dum_frame_proto : std_logic_vector(4 downto 0);
+signal dum_q : std_logic_vector(8 downto 0);
begin
end if;
end process reset_sync;
-global_reset <= not rst_n or soft_rst;
+global_reset <= not rst_n; -- or soft_rst;
-- gk 23.04.10
LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_INIT_READ_IN => '1', --GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => dum_dataready, --GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => dum_data, --GSC_REPLY_DATA_IN,
GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
+ GSC_REPLY_READ_OUT => dum_read, --GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => dum_busy, --GSC_BUSY_IN,
MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
FEE_READ_IN =>gbe_fee_read,
FEE_STATUS_BITS_OUT =>gbe_fee_status_bits,
FEE_BUSY_OUT =>gbe_fee_busy
- );
+ );
+
+-- sctrl_dummy : gbe_sctrl_dummy
+-- generic map(
+-- DO_SIMULATION => DO_SIMULATION,
+-- FIXED_DELAY_MODE => 0,
+-- FIXED_DELAY => 4096
+-- )
+-- port map(
+-- clk => clk,
+-- rst => global_reset,
+--
+-- RC_RD_EN_IN => dum_rd_en,
+-- RC_Q_OUT => dum_q,
+-- RC_FRAME_WAITING_OUT => dum_frame_ready,
+-- RC_LOADING_DONE_IN => '0',
+-- RC_FRAME_SIZE_OUT => dum_frame_size,
+-- RC_FRAME_PROTO_OUT => dum_frame_proto,
+--
+-- RC_SRC_MAC_ADDRESS_OUT => open,
+-- RC_DEST_MAC_ADDRESS_OUT => open,
+-- RC_SRC_IP_ADDRESS_OUT => open,
+-- RC_DEST_IP_ADDRESS_OUT => open,
+-- RC_SRC_UDP_PORT_OUT => open,
+-- RC_DEST_UDP_PORT_OUT => open,
+--
+-- GSC_REPLY_DATAREADY_OUT => dum_dataready,
+-- GSC_REPLY_DATA_OUT => dum_data,
+-- GSC_REPLY_PACKET_NUM_OUT => open,
+-- GSC_REPLY_READ_IN => dum_read,
+-- GSC_BUSY_OUT => dum_busy
+-- );
+
+
end generate main_with_dummy_gen;
MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
load_next_state <= CLOSE_QUEUE;
elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
load_next_state <= CLOSE_QUEUE;
- elsif (trigger_type /= previous_ttype and previous_ttype /= x"0") then
+ elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then
load_next_state <= CLOSE_QUEUE;
- elsif (bank_select /= previous_bank and previous_ttype /= x"0") then
+ elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then
load_next_state <= CLOSE_QUEUE;
else
load_next_state <= PREPARE_TO_LOAD_SUB;
elsif (load_current_state = DECIDE) then
if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then
queue_size <= subevent_size + x"10" + x"8" + x"4";
--- elsif (number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
--- queue_size <= subevent_size + x"10" + x"8" + x"4";
elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
queue_size <= subevent_size + x"10" + x"8" + x"4";
elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (trigger_type /= previous_ttype and previous_ttype /= x"0") then
+ elsif (trigger_type /= previous_ttype and number_of_subs /= x"0000") then
queue_size <= subevent_size + x"10" + x"8" + x"4";
- elsif (bank_select /= previous_bank and previous_ttype /= x"0") then
+ elsif (bank_select /= previous_bank and number_of_subs /= x"0000") then
queue_size <= subevent_size + x"10" + x"8" + x"4";
else
queue_size <= queue_size;
--*****
-- event builder selection
---TODO: close the current multievent packet in case event builder address changes
BANK_SELECT_PROC : process(CLK_GBE)
begin
if RESET = '1' then
redirect_current_state <= IDLE;
elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- redirect_current_state <= IDLE;
--- else
if RX_PATH_ENABLE = 1 then
redirect_current_state <= redirect_next_state;
else
redirect_current_state <= IDLE;
end if;
--- end if;
end if;
end process REDIRECT_MACHINE_PROC;
else
redirect_next_state <= IDLE;
end if;
- -- gk 16.11.11
+
when CHECK_TYPE =>
if (link_current_state = ACTIVE) then
redirect_next_state <= CHECK_BUSY;
redirect_next_state <= DROP;
end if;
- -- gk 07.11.11
when DROP =>
redirect_state <= x"7";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE; --FINISH;
+ redirect_next_state <= WAIT_ONE;
else
redirect_next_state <= DROP;
end if;
when LOAD =>
redirect_state <= x"2";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE; --FINISH;
+ redirect_next_state <= WAIT_ONE;
else
redirect_next_state <= LOAD;
end if;
FLOW_MACHINE_PROC : process(RESET, CLK)
begin
if RESET = '1' then
- flow_current_state <= IDLE;
- elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- flow_current_state <= IDLE;
--- else
- flow_current_state <= flow_next_state;
--- end if;
- end if;
+ flow_current_state <= IDLE;
+ elsif rising_edge(CLK) then
+ flow_current_state <= flow_next_state;
+ end if;
end process FLOW_MACHINE_PROC;
FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data)
end if;
end if;
end process;
---TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0';
---TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = IDLE and ps_response_ready = '1') else '0';
-
---mc_busy <= '0' when flow_current_state = IDLE else '1';
---mc_busy <= '1' when flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC else '0';
--***********************
-- LINK STATE CONTROL
if MC_RESET_LINK_IN = '1' then
link_current_state <= INACTIVE;
elsif rising_edge(CLK) then
--- --if (RESET = '1') then
--- if (RESET_FOR_DHCP = '1') then
--- if (g_SIMULATE = 0) then
--- link_current_state <= INACTIVE;
--- else
--- link_current_state <= FINALIZE; --ACTIVE; --GET_ADDRESS; --ACTIVE;
--- end if;
--- else
if RX_PATH_ENABLE = 1 and DO_SIMULATION = 0 then
link_current_state <= link_next_state;
elsif DO_SIMULATION = 1 then
else
link_current_state <= ACTIVE;
end if;
--- end if;
end if;
end process;
begin
-PRIORITIZE : process(CLK, FRAME_TYPE_IN, PROTOCOL_CODE_IN)
+PRIORITIZE : process(RESET, CLK)
begin
if RESET = '1' then
CODE_OUT <= (others => '0');
--DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
--DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
-LOAD_MACHINE_PROC : process(CLK)
+LOAD_MACHINE_PROC : process(RESET, CLK)
begin
if RESET = '1' then
load_current_state <= IDLE;
elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- load_current_state <= IDLE;
--- else
load_current_state <= load_next_state;
--- end if;
end if;
end process LOAD_MACHINE_PROC;
-- end if;
--end process SYNC_PROC;
-FRAMES_REC_CTR_PROC : process(CLK)
+FRAMES_REC_CTR_PROC : process(RESET, CLK)
begin
if (RESET = '1') then
frames_received_ctr <= (others => '0');
end if;
end process FRAMES_REC_CTR_PROC;
-FRAMES_READOUT_CTR_PROC : process(CLK)
+FRAMES_READOUT_CTR_PROC : process(RESET, CLK)
begin
if (RESET = '1') then
frames_readout_ctr <= (others => '0');
end process FRAMES_READOUT_CTR_PROC;
-- debug only
-BYTES_REC_CTR_PROC : process(CLK)
+BYTES_REC_CTR_PROC : process(RESET, CLK)
begin
if (RESET = '1') then
bytes_rec_ctr <= (others => '0');
if RESET = '1' then
main_current_state <= BOOTING;
elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- main_current_state <= BOOTING;
--- else
- main_current_state <= main_next_state;
--- end if;
+ main_current_state <= main_next_state;
end if;
end process MAIN_MACHINE_PROC;
-MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, saved_true_ip, saved_proposed_ip, wait_ctr, receive_current_state, PS_DATA_IN)
+MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, wait_ctr, receive_current_state, PS_DATA_IN)
begin
case (main_current_state) is
when ESTABLISHED =>
state2 <= x"6";
--- if (saved_proposed_ip = saved_true_ip) then
- main_next_state <= ESTABLISHED;
--- else
--- main_next_state <= BOOTING;
--- end if;
+ main_next_state <= ESTABLISHED;
end case;
if RESET = '1' then
receive_current_state <= IDLE;
elsif rising_edge(CLK) then
- --if (main_current_state = BOOTING) then
- -- receive_current_state <= IDLE;
- --else
- receive_current_state <= receive_next_state;
- --end if;
+ receive_current_state <= receive_next_state;
end if;
end process RECEIVE_MACHINE_PROC;
state3 <= x"1";
if (PS_ACTIVATE_IN = '1' and PS_WR_EN_IN = '1') then
if (main_current_state = WAITING_FOR_OFFER or main_current_state = WAITING_FOR_ACK) then -- ready to receive dhcp frame
- if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) then --or (PS_DEST_MAC_ADDRESS_IN = x"ffffffffffff") then -- check if i'm the addressee (discards broadcasts also)
+ if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) then -- check if i'm the addressee (discards broadcasts also)
receive_next_state <= SAVE_VALUES;
else
receive_next_state <= DISCARD; -- discard if the frame is not for me
if (construct_current_state = IDLE) then
load_ctr <= 0;
elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then
--- elsif (construct_current_state /= IDLE and construct_current_state /= CLEANUP and PS_SELECTED_IN = '1') then
load_ctr <= load_ctr + 1;
else
load_ctr <= load_ctr;
end if;
end process LOAD_CTR_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (construct_current_state /= IDLE and construct_current_state /= CLEANUP and PS_SELECTED_IN = '1') then
--- TC_WR_EN_OUT <= '1';
--- else
--- TC_WR_EN_OUT <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
TC_DATA_PROC : process(CLK)
begin
if rising_edge(CLK) then
architecture trb_net16_gbe_response_constructor_Ping of trb_net16_gbe_response_constructor_Ping is
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Ping : architecture is "GBE_MAIN_group";
-
attribute syn_encoding : string;
type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
attribute syn_encoding of stats_current_state : signal is "onehot";
-signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
signal saved_data : std_logic_vector(447 downto 0);
signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0);
signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0);
-signal fifo_wr_en, fifo_rd_en : std_logic;
-signal fifo_q : std_logic_vector(7 downto 0);
-
-
-signal stat_data_temp : std_logic_vector(31 downto 0);
-
-signal tc_wr : std_logic;
-
-signal data_reg : std_logic_vector(511 downto 0);
-
begin
-DISSECT_MACHINE_PROC : process(CLK)
+DISSECT_MACHINE_PROC : process(RESET, CLK)
begin
if RESET = '1' then
dissect_current_state <= IDLE;
elsif rising_edge(CLK) then
--- if (RESET = '1') then
--- dissect_current_state <= IDLE;
--- else
- dissect_current_state <= dissect_next_state;
--- end if;
+ dissect_current_state <= dissect_next_state;
end if;
end process DISSECT_MACHINE_PROC;
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length)
+DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length)
begin
case dissect_current_state is
end if;
end process DATA_CTR_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then
--- tc_wr <= '1';
--- else
--- tc_wr <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
DATA_LENGTH_PROC: process(CLK)
begin
if rising_edge(CLK) then
end if;
end process SAVE_VALUES_PROC;
-----TODO: change it to one register 64B
---fifo : fifo_2048x8
--- PORT map(
--- Reset => RESET,
--- RPReset => RESET,
--- WrClock => CLK,
--- RdClock => CLK,
--- Data => PS_DATA_IN(7 downto 0),
--- WrEn => fifo_wr_en,
--- RdEn => fifo_rd_en,
--- Q => fifo_q,
--- Full => open,
--- Empty => open
--- );
-
-----TODO: change it to synchronous
---fifo_wr_en <= '1' when (dissect_current_state = READ_FRAME and data_ctr > 8) else '0';
---fifo_rd_en <= '1' when (dissect_current_state = LOAD_FRAME and data_ctr > 8) else '0';
-
CS_PROC : process(CLK)
begin
if rising_edge(CLK) then
checksum(7 downto 0) <= not (checksum_rrr(7 downto 0) + checksum_lll(15 downto 8));
checksum(15 downto 8) <= not (checksum_lll(7 downto 0) + checksum_rrr(15 downto 8));
-TC_DATA_PROC : process(dissect_current_state, data_ctr, saved_headers, saved_data, data_length)
+TC_DATA_PROC : process(CLK)
begin
if rising_edge(CLK) then
tc_data(8) <= '0';
end loop;
else -- data
for i in 0 to 7 loop
- tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i); --fifo_q(i);
+ tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i);
end loop;
-- mark the last byte
end if;
end process TC_DATA_PROC;
---TC_WR_EN_OUT <= tc_wr;
-
PS_RESPONSE_SYNC : process(CLK)
begin
if rising_edge(CLK) then
signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
signal ip_cfg_mem_clk : std_logic;
-signal ic_dest_mac : std_logic_vector(47 downto 0);
-signal ic_dest_ip : std_logic_vector(31 downto 0);
-signal ic_dest_udp : std_logic_vector(15 downto 0);
-signal ic_src_mac : std_logic_vector(47 downto 0);
-signal ic_src_ip : std_logic_vector(31 downto 0);
-signal ic_src_udp : std_logic_vector(15 downto 0);
+signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0);
+signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0);
+signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0);
+signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0);
+signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0);
+signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0);
signal pc_wr_en : std_logic;
signal pc_data : std_logic_vector(7 downto 0);
TC_FRAME_SIZE_OUT <= event_bytes;
TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= ic_dest_mac; --x"c4e870211b00"; --ic_dest_mac;
-TC_DEST_IP_OUT <= ic_dest_ip; --x"0300a8c0"; --ic_dest_ip;
-TC_DEST_UDP_OUT <= ic_dest_udp; --x"c35c"; --ic_dest_udp;
+
+TC_DEST_MAC_OUT <= ic_dest_mac_shift; --x"c4e870211b00"; --ic_dest_mac;
+TC_DEST_IP_OUT <= ic_dest_ip_shift; --x"0300a8c0"; --ic_dest_ip;
+TC_DEST_UDP_OUT <= ic_dest_udp_shift; --x"c35c"; --ic_dest_udp;
+
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (ip_cfg_start = '1') then
+ ic_dest_mac_shift <= ic_dest_mac;
+ ic_dest_ip_shift <= ic_dest_ip;
+ ic_dest_udp_shift <= ic_dest_udp;
+ else
+ ic_dest_mac_shift <= ic_dest_mac_shift;
+ ic_dest_ip_shift <= ic_dest_ip_shift;
+ ic_dest_udp_shift <= ic_dest_udp_shift;
+ end if;
+ end if;
+end process;
+
rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
when x"0c" =>
max_sub <= BUS_DATA_IN(15 downto 0);
- when x"0d" =>
+ when x"10" =>
max_queue <= BUS_DATA_IN(15 downto 0);
when x"0e" =>
data_out(15 downto 0) <= max_sub;
data_out(31 downto 16) <= (others => '0');
- when 13 =>
- data_out(15 downto 0) <= max_queue;
- data_out(31 downto 16) <= (others => '0');
-
when 14 =>
data_out(15 downto 0) <= max_subs_in_queue;
data_out(31 downto 16) <= (others => '0');
data_out(15 downto 0) <= max_single_sub;
data_out(31 downto 16) <= (others => '0');
+ when 16 =>
+ data_out(15 downto 0) <= max_queue;
+ data_out(31 downto 16) <= (others => '0');
+
-- Histogram of sctrl data sizes
when 96 to 127 =>
data_out <= SCTRL_HIST_IN(address - 96);
);
end component;
+component gbe_sctrl_dummy is
+ generic (
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+ FIXED_DELAY : integer range 0 to 65535 := 4096
+ );
+ port (
+ clk : in std_logic;
+ rst : in std_logic;
+
+ RC_RD_EN_IN : in std_logic;
+ RC_Q_OUT : out std_logic_vector(8 downto 0);
+ RC_FRAME_WAITING_OUT : out std_logic;
+ RC_LOADING_DONE_IN : in std_logic;
+ RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+
+ RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+ RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+
+ GSC_REPLY_DATAREADY_OUT : out std_logic;
+ GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_IN : in std_logic;
+ GSC_BUSY_OUT : out std_logic
+ );
+end component;
+
component trb_net16_gbe_buf is
generic(
DO_SIMULATION : integer range 0 to 1 := 1;
jspc29 / trbnet.git / commitdiff