mbs trigger isgnal generation is moved to deciated entitiy in CRI repo.

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index d9e973a7bf75c2ead94f76b0848861737be2cee2..8c18a31b82d78b84ccc0796c0ff2cc88afcad58b 100644 (file)
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -224,6 +224,7 @@ add_file -vhdl -lib work "../../cri/src/trb_net16_cri_interface.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
 add_file -vhdl -lib work "../../cri/src/cri_data_sender.vhd"
+add_file -vhdl -lib work "../../cri/src/mbs_generator_cbmrich.vhd"
 
 add_file -vhdl -lib work "../../trb3/cts/source/mbs_master.vhd"
 add_file -vhdl -lib work "../../trb3sc/hub_cts/code/mbs_vulom_recv.vhd"

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index 1202eaa788246e68006224016d990958bb87db64..3710d98425fd9b6fb73f1c00310b6db38756b64a 100644 (file)
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -116,8 +116,8 @@ architecture arch of combiner is
   signal int2med           : int2med_array_t(0 to INTERFACE_NUM); -- 1 more due to uplink
   signal med_stat_debug    : std_logic_vector (1*64-1  downto 0);
   
-  signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx,  bustdc_rx ,bustdccal_rx, bus_mbs_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx                    : CTRLBUS_RX;
-  signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx  , bustdc_tx, bustdccal_tx, bus_mbs_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx      : CTRLBUS_TX;
+  signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx,  bustdc_rx ,bustdccal_rx, bus_mbs_rx, bus_mbs_gen_rx, buscts_rx, buscrireg_rx, busCriDatadbgReg_rx                    : CTRLBUS_RX;
+  signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx  , bustdc_tx, bustdccal_tx, bus_mbs_tx, bus_mbs_gen_tx, buscts_tx, buscrireg_tx, busCriDatadbgReg_tx      : CTRLBUS_TX;
   
   signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
   signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
@@ -865,31 +865,22 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 ---------------------------------------------------------------------------
 -- MBS
 ---------------------------------------------------------------------------  
-   THE_LOCAL_MBS_CREATE : process
-     variable cnt : unsigned(17 downto 0) := (others => '0');
-   begin
---     wait until rising_edge(clk_sys);
-     wait until rising_edge(med2int(INTERFACE_NUM).clk_full);
-     mbs_local_trigger_in <= '0';
-     if (reset_i = '1') then
-       cnt := 0;
-       mbs_local_trigger_num_in <= (others => '0');
-     elsif (dlm_rx_i = '1') then
-       mbs_local_trigger_in     <= '1';
-       mbs_local_trigger_num_in <= (others => '0');    
-       cnt := 20479;--(10240*2)-1;
-     else
-       cnt := cnt + 1;
-       if (cnt = 20479) then --(10240*2)-1;
-         mbs_local_trigger_in     <= '1';
-         mbs_local_trigger_num_in <= std_logic_vector(unsigned(mbs_local_trigger_num_in) + 1);
-       end if;
-       if (cnt = (10240*2)) then
-         mbs_local_trigger_in <= '1';
-         cnt := 0;
-       end if;
-     end if;
-   end process;
+   
+   THE_MBS_GENERATOR : entity work.mbs_generator_cbmrich
+   port map (
+      CLK_SYS               => clk_sys,                       
+      CLK_RX                => med2int(INTERFACE_NUM).clk_full,
+      RESET_IN              => reset_i,
+
+      DLM_RX_IN             => dlm_rx_i,
+      DLM_RX_DATA           => dlm_rx_word,
+      
+      MBS_LOC_TRIG          => mbs_local_trigger_in,
+      MBS_LOC_TRIG_NUM      => mbs_local_trigger_num_in,
+      
+      BUS_RX                => bus_mbs_gen_rx,
+      BUS_TX                => bus_mbs_gen_tx
+     );
   
   
    THE_MBS_MASTER : entity work.mbs_master
@@ -950,11 +941,11 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
-      PORT_NUMBER      => 13,
+      PORT_NUMBER      => 14,
       PORT_ADDRESSES   => (0 => x"d000", 1 => x"d300", 2 => x"b000",  3 => x"b200",  4 => x"b400",  5 => x"b600", 6 => x"c000",
-                           7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e100", 12 => x"e400", others => x"0000"),
-      PORT_ADDR_MASK   => (0 => 12,      1 => 1,       2 => 9,        3 => 9,        4 => 9,        5 => 9,       6 => 12,
-                           7 =>  4,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 2,  others => 0),
+                           7 => x"e000", 8 => x"ef00", 9 => x"a000", 10 => x"8300", 11 => x"e100", 12 => x"e400", 13 => x"e410", others => x"0000"),
+      PORT_ADDR_MASK   => (0 => 12,      1 => 1,       2 => 9,        3 => 9,        4 => 9,        5 => 9,       6  => 12,
+                           7 =>  4,      8 => 8,       9 => 11,      10 => 8,       11 => 8,       12 => 4,       13 => 2,  others => 0),
       PORT_MASK_ENABLE => 1
       )
     port map(
@@ -974,9 +965,10 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
       BUS_RX(7) => bustdccal_rx,
       BUS_RX(8) => busdebug_rx,
       BUS_RX(9) => buscts_rx,
-      BUS_RX(10) => buscrireg_rx,
+      BUS_RX(10)=> buscrireg_rx,
       BUS_RX(11)=> busCriDatadbgReg_rx,
-      BUS_RX(12)=> bus_mbs_rx,
+      BUS_RX(12)=> bus_mbs_gen_rx,
+      BUS_RX(13)=> bus_mbs_rx,
       BUS_TX(0) => bustools_tx,
       BUS_TX(1) => bustc_tx,
       BUS_TX(2) => bussci_tx(0),
@@ -987,9 +979,10 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
       BUS_TX(7) => bustdccal_tx,
       BUS_TX(8) => busdebug_tx,
       BUS_TX(9) => buscts_tx,
-      BUS_TX(10) => buscrireg_tx,
+      BUS_TX(10)=> buscrireg_tx,
       BUS_TX(11)=> busCriDatadbgReg_tx,
-      BUS_TX(12)=> bus_mbs_tx,
+      BUS_TX(12)=> bus_mbs_gen_tx,
+      BUS_TX(13)=> bus_mbs_tx,
       STAT_DEBUG => open
       );