--Begin of design configuration
------------------------------------------------------------------------------
-
+ constant USE_DUMMY_READOUT : integer := c_YES; --use slowcontrol for readout, no trigger logic
--Run wih 125 MHz instead of 100 MHz
constant USE_125_MHZ : integer := c_NO; --not implemented yet!
library work;
use work.trb_net_std.all;
use work.trb3_components.all;
+use work.adc_package.all;
entity adc_ad9219 is
generic(
- CHANNELS : integer range 4 to 4 := 4;
- DEVICES_LEFT : integer range 1 to 7 := 7;
- DEVICES_RIGHT : integer range 1 to 7 := 5;
- RESOLUTION : integer range 10 to 10 := 10
+ NUM_DEVICES : integer := 5
);
port(
CLK : in std_logic;
RESTART_IN : in std_logic;
ADCCLK_OUT : out std_logic;
--FCO is another channel for each ADC
- ADC_DATA : in std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*(CHANNELS+1)-1 downto 0);
- ADC_DCO : in std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT) downto 1);
+ ADC_DATA : in std_logic_vector(NUM_DEVICES*(CHANNELS+1)-1 downto 0);
+ ADC_DCO : in std_logic_vector(NUM_DEVICES downto 1);
- DATA_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*CHANNELS*RESOLUTION-1 downto 0);
- FCO_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*RESOLUTION-1 downto 0);
- DATA_VALID_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)-1 downto 0);
- DEBUG : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*CHANNELS*32-1 downto 0)
+ DATA_OUT : out std_logic_vector(NUM_DEVICES*CHANNELS*RESOLUTION-1 downto 0);
+ FCO_OUT : out std_logic_vector(NUM_DEVICES*RESOLUTION-1 downto 0);
+ DATA_VALID_OUT : out std_logic_vector(NUM_DEVICES-1 downto 0);
+ DEBUG : out std_logic_vector(NUM_DEVICES*CHANNELS*32-1 downto 0)
);
end entity;
architecture adc_ad9219_arch of adc_ad9219 is
-type s_t is array(0 to 11) of integer range 0 to 1;
-constant fpgaside : s_t := (0,0,0,0,0,0,1,0,1,1,1,1);
-
-type q_t is array(0 to 11) of std_logic_vector(19 downto 0);
+type q_t is array(0 to NUM_DEVICES-1) of std_logic_vector(19 downto 0);
signal q,qq,qqq,q_q : q_t;
-signal clk_adcfast_i : std_logic_vector(1 downto 0); --200MHz
-signal clk_data : std_logic_vector(1 downto 0); --100MHz
-signal clk_data_half : std_logic_vector(1 downto 0);
-signal restart_i : std_logic_vector(1 downto 0);
+signal clk_adcfast_i : std_logic; --200MHz
+signal clk_data : std_logic; --100MHz
+signal clk_data_half : std_logic;
+signal restart_i : std_logic;
type state_t is (S1,S2,S3,S4,S5);
-type states_t is array(0 to 11) of state_t;
+type states_t is array(0 to NUM_DEVICES-1) of state_t;
signal state : states_t;
signal state_q : states_t;
type value_it is array(0 to 4) of std_logic_vector(9 downto 0);
-type value_t is array(0 to 11) of value_it;
+type value_t is array(0 to NUM_DEVICES-1) of value_it;
signal value : value_t;
signal fifo_input : value_t;
-type fifo_t is array(0 to 11) of std_logic_vector(49 downto 0);
+type fifo_t is array(0 to NUM_DEVICES-1) of std_logic_vector(49 downto 0);
signal fifo_output: fifo_t;
-signal fifo_write : std_logic_vector(11 downto 0);
-signal fifo_empty : std_logic_vector(11 downto 0);
-signal fifo_last_empty : std_logic_vector(11 downto 0);
+signal fifo_write : std_logic_vector(NUM_DEVICES-1 downto 0);
+signal fifo_empty : std_logic_vector(NUM_DEVICES-1 downto 0);
+signal fifo_last_empty : std_logic_vector(NUM_DEVICES-1 downto 0);
-signal lock : std_logic_vector(2 downto 0);
+signal lock : std_logic_vector(1 downto 0);
begin
THE_ADC_PLL_0 : entity work.pll_adc10bit
port map(
CLK => CLK_ADCRAW,
- CLKOP => clk_adcfast_i(0),
+ CLKOP => clk_adcfast_i,
LOCK => lock(1)
);
-
- THE_ADC_PLL_1 : entity work.pll_adc10bit
- port map(
- CLK => CLK_ADCRAW,
- CLKOP => clk_adcfast_i(1),
- LOCK => lock(2)
- );
- restart_i(0) <= RESTART_IN when rising_edge(clk_data(0));
- restart_i(1) <= RESTART_IN when rising_edge(clk_data(1));
+ restart_i <= RESTART_IN when rising_edge(clk_data);
+
+gen_7 : if NUM_DEVICES = 7 generate
+ THE_7 : entity work.dqsinput_7x5
+ port map(
+ clk_0 => ADC_DCO(1),
+ clk_1 => ADC_DCO(2),
+ clk_2 => ADC_DCO(3),
+ clk_3 => ADC_DCO(4),
+ clk_4 => ADC_DCO(5),
+ clk_5 => ADC_DCO(6),
+ clk_6 => ADC_DCO(7),
+ clkdiv_reset => RESTART_IN,
+ eclk => clk_adcfast_i,
+ reset_0 => restart_i,
+ reset_1 => restart_i,
+ reset_2 => restart_i,
+ reset_3 => restart_i,
+ reset_4 => restart_i,
+ reset_5 => restart_i,
+ reset_6 => restart_i,
+ sclk => clk_data,
+ datain_0 => ADC_DATA( 4 downto 0),
+ datain_1 => ADC_DATA( 9 downto 5),
+ datain_2 => ADC_DATA(14 downto 10),
+ datain_3 => ADC_DATA(19 downto 15),
+ datain_4 => ADC_DATA(24 downto 20),
+ datain_5 => ADC_DATA(29 downto 25),
+ datain_6 => ADC_DATA(34 downto 30),
+ q_0 => q(0),
+ q_1 => q(1),
+ q_2 => q(2),
+ q_3 => q(3),
+ q_4 => q(4),
+ q_5 => q(5),
+ q_6 => q(6)
+ );
+end generate;
-THE_LEFT : entity work.dqsinput_7x5
+gen_5 : if NUM_DEVICES = 5 generate
+ THE_5 : entity work.dqsinput_5x5
port map(
clk_0 => ADC_DCO(1),
clk_1 => ADC_DCO(2),
clk_2 => ADC_DCO(3),
clk_3 => ADC_DCO(4),
clk_4 => ADC_DCO(5),
- clk_5 => ADC_DCO(6),
- clk_6 => ADC_DCO(8),
clkdiv_reset => RESTART_IN,
- eclk => clk_adcfast_i(0),
- reset_0 => restart_i(0),
- reset_1 => restart_i(0),
- reset_2 => restart_i(0),
- reset_3 => restart_i(0),
- reset_4 => restart_i(0),
- reset_5 => restart_i(0),
- reset_6 => restart_i(0),
- sclk => clk_data(0),
+ eclk => clk_adcfast_i,
+ reset_0 => restart_i,
+ reset_1 => restart_i,
+ reset_2 => restart_i,
+ reset_3 => restart_i,
+ reset_4 => restart_i,
+ sclk => clk_data,
datain_0 => ADC_DATA( 4 downto 0),
datain_1 => ADC_DATA( 9 downto 5),
datain_2 => ADC_DATA(14 downto 10),
datain_3 => ADC_DATA(19 downto 15),
datain_4 => ADC_DATA(24 downto 20),
- datain_5 => ADC_DATA(29 downto 25),
- datain_6 => ADC_DATA(39 downto 35),
q_0 => q(0),
q_1 => q(1),
q_2 => q(2),
q_3 => q(3),
- q_4 => q(4),
- q_5 => q(5),
- q_6 => q(7)
- );
-
-THE_RIGHT : entity work.dqsinput_5x5
- port map(
- clk_0 => ADC_DCO(7),
- clk_1 => ADC_DCO(9),
- clk_2 => ADC_DCO(10),
- clk_3 => ADC_DCO(11),
- clk_4 => ADC_DCO(12),
- clkdiv_reset => RESTART_IN,
- eclk => clk_adcfast_i(1),
- reset_0 => restart_i(1),
- reset_1 => restart_i(1),
- reset_2 => restart_i(1),
- reset_3 => restart_i(1),
- reset_4 => restart_i(1),
- sclk => clk_data(1),
- datain_0 => ADC_DATA(34 downto 30),
- datain_1 => ADC_DATA(44 downto 40),
- datain_2 => ADC_DATA(49 downto 45),
- datain_3 => ADC_DATA(54 downto 50),
- datain_4 => ADC_DATA(59 downto 55),
- q_0 => q(6),
- q_1 => q(8),
- q_2 => q(9),
- q_3 => q(10),
- q_4 => q(11)
+ q_4 => q(4)
);
+end generate;
-
-gen_chips_left : for i in 0 to DEVICES_LEFT+DEVICES_RIGHT-1 generate
+gen_chips : for i in 0 to NUM_DEVICES-1 generate
gen_data_mapping : for j in 0 to CHANNELS generate
gen_data_mapping_bits : for k in 0 to 3 generate
end generate;
proc_collect_data : process begin
- wait until rising_edge(clk_data(fpgaside(i)));
+ wait until rising_edge(clk_data);
qq(i) <= q(i);
fifo_write(i) <= '0';
case state(i) is
when S1 =>
--- fifo_input(i)(0)(3 downto 0) <= qqq(i)(3 downto 0 );
--- fifo_input(i)(1)(3 downto 0) <= qqq(i)(7 downto 4 );
--- fifo_input(i)(2)(3 downto 0) <= qqq(i)(11 downto 8 );
--- fifo_input(i)(3)(3 downto 0) <= qqq(i)(15 downto 12);
--- fifo_input(i)(4)(3 downto 0) <= qqq(i)(19 downto 16);
--- fifo_write(i) <= '1';
if qqq(i)(19 downto 16) = "0011" then
state(i) <= S2;
value(i)(0)(9 downto 8) <= qqq(i)(1 downto 0 );
value(i)(3)(5 downto 2) <= qqq(i)(15 downto 12);
value(i)(4)(5 downto 2) <= qqq(i)(19 downto 16);
end case;
- if restart_i(fpgaside(i)) = '1' then
+ if restart_i = '1' then
state(i) <= S1;
end if;
end process;
Data(29 downto 20) => fifo_input(i)(2),
Data(39 downto 30) => fifo_input(i)(3),
Data(49 downto 40) => fifo_input(i)(4),
- WrClock => clk_data(fpgaside(i)),
+ Data(59 downto 50) => (others => '0'),
+ WrClock => clk_data,
RdClock => CLK,
WrEn => fifo_write(i),
RdEn => '1',
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb3_components.all;
+use work.adc_package.all;
+
+entity adc_handler is
+ port(
+ CLK : in std_logic;
+ CLK_ADCRAW : in std_logic;
+
+--ADC
+ ADCCLK_OUT : out std_logic;
+ ADC_DATA : in std_logic_vector((DEVICES_1+DEVICES_2)*(CHANNELS+1)-1 downto 0);
+ ADC_DCO : in std_logic_vector((DEVICES_1+DEVICES_2) downto 1);
+--Trigger In and Out
+ TRIGGER_IN : in std_logic;
+ TRIGGER_FLAG_OUT : out std_logic;
+--Readout
+ READOUT_RX : in READOUT_RX;
+ READOUT_TX : out readout_tx_array_t((DEVICES_1+DEVICES_2)-1 downto 0);
+--Slow control
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ ADCSPI_CTRL: out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture adc_handler_arch of adc_handler is
+
+signal adc_data_out : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
+signal adc_fco_out : std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
+signal adc_valid_out : std_logic_vector(DEVICES-1 downto 0);
+signal adc_debug : std_logic_vector(DEVICES*CHANNELS*32-1 downto 0);
+
+signal buffer_empty : std_logic;
+signal buffer_stop_override : std_logic;
+
+signal ctrl_reg : std_logic_vector(31 downto 0);
+signal adc_restart : std_logic;
+
+signal adc_trigger : std_logic_vector(DEVICES-1 downto 0);
+signal adc_stop : std_logic;
+
+signal config : cfg_t;
+
+signal buffer_addr : std_logic_vector(3 downto 0);
+signal buffer_data : buffer_data_t;
+signal buffer_read : std_logic_vector(DEVICES-1 downto 0);
+signal buffer_ready : std_logic_vector(DEVICES-1 downto 0);
+
+
+-- 000 - 0ff configuration
+-- 000 reset, buffer clear strobes
+-- 010 buffer depth (1-1023)
+-- 011 number of samples after trigger arrived (0-1023 * 25ns)
+-- 012 number of blocks to process (1-4)
+-- 013 trigger generation offset (0-1023 from baseline, polarity)
+-- 014 read-out threshold (0-1023 from baseline, polarity)
+-- 015 number of values to sum before storing
+-- 016 baseline averaging
+-- 020 - 023 number of values to sum (1-255)
+-- 024 - 027 number of sums (1-255)
+-- 028 - 02b 2^k scaling factor (0-8)
+-- 02c - 02f
+-- 100 - 1ff status
+-- 100 clock valid (1 bit per ADC)
+-- 101 fco valid (1 bit per ADC)
+-- 102 readout state
+-- 800 - 87f last ADC values (local 0x0 - 0x3)
+-- 880 - 8ff long-term average / baseline (local 0x4 - 0x7)
+-- e00 - e7f fifo access (debugging only) (local 0x8 - 0xb)
+
+
+begin
+
+
+
+THE_ADC_LEFT : entity work.adc_ad9219
+ generic map(
+ NUM_DEVICES => DEVICES_1
+ )
+ port map(
+ CLK => CLK,
+ CLK_ADCRAW => CLK_ADCRAW,
+ RESTART_IN => adc_restart,
+ ADCCLK_OUT => ADCCLK_OUT,
+ --FCO is another channel for each ADC
+ ADC_DATA( 4 downto 0) => ADC_DATA( 4 downto 0),
+ ADC_DATA( 9 downto 5) => ADC_DATA( 9 downto 5),
+ ADC_DATA(14 downto 10) => ADC_DATA(14 downto 10),
+ ADC_DATA(19 downto 15) => ADC_DATA(19 downto 15),
+ ADC_DATA(24 downto 20) => ADC_DATA(24 downto 20),
+ ADC_DATA(29 downto 25) => ADC_DATA(29 downto 25),
+ ADC_DATA(34 downto 30) => ADC_DATA(39 downto 35),
+ ADC_DCO(6 downto 1) => ADC_DCO(6 downto 1),
+ ADC_DCO(7) => ADC_DCO(8),
+
+ DATA_OUT(6*CHANNELS*RESOLUTION-1 downto 0)
+ => adc_data_out(6*CHANNELS*RESOLUTION-1 downto 0),
+ DATA_OUT(7*CHANNELS*RESOLUTION-1 downto 6*CHANNELS*RESOLUTION)
+ => adc_data_out(8*CHANNELS*RESOLUTION-1 downto 7*CHANNELS*RESOLUTION),
+ FCO_OUT(6*RESOLUTION-1 downto 0)
+ => adc_fco_out(6*RESOLUTION-1 downto 0),
+ FCO_OUT(7*RESOLUTION-1 downto 6*RESOLUTION)
+ => adc_fco_out(8*RESOLUTION-1 downto 7*RESOLUTION),
+
+ DATA_VALID_OUT(5 downto 0) => adc_valid_out(5 downto 0),
+ DATA_VALID_OUT(6) => adc_valid_out(7),
+
+ DEBUG(32*6*CHANNELS-1 downto 0)
+ => adc_debug(32*6*CHANNELS-1 downto 0),
+ DEBUG(32*7*CHANNELS -1 downto 32*6*CHANNELS)
+ => adc_debug(32*8*CHANNELS-1 downto 32*7*CHANNELS)
+
+ );
+
+THE_ADC_RIGHT : entity work.adc_ad9219
+ generic map(
+ NUM_DEVICES => DEVICES_2
+ )
+ port map(
+ CLK => CLK,
+ CLK_ADCRAW => CLK_ADCRAW,
+ RESTART_IN => adc_restart,
+ ADCCLK_OUT => open,
+ --FCO is another channel for each ADC
+ ADC_DATA( 4 downto 0) => ADC_DATA(34 downto 30),
+ ADC_DATA( 9 downto 5) => ADC_DATA(44 downto 40),
+ ADC_DATA(14 downto 10) => ADC_DATA(49 downto 45),
+ ADC_DATA(19 downto 15) => ADC_DATA(54 downto 50),
+ ADC_DATA(24 downto 20) => ADC_DATA(59 downto 55),
+ ADC_DCO(1) => ADC_DCO(7),
+ ADC_DCO(5 downto 2) => ADC_DCO(12 downto 9),
+
+ DATA_OUT(1*CHANNELS*RESOLUTION-1 downto 0)
+ => adc_data_out(7*CHANNELS*RESOLUTION-1 downto 6*CHANNELS*RESOLUTION),
+ DATA_OUT(5*CHANNELS*RESOLUTION-1 downto 1*CHANNELS*RESOLUTION)
+ => adc_data_out(12*CHANNELS*RESOLUTION-1 downto 8*CHANNELS*RESOLUTION),
+ FCO_OUT(1*RESOLUTION-1 downto 0)
+ => adc_fco_out(7*RESOLUTION-1 downto 6*RESOLUTION),
+ FCO_OUT(5*RESOLUTION-1 downto 1*RESOLUTION)
+ => adc_fco_out(12*RESOLUTION-1 downto 8*RESOLUTION),
+
+ DATA_VALID_OUT(0) => adc_valid_out(6),
+ DATA_VALID_OUT(4 downto 1) => adc_valid_out(11 downto 8),
+
+ DEBUG(32*1*CHANNELS-1 downto 0)
+ => adc_debug(32*7*CHANNELS-1 downto 32*6*CHANNELS),
+ DEBUG(32*5*CHANNELS -1 downto 32*1*CHANNELS)
+ => adc_debug(32*12*CHANNELS-1 downto 32*8*CHANNELS)
+
+ );
+
+
+gen_processors : for i in 0 to DEVICES-1 generate
+ THE_ADC_PROC : entity work.adc_processor
+ generic map(
+ DEVICE => i
+ )
+ port map(
+ CLK => CLK,
+
+ ADC_DATA => adc_data_out((i+1)*RESOLUTION*CHANNELS-1 downto i*RESOLUTION*CHANNELS),
+ ADC_VALID => adc_valid_out(i),
+
+ STOP_IN => adc_stop,
+ TRIGGER_OUT => adc_trigger(i),
+
+ CONFIG => config, --trigger offset, zero sup offset, depth,
+
+ DEBUG_BUFFER_ADDR => buffer_addr,
+ DEBUG_BUFFER_READ => buffer_read(i),
+ DEBUG_BUFFER_DATA => buffer_data(i),
+ DEBUG_BUFFER_READY => buffer_ready(i),
+
+ READOUT_RX => READOUT_RX,
+ READOUT_TX => READOUT_TX(i)
+
+ );
+end generate;
+
+TRIGGER_FLAG_OUT <= or_all(adc_trigger);
+
+
+
+PROC_BUS : process begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+
+ if BUS_RX.read = '1' then
+ if BUS_RX.addr >= x"0010" and BUS_RX.addr <= x"0015" then --basic config registers
+ BUS_TX.ack <= '1';
+ BUS_TX.data <= (othrs => '0');
+ case BUS_RX.addr(7 downto 0) is
+ when x"10" => BUS_TX.data(10 downto 0) <= config.buffer_depth;
+ when x"11" => BUS_TX.data(10 downto 0) <= config.samples_after;
+ when x"12" => BUS_TX.data( 1 downto 0) <= config.block_count;
+ when x"13" => BUS_TX.data(17 downto 0) <= config.trigger_threshold;
+ when x"14" => BUS_TX.data(17 downto 0) <= config.readout_threshold;
+ when x"15" => BUS_TX.data( 7 downto 0) <= config.presum;
+
+ end case;
+ end if;
+ elsif BUS_RX.write = '1' then
+ end if;
+end process;
+
+-- 010 buffer depth (1-1023)
+-- 011 number of samples after trigger arrived (0-1023 * 25ns)
+-- 012 number of blocks to process (1-4)
+-- 013 trigger generation offset (0-1023 from baseline, polarity)
+-- 014 read-out threshold (0-1023 from baseline, polarity)
+-- 015 number of values to sum before storing
+
+
+-- if BUS_RX.addr(7 downto 0) = x"80" then
+-- BUS_TX.data <= ctrl_reg;
+-- BUS_TX.ack <= '1';
+-- elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"80"
+-- and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then
+-- BUS_TX.data <= adc_debug(to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32);
+-- BUS_TX.ack <= '1';
+-- elsif BUS_RX.addr(7 downto 0) = x"83" then
+-- BUS_TX.data <= (others => '0');
+-- --BUS_TX.data(10 downto 0) <= buffer_count(0);
+-- BUS_TX.ack <= '1';
+-- elsif BUS_RX.addr(7 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,8)) then
+-- buffer_addr <= to_integer(unsigned(BUS_RX.addr(6 downto 0)));
+-- buffer_read <= '1';
+-- else
+-- BUS_TX.unknown <= '1';
+-- end if;
+--
+-- elsif BUS_RX.write = '1' then
+-- if BUS_RX.addr(7 downto 0) = x"80" then
+-- ctrl_reg <= BUS_RX.data;
+-- BUS_TX.ack <= '1';
+-- elsif BUS_RX.addr(7 downto 0) = x"81" then
+-- adc_restart <= BUS_RX.data(0);
+-- buffer_stop_override <= BUS_RX.data(1);
+-- BUS_TX.ack <= '1';
+-- else
+-- BUS_TX.unknown <= '1';
+-- end if;
+-- end if;
+--
+-- if buffer_ready = '1' then
+-- BUS_TX.ack <= '1';
+-- BUS_TX.data(17 downto 0) <= buffer_data;
+-- BUS_TX.data(30 downto 18) <= (others => '0');
+-- BUS_TX.data(31) <= buffer_empty;
+-- end if;
+-- end process;
+
+
+
+
+end architecture;
+
+
+-- type CTRLBUS_TX is record
+-- data : std_logic_vector(31 downto 0);
+-- ack : std_logic;
+-- wack,rack : std_logic; --for the old-fashioned guys
+-- unknown : std_logic;
+-- nack : std_logic;
+-- end record;
+--
+-- type CTRLBUS_RX is record
+-- data : std_logic_vector(31 downto 0);
+-- addr : std_logic_vector(15 downto 0);
+-- write : std_logic;
+-- read : std_logic;
+-- timeout : std_logic;
+-- end record;
+--
+--
+-- type READOUT_RX is record
+-- data_valid : std_logic;
+-- valid_timing_trg : std_logic;
+-- valid_notiming_trg : std_logic;
+-- invalid_trg : std_logic;
+-- --
+-- trg_type : std_logic_vector( 3 downto 0);
+-- trg_number : std_logic_vector(15 downto 0);
+-- trg_code : std_logic_vector( 7 downto 0);
+-- trg_information : std_logic_vector(23 downto 0);
+-- trg_int_number : std_logic_vector(15 downto 0);
+-- --
+-- trg_multiple : std_logic;
+-- trg_timeout : std_logic;
+-- trg_spurious : std_logic;
+-- trg_missing : std_logic;
+-- trg_spike : std_logic;
+-- --
+-- buffer_almost_full : std_logic;
+-- end record;
+--
+--
+-- type READOUT_TX is record
+-- busy_release : std_logic;
+-- statusbits : std_logic_vector(31 downto 0);
+-- data : std_logic_vector(31 downto 0);
+-- data_write : std_logic;
+-- data_finished : std_logic;
+-- end record;
+--
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package adc_package is
+
+
+
+constant DEVICES : integer := 12;
+constant DEVICES_1 : integer := 7;
+constant DEVICES_2 : integer := 5;
+constant CHANNELS : integer := 4;
+constant RESOLUTION : integer := 10;
+
+
+
+type cfg_t is record
+ buffer_depth : std_logic_vector(10 downto 0);
+ samples_after : std_logic_vector(10 downto 0);
+ block_count : std_logic_vector( 1 downto 0);
+ trigger_threshold : std_logic_vector(17 downto 0);
+ readout_threshold : std_logic_vector(17 downto 0);
+ presum : std_logic_vector( 7 downto 0);
+end record;
+
+type buffer_data_t is array(0 to DEVICES-1) of std_logic_vector(31 downto 0);
+
+end package;
+
+
+package body adc_package is
+end package body;
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb3_components.all;
+use work.adc_package.all;
+
+entity adc_processor is
+ generic(
+ DEVICE : integer range 0 to 15 := 15
+ );
+ port(
+ CLK : in std_logic;
+
+ ADC_DATA : in std_logic_vector(RESOLUTION*CHANNELS-1 downto 0);
+ ADC_VALID : in std_logic;
+ STOP_IN : in std_logic;
+ TRIGGER_OUT: out std_logic;
+
+ CONFIG : in cfg_t;
+
+ DEBUG_BUFFER_READ : in std_logic;
+ DEBUG_BUFFER_ADDR : in std_logic_vector(3 downto 0);
+ DEBUG_BUFFER_DATA : out std_logic_vector(31 downto 0);
+ DEBUG_BUFFER_READY: out std_logic;
+
+ READOUT_RX : in READOUT_RX;
+ READOUT_TX : out READOUT_TX
+
+ );
+end entity;
+
+
+architecture adc_processor_arch of adc_processor is
+
+type ram_t is array(0 to 1023) of std_logic_vector(17 downto 0);
+type ram_arr_t is array(0 to 3) of ram_t;
+
+signal ram : ram_arr_t;
+
+
+
+begin
+
+PROC_REGS : process begin
+ wait until rising_edge(CLK);
+-- if then
+-- end if;
+end process;
+
+end architecture;
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb3_components.all;
+use work.adc_package.all;
+
+entity adc_slowcontrol_data_buffer is
+ port(
+ CLK : in std_logic;
+ CLK_ADCRAW : in std_logic;
+
+ ADCCLK_OUT : out std_logic;
+ ADC_DATA : in std_logic_vector((DEVICES_1+DEVICES_2)*(CHANNELS+1)-1 downto 0);
+ ADC_DCO : in std_logic_vector((DEVICES_1+DEVICES_2) downto 1);
+
+ ADC_CONTROL_OUT : out std_logic_vector(7 downto 0);
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+
+architecture adc_slowcontrol_data_buffer_arch of adc_slowcontrol_data_buffer is
+
+signal fifo_read : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+signal fifo_empty : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+signal fifo_full : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+signal fifo_write : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+signal fifo_reset : std_logic;
+signal fifo_stop : std_logic;
+
+type dout_t is array(0 to DEVICES*CHANNELS-1) of std_logic_vector(17 downto 0);
+signal fifo_dout : dout_t;
+
+type fifo_count_t is array(0 to DEVICES*CHANNELS-1) of std_logic_vector(10 downto 0);
+signal fifo_count : fifo_count_t;
+
+signal ctrl_reg : std_logic_vector(31 downto 0);
+
+signal saved_addr : integer range 0 to DEVICES*CHANNELS-1;
+signal fifo_wait_0, fifo_wait_1, fifo_wait_2 : std_logic;
+
+
+signal adc_data_out : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
+signal adc_fco_out : std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
+signal adc_valid_out : std_logic_vector(DEVICES-1 downto 0);
+signal adc_debug : std_logic_vector(DEVICES*CHANNELS*32-1 downto 0);
+signal adc_restart : std_logic;
+begin
+
+
+
+THE_ADC_LEFT : entity work.adc_ad9219
+ generic map(
+ NUM_DEVICES => DEVICES_1
+ )
+ port map(
+ CLK => CLK,
+ CLK_ADCRAW => CLK_ADCRAW,
+ RESTART_IN => adc_restart,
+ ADCCLK_OUT => ADCCLK_OUT,
+ --FCO is another channel for each ADC
+ ADC_DATA( 4 downto 0) => ADC_DATA( 4 downto 0),
+ ADC_DATA( 9 downto 5) => ADC_DATA( 9 downto 5),
+ ADC_DATA(14 downto 10) => ADC_DATA(14 downto 10),
+ ADC_DATA(19 downto 15) => ADC_DATA(19 downto 15),
+ ADC_DATA(24 downto 20) => ADC_DATA(24 downto 20),
+ ADC_DATA(29 downto 25) => ADC_DATA(29 downto 25),
+ ADC_DATA(34 downto 30) => ADC_DATA(39 downto 35),
+ ADC_DCO(6 downto 1) => ADC_DCO(6 downto 1),
+ ADC_DCO(7) => ADC_DCO(8),
+
+ DATA_OUT(6*CHANNELS*RESOLUTION-1 downto 0)
+ => adc_data_out(6*CHANNELS*RESOLUTION-1 downto 0),
+ DATA_OUT(7*CHANNELS*RESOLUTION-1 downto 6*CHANNELS*RESOLUTION)
+ => adc_data_out(8*CHANNELS*RESOLUTION-1 downto 7*CHANNELS*RESOLUTION),
+ FCO_OUT(6*RESOLUTION-1 downto 0)
+ => adc_fco_out(6*RESOLUTION-1 downto 0),
+ FCO_OUT(7*RESOLUTION-1 downto 6*RESOLUTION)
+ => adc_fco_out(8*RESOLUTION-1 downto 7*RESOLUTION),
+
+ DATA_VALID_OUT(5 downto 0) => adc_valid_out(5 downto 0),
+ DATA_VALID_OUT(6) => adc_valid_out(7),
+
+ DEBUG(32*6*CHANNELS-1 downto 0)
+ => adc_debug(32*6*CHANNELS-1 downto 0),
+ DEBUG(32*7*CHANNELS -1 downto 32*6*CHANNELS)
+ => adc_debug(32*8*CHANNELS-1 downto 32*7*CHANNELS)
+
+ );
+
+THE_ADC_RIGHT : entity work.adc_ad9219
+ generic map(
+ NUM_DEVICES => DEVICES_2
+ )
+ port map(
+ CLK => CLK,
+ CLK_ADCRAW => CLK_ADCRAW,
+ RESTART_IN => adc_restart,
+ ADCCLK_OUT => open,
+ --FCO is another channel for each ADC
+ ADC_DATA( 4 downto 0) => ADC_DATA(34 downto 30),
+ ADC_DATA( 9 downto 5) => ADC_DATA(44 downto 40),
+ ADC_DATA(14 downto 10) => ADC_DATA(49 downto 45),
+ ADC_DATA(19 downto 15) => ADC_DATA(54 downto 50),
+ ADC_DATA(24 downto 20) => ADC_DATA(59 downto 55),
+ ADC_DCO(1) => ADC_DCO(7),
+ ADC_DCO(5 downto 2) => ADC_DCO(12 downto 9),
+
+ DATA_OUT(1*CHANNELS*RESOLUTION-1 downto 0)
+ => adc_data_out(7*CHANNELS*RESOLUTION-1 downto 6*CHANNELS*RESOLUTION),
+ DATA_OUT(5*CHANNELS*RESOLUTION-1 downto 1*CHANNELS*RESOLUTION)
+ => adc_data_out(12*CHANNELS*RESOLUTION-1 downto 8*CHANNELS*RESOLUTION),
+ FCO_OUT(1*RESOLUTION-1 downto 0)
+ => adc_fco_out(7*RESOLUTION-1 downto 6*RESOLUTION),
+ FCO_OUT(5*RESOLUTION-1 downto 1*RESOLUTION)
+ => adc_fco_out(12*RESOLUTION-1 downto 8*RESOLUTION),
+
+ DATA_VALID_OUT(0) => adc_valid_out(6),
+ DATA_VALID_OUT(4 downto 1) => adc_valid_out(11 downto 8),
+
+ DEBUG(32*1*CHANNELS-1 downto 0)
+ => adc_debug(32*7*CHANNELS-1 downto 32*6*CHANNELS),
+ DEBUG(32*5*CHANNELS -1 downto 32*1*CHANNELS)
+ => adc_debug(32*12*CHANNELS-1 downto 32*8*CHANNELS)
+
+ );
+
+
+
+gen_data_fifo : for i in 0 to DEVICES*CHANNELS-1 generate
+ THE_FIFO : entity work.fifo_18x1k_oreg
+ port map (
+ Data(9 downto 0) => adc_data_out(10*i+9 downto 10*i),
+-- Data(17 downto 10) => ADC_FCO_IN (10*(i/CHANNELS)+7 downto 10*(i/CHANNELS)),
+ Data(17 downto 12) => adc_fco_out (10*(i/CHANNELS)+6 downto 10*(i/CHANNELS)+1),
+ Clock => CLK,
+ WrEn => fifo_write(i),
+ RdEn => fifo_read(i),
+ Reset => fifo_reset,
+ AmFullThresh => "1111110000",
+ Q => fifo_dout(i),
+ WCNT => fifo_count(i),
+ Empty => fifo_empty(i),
+ Full => open,
+ AlmostFull => fifo_full(i)
+ );
+ fifo_write(i) <= adc_valid_out(i / CHANNELS) and not fifo_stop;
+end generate;
+
+fifo_wait_1 <= fifo_wait_0 when rising_edge(CLK);
+fifo_wait_2 <= fifo_wait_1 when rising_edge(CLK);
+
+ADC_CONTROL_OUT <= ctrl_reg(7 downto 0);
+
+
+PROC_BUS : process begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+ adc_restart <= '0';
+ fifo_read <= fifo_full;
+ fifo_wait_0 <= '0';
+ fifo_reset <= '0';
+
+ if BUS_RX.read = '1' then
+ if BUS_RX.addr(7 downto 0) = x"80" then
+ BUS_TX.data <= ctrl_reg;
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"80"
+ and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then
+ BUS_TX.data <= adc_debug(to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32);
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) = x"83" then
+ BUS_TX.data <= (others => '0');
+ BUS_TX.data(10 downto 0) <= fifo_count(0);
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,8)) then
+ saved_addr <= to_integer(unsigned(BUS_RX.addr(6 downto 0)));
+ fifo_read(to_integer(unsigned(BUS_RX.addr(6 downto 0)))) <= '1';
+ fifo_wait_0 <= '1';
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+
+ elsif BUS_RX.write = '1' then
+ if BUS_RX.addr(7 downto 0) = x"80" then
+ ctrl_reg <= BUS_RX.data;
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) = x"81" then
+ adc_restart <= BUS_RX.data(0);
+ fifo_stop <= BUS_RX.data(1);
+ fifo_reset <= BUS_RX.data(2);
+ BUS_TX.ack <= '1';
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+ end if;
+
+ if fifo_wait_2 = '1' then
+ BUS_TX.ack <= '1';
+ BUS_TX.data(17 downto 0) <= fifo_dout(saved_addr);
+ BUS_TX.data(30 downto 18) <= (others => '0');
+ BUS_TX.data(31) <= fifo_empty(saved_addr);
+ end if;
+end process;
+
+
+end architecture;
+
+
+
add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd"
-add_file -vhdl -lib "work" "../base/code/adc_ad9219.vhd"
-add_file -vhdl -lib "work" "../base/code/adc_data_buffer.vhd"
+
+add_file -vhdl -lib "work" "source/adc_package.vhd"
+add_file -vhdl -lib "work" "source/adc_processor.vhd"
+add_file -vhdl -lib "work" "source/adc_ad9219.vhd"
+add_file -vhdl -lib "work" "source/adc_handler.vhd"
+add_file -vhdl -lib "work" "source/adc_slowcontrol_data_buffer.vhd"
+
add_file -vhdl -lib "work" "trb3_periph_adc.vhd"
--LVL1 channel
signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i : std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic;
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
- signal fee_data_i : std_logic_vector(31 downto 0);
- signal fee_data_write_i : std_logic;
- signal fee_data_finished_i : std_logic;
- signal fee_almost_full_i : std_logic;
--Slow Control channel
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal time_since_last_trg : std_logic_vector(31 downto 0);
signal timer_ticks : std_logic_vector(1 downto 0);
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
--SPI to MachXO FPGA (and LMK01010, and ADC SPI)
- signal spifpga_read_en : std_logic;
- signal spifpga_write_en : std_logic;
- signal spifpga_data_in : std_logic_vector(31 downto 0);
- signal spifpga_addr : std_logic_vector(4 downto 0);
- signal spifpga_data_out : std_logic_vector(31 downto 0);
- signal spifpga_ack : std_logic;
- signal spifpga_busy : std_logic;
-
- signal spi_cs : std_logic_vector(15 downto 0);
+ signal spi_cs : std_logic_vector(15 downto 0);
signal spi_sdi, spi_sdo, spi_sck : std_logic;
-
- signal clk_adcref_i : std_logic;
- signal debug_adc : std_logic_vector(48*32-1 downto 0);
- signal adc_restart_i : std_logic;
-
- signal adc_data : std_logic_vector(479 downto 0);
- signal adc_fco : std_logic_vector(119 downto 0);
- signal adc_data_valid : std_logic_vector(11 downto 0);
- signal adc_ctrl : std_logic_vector(31 downto 0);
+ signal adcspi_ctrl : std_logic_vector(7 downto 0);
signal busadc_rx : CTRLBUS_RX;
signal busadc_tx : CTRLBUS_TX;
+ signal busspi_rx : CTRLBUS_RX;
+ signal busspi_tx : CTRLBUS_TX;
+ signal busmem_rx : CTRLBUS_RX;
+ signal busmem_tx : CTRLBUS_TX;
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 11);
begin
---------------------------------------------------------------------------
REGIO_NUM_STAT_REGS => 0,
REGIO_NUM_CTRL_REGS => 0,
ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"48",
+ BROADCAST_BITMASK => x"ff",
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
REGIO_HARDWARE_VERSION => HARDWARE_INFO,
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13, --13
+ DATA_INTERFACE_NUMBER => 12,
+ DATA_BUFFER_DEPTH => 10,
DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12)
+ DATA_BUFFER_FULL_THRESH => 2**10-511,
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
CLK => clk_100_i,
RESET => reset_i,
CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_DATAREADY_OUT => med_dataready_out,
+ MED_DATA_OUT => med_data_out,
+ MED_PACKET_NUM_OUT => med_packet_num_out,
MED_READ_IN => med_read_in,
MED_DATAREADY_IN => med_dataready_in,
MED_DATA_IN => med_data_in,
MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
+ MED_READ_OUT => med_read_out,
MED_STAT_OP_IN => med_stat_op,
MED_CTRL_OP_OUT => med_ctrl_op,
-
+
--Timing trigger in
TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
--LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
+ LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid,
+ LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg,
+ LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg,
+ LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg,
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+ LVL1_TRG_TYPE_OUT => readout_rx.trg_type,
+ LVL1_TRG_NUMBER_OUT => readout_rx.trg_number,
+ LVL1_TRG_CODE_OUT => readout_rx.trg_code,
+ LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information,
+ LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number,
--Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+ TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple,
+ TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout,
+ TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious,
+ TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing,
+ TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
--Response from FEE
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
- FEE_DATA_IN => fee_data_i,
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
-
+ FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release,
+ FEE_TRG_STATUSBITS_IN(31 downto 0) => readout_tx(0).statusbits,
+ FEE_DATA_IN(31 downto 0) => readout_tx(0).data,
+ FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write,
+ FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished,
+ FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
+
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
---------------------------------------------------------------------------
-- AddOn
---------------------------------------------------------------------------
-THE_ADC : entity work.adc_ad9219
- generic map(
- CHANNELS => 4,
- DEVICES_LEFT => 7,
- DEVICES_RIGHT => 5,
- RESOLUTION => 10
- )
- port map(
- CLK => clk_100_i,
- CLK_ADCRAW => CLK_PCLK_RIGHT,
- RESTART_IN => adc_restart_i,
- ADCCLK_OUT => P_CLOCK,
-
- ADC_DATA( 4 downto 0) => ADC1_CH,
- ADC_DATA( 9 downto 5) => ADC2_CH,
- ADC_DATA(14 downto 10) => ADC3_CH,
- ADC_DATA(19 downto 15) => ADC4_CH,
- ADC_DATA(24 downto 20) => ADC5_CH,
- ADC_DATA(29 downto 25) => ADC6_CH,
- ADC_DATA(34 downto 30) => ADC7_CH,
- ADC_DATA(39 downto 35) => ADC8_CH,
- ADC_DATA(44 downto 40) => ADC9_CH,
- ADC_DATA(49 downto 45) => ADC10_CH,
- ADC_DATA(54 downto 50) => ADC11_CH,
- ADC_DATA(59 downto 55) => ADC12_CH,
-
- ADC_DCO => ADC_DCO,
-
- DATA_OUT => adc_data,
- FCO_OUT => adc_fco,
- DATA_VALID_OUT => adc_data_valid,
- DEBUG => debug_adc
- );
-
-
-THE_ADC_DATA_BUFFER : entity work.adc_data_buffer
- generic map(
- RESOLUTION => 10,
- CHANNELS => 4,
- DEVICES => 12
- )
- port map(
- CLK => clk_100_i,
- ADC_DATA_IN => adc_data,
- ADC_FCO_IN => adc_fco,
- ADC_DATA_VALID => adc_data_valid,
- ADC_STATUS_IN => debug_adc,
- ADC_CONTROL_OUT => adc_ctrl,
-
- ADC_RESET_OUT => adc_restart_i,
+gen_reallogic : if USE_DUMMY_READOUT = 0 generate
+ THE_ADC : entity work.adc_handler
+ port map(
+ CLK => clk_100_i,
+ CLK_ADCRAW => CLK_PCLK_RIGHT,
+
+ ADCCLK_OUT => P_CLOCK,
+ ADC_DATA( 4 downto 0) => ADC1_CH,
+ ADC_DATA( 9 downto 5) => ADC2_CH,
+ ADC_DATA(14 downto 10) => ADC3_CH,
+ ADC_DATA(19 downto 15) => ADC4_CH,
+ ADC_DATA(24 downto 20) => ADC5_CH,
+ ADC_DATA(29 downto 25) => ADC6_CH,
+ ADC_DATA(34 downto 30) => ADC7_CH,
+ ADC_DATA(39 downto 35) => ADC8_CH,
+ ADC_DATA(44 downto 40) => ADC9_CH,
+ ADC_DATA(49 downto 45) => ADC10_CH,
+ ADC_DATA(54 downto 50) => ADC11_CH,
+ ADC_DATA(59 downto 55) => ADC12_CH,
+ ADC_DCO => ADC_DCO,
+
+ TRIGGER_IN => TRIGGER_LEFT,
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
+ BUS_RX => busadc_rx,
+ BUS_TX => busadc_tx,
+
+ ADCSPI_CTRL => adcspi_ctrl
+ );
+end generate;
- BUS_RX => busadc_rx,
- BUS_TX => busadc_tx
+gen_dummyreadout : if USE_DUMMY_READOUT = 1 generate
+ THE_ADC : entity work.adc_slowcontrol_data_buffer
+ port map(
+ CLK => clk_100_i,
+ CLK_ADCRAW => CLK_PCLK_RIGHT,
+
+ ADCCLK_OUT => P_CLOCK,
+ ADC_DATA( 4 downto 0) => ADC1_CH,
+ ADC_DATA( 9 downto 5) => ADC2_CH,
+ ADC_DATA(14 downto 10) => ADC3_CH,
+ ADC_DATA(19 downto 15) => ADC4_CH,
+ ADC_DATA(24 downto 20) => ADC5_CH,
+ ADC_DATA(29 downto 25) => ADC6_CH,
+ ADC_DATA(34 downto 30) => ADC7_CH,
+ ADC_DATA(39 downto 35) => ADC8_CH,
+ ADC_DATA(44 downto 40) => ADC9_CH,
+ ADC_DATA(49 downto 45) => ADC10_CH,
+ ADC_DATA(54 downto 50) => ADC11_CH,
+ ADC_DATA(59 downto 55) => ADC12_CH,
+ ADC_DCO => ADC_DCO,
+
+ ADC_CONTROL_OUT => adcspi_ctrl,
+
+ BUS_RX => busadc_rx,
+ BUS_TX => busadc_tx
+ );
+end generate;
- );
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"e000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 8, others => 0)
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"a000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
)
port map(
CLK => clk_100_i,
DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
- --Bus Handler (SPI Flash control)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- --Bus Handler (SPI to FPGA)
- BUS_READ_ENABLE_OUT(1) => spifpga_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spifpga_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spifpga_data_in,
- BUS_ADDR_OUT(1*16+4 downto 1*16) => spifpga_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spifpga_data_out,
- BUS_DATAREADY_IN(1) => spifpga_ack,
- BUS_WRITE_ACK_IN(1) => spifpga_ack,
- BUS_NO_MORE_DATA_IN(1) => spifpga_busy,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
-
- BUS_READ_ENABLE_OUT(2) => busadc_rx.read,
- BUS_WRITE_ENABLE_OUT(2) => busadc_rx.write,
- BUS_DATA_OUT(2*32+31 downto 2*32) => busadc_rx.data,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => busadc_rx.addr,
- BUS_TIMEOUT_OUT(2) => busadc_rx.timeout,
- BUS_DATA_IN(2*32+31 downto 2*32) => busadc_tx.data,
- BUS_DATAREADY_IN(2) => busadc_tx.ack,
- BUS_WRITE_ACK_IN(2) => busadc_tx.ack,
- BUS_NO_MORE_DATA_IN(2) => busadc_tx.nack,
- BUS_UNKNOWN_ADDR_IN(2) => busadc_tx.unknown,
+ BUS_RX(0) => busmem_rx, --Flash
+ BUS_TX(0) => busmem_tx,
+ BUS_RX(1) => busspi_rx, --SPI
+ BUS_TX(1) => busspi_tx,
+ BUS_RX(2) => busadc_rx, --ADC
+ BUS_TX(2) => busadc_tx,
STAT_DEBUG => open
);
CLK_IN => clk_100_i,
RESET_IN => reset_i,
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
+ BUS_ADDR_IN => busmem_rx.addr(8 downto 0),
+ BUS_READ_IN => busmem_rx.read,
+ BUS_WRITE_IN => busmem_rx.write,
+ BUS_DATAREADY_OUT => busmem_tx.rack,
+ BUS_WRITE_ACK_OUT => busmem_tx.wack,
+ BUS_UNKNOWN_ADDR_OUT => busmem_tx.unknown,
+ BUS_NO_MORE_DATA_OUT => busmem_tx.nack,
+ BUS_DATA_IN => busmem_rx.data,
+ BUS_DATA_OUT => busmem_tx.data,
DO_REBOOT_IN => common_ctrl_reg(15),
PROGRAMN => PROGRAMN,
CLK_IN => clk_100_i,
RESET_IN => reset_i,
-- Slave bus
- BUS_READ_IN => spifpga_read_en,
- BUS_WRITE_IN => spifpga_write_en,
- BUS_BUSY_OUT => spifpga_busy,
- BUS_ACK_OUT => spifpga_ack,
- BUS_ADDR_IN => spifpga_addr,
- BUS_DATA_IN => spifpga_data_in,
- BUS_DATA_OUT => spifpga_data_out,
+ BUS_READ_IN => busspi_rx.read,
+ BUS_WRITE_IN => busspi_rx.write,
+ BUS_BUSY_OUT => busspi_tx.nack,
+ BUS_ACK_OUT => busspi_tx.ack,
+ BUS_ADDR_IN => busspi_rx.addr(4 downto 0),
+ BUS_DATA_IN => busspi_rx.data,
+ BUS_DATA_OUT => busspi_tx.data,
-- SPI connections
SPI_CS_OUT => spi_CS,
SPI_SDI_IN => spi_SDI,
FPGA_SDI(0) <= spi_SDO when spi_CS(2 downto 0) /= b"111" else '0';
spi_SDI <= FPGA_SDO(0) when spi_CS(2 downto 0) /= b"111" else '0';
- SPI_ADC_SCK <= spi_SCK when spi_CS(3) = '0' else adc_ctrl(4);
- SPI_ADC_SDIO <= spi_SDO when spi_CS(3) = '0' else adc_ctrl(5);
- FPGA_SCK(1) <= '0' when spi_CS(3) = '0' else adc_ctrl(6); --CSB
+ SPI_ADC_SCK <= spi_SCK when spi_CS(3) = '0' else adcspi_ctrl(4);
+ SPI_ADC_SDIO <= spi_SDO when spi_CS(3) = '0' else adcspi_ctrl(5);
+ FPGA_SCK(1) <= '0' when spi_CS(3) = '0' else adcspi_ctrl(6); --CSB
LMK_CLK <= spi_SCK when spi_CS(5 downto 4) /= b"11" else '1' ;
LMK_DATA <= spi_SDO when spi_CS(5 downto 4) /= b"11" else '0' ;
LMK_LE_1 <= spi_CS(4); -- active low
LMK_LE_2 <= spi_CS(5); -- active low
- POWER_ENABLE <= adc_ctrl(0);
+ POWER_ENABLE <= adcspi_ctrl(0);
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb3_components.all;
-
-entity adc_data_buffer is
- generic(
- CHANNELS : integer := 4;
- DEVICES : integer := 12;
- RESOLUTION : integer := 10
- );
- port(
- CLK : in std_logic;
-
- ADC_DATA_IN : in std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
- ADC_FCO_IN : in std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
- ADC_DATA_VALID : in std_logic_vector(DEVICES-1 downto 0);
- ADC_STATUS_IN : in std_logic_vector(DEVICES*CHANNELS*32-1 downto 0);
- ADC_CONTROL_OUT: out std_logic_vector(31 downto 0);
- ADC_RESET_OUT : out std_logic;
-
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX
- );
-end entity;
-
-
-
-architecture adc_data_buffer_arch of adc_data_buffer is
-
-signal fifo_read : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
-signal fifo_empty : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
-signal fifo_full : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
-signal fifo_write : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
-signal fifo_reset : std_logic;
-signal fifo_stop : std_logic;
-
-type dout_t is array(0 to DEVICES*CHANNELS-1) of std_logic_vector(17 downto 0);
-signal fifo_dout : dout_t;
-
-type fifo_count_t is array(0 to DEVICES*CHANNELS-1) of std_logic_vector(10 downto 0);
-signal fifo_count : fifo_count_t;
-
-signal ctrl_reg : std_logic_vector(31 downto 0);
-
-signal saved_addr : integer range 0 to DEVICES*CHANNELS-1;
-signal fifo_wait_0, fifo_wait_1, fifo_wait_2 : std_logic;
-
-begin
-
-
-gen_data_fifo : for i in 0 to DEVICES*CHANNELS-1 generate
- THE_FIFO : entity work.fifo_18x1k_oreg
- port map (
- Data(9 downto 0) => ADC_DATA_IN(10*i+9 downto 10*i),
--- Data(17 downto 10) => ADC_FCO_IN (10*(i/CHANNELS)+7 downto 10*(i/CHANNELS)),
- Data(17 downto 12) => ADC_FCO_IN (10*(i/CHANNELS)+6 downto 10*(i/CHANNELS)+1),
- Clock => CLK,
- WrEn => fifo_write(i),
- RdEn => fifo_read(i),
- Reset => fifo_reset,
- AmFullThresh => "1111110000",
- Q => fifo_dout(i),
- WCNT => fifo_count(i),
- Empty => fifo_empty(i),
- Full => open,
- AlmostFull => fifo_full(i)
- );
- fifo_write(i) <= ADC_DATA_VALID(i / CHANNELS) and not fifo_stop;
-end generate;
-
-fifo_wait_1 <= fifo_wait_0 when rising_edge(CLK);
-fifo_wait_2 <= fifo_wait_1 when rising_edge(CLK);
-
-ADC_CONTROL_OUT <= ctrl_reg;
-
-
-PROC_BUS : process begin
- wait until rising_edge(CLK);
- BUS_TX.ack <= '0';
- BUS_TX.nack <= '0';
- BUS_TX.unknown <= '0';
- ADC_RESET_OUT <= '0';
- fifo_read <= fifo_full;
- fifo_wait_0 <= '0';
- fifo_reset <= '0';
-
- if BUS_RX.read = '1' then
- if BUS_RX.addr(7 downto 0) = x"80" then
- BUS_TX.data <= ctrl_reg;
- BUS_TX.ack <= '1';
- elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"80"
- and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then
- BUS_TX.data <= ADC_STATUS_IN(to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32);
- BUS_TX.ack <= '1';
- elsif BUS_RX.addr(7 downto 0) = x"83" then
- BUS_TX.data <= (others => '0');
- BUS_TX.data(10 downto 0) <= fifo_count(0);
- BUS_TX.ack <= '1';
- elsif BUS_RX.addr(7 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,8)) then
- saved_addr <= to_integer(unsigned(BUS_RX.addr(6 downto 0)));
- fifo_read(to_integer(unsigned(BUS_RX.addr(6 downto 0)))) <= '1';
- fifo_wait_0 <= '1';
- else
- BUS_TX.unknown <= '1';
- end if;
-
- elsif BUS_RX.write = '1' then
- if BUS_RX.addr(7 downto 0) = x"80" then
- ctrl_reg <= BUS_RX.data;
- BUS_TX.ack <= '1';
- elsif BUS_RX.addr(7 downto 0) = x"81" then
- ADC_RESET_OUT <= BUS_RX.data(0);
- fifo_stop <= BUS_RX.data(1);
- fifo_reset <= BUS_RX.data(2);
- BUS_TX.ack <= '1';
- else
- BUS_TX.unknown <= '1';
- end if;
- end if;
-
- if fifo_wait_2 = '1' then
- BUS_TX.ack <= '1';
- BUS_TX.data(17 downto 0) <= fifo_dout(saved_addr);
- BUS_TX.data(30 downto 18) <= (others => '0');
- BUS_TX.data(31) <= fifo_empty(saved_addr);
- end if;
-end process;
-
-
-end architecture;
-
-
-
jspc29 / trb3.git / commitdiff