updated pulser design

diff --git a/.gitignore b/.gitignore
index 3bd1b81a571f15acdff6f8b216cb822c1908a4ea..398ed0a1114fb414161d51d65d54481d93b78d7a 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -32,3 +32,4 @@ modelsim.ini
 work
 *.wlf
 *stacktrace.txt
+*edn

diff --git a/base/trb3_periph_pulser.lpf b/base/trb3_periph_pulser.lpf
index 580a0e20b8a035d323362dd33487510ab9818395..21430c852a778315a571b2edc391fb826e0189b3 100644 (file)
--- a/base/trb3_periph_pulser.lpf
+++ b/base/trb3_periph_pulser.lpf
@@ -85,11 +85,11 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
 # TDC INPUTS
 #################################################################
 
-LOCATE COMP  "OUTP_0"    SITE "P1";  
-LOCATE COMP  "OUTP_1"    SITE "T2";  
-LOCATE COMP  "OUTP_2"    SITE "R1";  
-LOCATE COMP  "OUTP_3"    SITE "P5";  
-LOCATE COMP  "OUTP_4"    SITE "N5";  
+# LOCATE COMP  "OUTP_0"    SITE "P1";  
+# LOCATE COMP  "OUTP_1"    SITE "T2";  
+# LOCATE COMP  "OUTP_2"    SITE "R1";  
+# LOCATE COMP  "OUTP_3"    SITE "P5";  
+# LOCATE COMP  "OUTP_4"    SITE "N5";  
 
 
 
@@ -97,14 +97,14 @@ LOCATE COMP  "OUTP_4"    SITE "N5";
 # LOCATE COMP  "INP_1"    SITE "T2";  
 # LOCATE COMP  "INP_2"    SITE "R1";  
 # LOCATE COMP  "INP_3"    SITE "N3";  
-# LOCATE COMP  "OUTP_0"    SITE "P5";  
-# LOCATE COMP  "OUTP_1"    SITE "N5";   
+LOCATE COMP  "OUTP_0"    SITE "P5";  
+LOCATE COMP  "OUTP_1"    SITE "N5";   
 # LOCATE COMP  "INP_6"    SITE "AC2";
-# LOCATE COMP  "OUTP_2"    SITE "AB1";
+LOCATE COMP  "OUTP_2"    SITE "AB1";
 # LOCATE COMP  "INP_8"    SITE "AA1";
 # LOCATE COMP  "INP_9"    SITE "W7";
-# LOCATE COMP  "OUTP_3"    SITE "Y5";
-# LOCATE COMP  "OUTP_4"    SITE "V6";
+LOCATE COMP  "OUTP_3"    SITE "Y5";
+LOCATE COMP  "OUTP_4"    SITE "V6";
 # LOCATE COMP  "INP_12"   SITE "H2";
 # LOCATE COMP  "INP_13"   SITE "K3";
 # LOCATE COMP  "INP_14"   SITE "H1";
@@ -161,7 +161,8 @@ LOCATE COMP  "OUTP_4"    SITE "N5";
 # DEFINE PORT GROUP "INP_group" "INP*" ;
 # IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 DEFINE PORT GROUP "OUT_group" "OUT*" ;
-IOBUF GROUP "OUT_group" IO_TYPE=LVCMOS25;
+#IOBUF GROUP "OUT_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST DRIVE=12 PULLMODE=NONE;
+IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 ;
 
 #################################################################
 # Additional Lines to AddOn

diff --git a/pulser/compile_frankfurt.pl b/pulser/compile_frankfurt.pl
index 14139ab10d9a6f5cdb9a06648b5ed80fbfcbb260..96a0633d1d5c79d8686fa0258ee2507766819215 100755 (executable)
--- a/pulser/compile_frankfurt.pl
+++ b/pulser/compile_frankfurt.pl
@@ -133,7 +133,7 @@ $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 # TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -u 15 -fullname -gt -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;

diff --git a/pulser/pulserddrecp3.vhd b/pulser/pulserddrecp3.vhd
index c8d17685e4d4a1db149dd763ab898c300cd4ddf8..e0c3cd0bd496419ec16afd6a3f33220d55af2113 100644 (file)
--- a/pulser/pulserddrecp3.vhd
+++ b/pulser/pulserddrecp3.vhd
@@ -136,10 +136,10 @@ architecture Structure of pulserddrecp3 is
     attribute ODDRAPPS of Inst_ODDRX2D_0_2 : label is "ECLK_ALIGNED";
     attribute ODDRAPPS of Inst_ODDRX2D_0_1 : label is "ECLK_ALIGNED";
     attribute ODDRAPPS of Inst_ODDRX2D_0_0 : label is "ECLK_ALIGNED";
-    attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "250.000000";
-    attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "250.000000";
-    attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "125.000000";
-    attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKOP of Inst2_EHXPLLF : label is "400.000000";
+    attribute FREQUENCY_PIN_CLKOS of Inst2_EHXPLLF : label is "400.000000";
+    attribute FREQUENCY_PIN_CLKI of Inst2_EHXPLLF : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKOK of Inst2_EHXPLLF : label is "200.000000";
     attribute IO_TYPE of Inst1_OBZ4 : label is "LVDS25";
     attribute IO_TYPE of Inst1_OBZ3 : label is "LVDS25";
     attribute IO_TYPE of Inst1_OBZ2 : label is "LVDS25";
@@ -171,12 +171,12 @@ begin
     Inst_ODDRX2D_0_1: ODDRX2D
         generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
         port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), 
-            SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo1);
+            SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo1);
 
     Inst_ODDRX2D_0_0: ODDRX2D
         generic map (MEMMODE=> "DISABLED", ISI_CAL=> "BYPASS")
         port map (DA0=>din(0), DB0=>din(1), DA1=>din(2), DB1=>din(3), 
-            SCLK=>sclk_t, DQCLK1=>dqclk10, DQCLK0=>dqclk00, Q=>buf_qo0);
+            SCLK=>sclk_t, DQCLK1=>dqclk11, DQCLK0=>dqclk01, Q=>buf_qo0);
 
     Inst7_DQSBUFE11: DQSBUFE1
         generic map (DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
@@ -223,7 +223,7 @@ begin
         CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
         PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
         CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  2, CLKI_DIV=>  1, 
-        FIN=> "125.000000")
+        FIN=> "200.000000")
         port map (CLKI=>clk, CLKFB=>clkintfb, RST=>pll_reset, 
             RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
             DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 

diff --git a/pulser/trb3_periph.vhd b/pulser/trb3_periph.vhd
index 9fff1d132bb06c995e88ba79cdab18626ab02740..a7ee6ee9610657604e3d81689bbe5a0fd76af6c5 100644 (file)
--- a/pulser/trb3_periph.vhd
+++ b/pulser/trb3_periph.vhd
@@ -180,10 +180,10 @@ begin
 ---------------------------------------------------------------------------
   THE_MAIN_PLL : pll_in200_out100
     port map(
-      CLK   => CLK_PCLK_RIGHT,
+      CLK   => clk_200_i,
       RESET => '0',
       CLKOP => clk_100_i,
-      CLKOK => clk_200_i,
+      CLKOK => open,
       LOCK  => pll_lock
       );
 
@@ -349,14 +349,15 @@ end generate;
 ---------------------------------------------------------------------------
 -- Pulser
 ---------------------------------------------------------------------------
- tristate_i <= "01010";
+ tristate_i <= "00000";
 --just generating some test output
-timer <= timer + 1 when rising_edge(clk_125_i);
+timer <= timer + 1 when rising_edge(clk_200_i);
 process begin
-  wait until rising_edge(clk_125_i);
-  if    timer = x"01" then   din_i <= x"3";
-  elsif timer = x"02" then   din_i <= x"f";
-  elsif timer = x"03" then   din_i <= x"1";
+  wait until rising_edge(clk_200_i);
+  if    timer = x"01" then   din_i <= x"1";
+  elsif timer = x"02" then   din_i <= x"0";
+  elsif timer = x"03" then   din_i <= x"0";
+  elsif timer = x"80" then   din_i <= x"f";
   else                       din_i <= x"0";
   end if;  
 end process;  
@@ -364,11 +365,11 @@ end process;
 
   THE_DDR: pulserddrecp3
     port map(
-        clk    => CLK_GPLL_LEFT,
+        clk    => CLK_PCLK_LEFT,
         pll_lock => open,
         pll_reset => '0',
         reset => '0',
-        sclk  => clk_125_i,
+        sclk  => clk_200_i,
         tristate => tristate_i,
         din => din_i,
         q   => OUTP

diff --git a/pulser/trb3_periph_constraints.lpf b/pulser/trb3_periph_constraints.lpf
index 7b127a5008a923ac0eb55d9b79cfdcccdc523939..bb534d0d9467fe99dd4799d83e5bcb5f14d92754 100644 (file)
--- a/pulser/trb3_periph_constraints.lpf
+++ b/pulser/trb3_periph_constraints.lpf
@@ -9,9 +9,9 @@ BLOCK RD_DURING_WR_PATHS ;
 SYSCONFIG MCCLK_FREQ = 20;
 
 FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-#FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-#FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-#FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
   
 #################################################################
 # Reset Nets