;mvc_lib = $MODEL_TECH/../mvc_lib
work = work
+ecp3 = /d/jspc29/lattice/diamond/3.2_x64/ispfpga/vhdl/data/ecp3/mti/work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 10
+Project_Files_Count = 11
Project_File_0 = ../../base/trb3_components.vhd
-Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417453875 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_1 = dummyADC.vhd
-Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1413789500 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_2 = ../config.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417829973 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_3 = txt_util.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1412580230 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_4 = tb_adcprocessor.vhd
-Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417505324 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_5 = ../source/adc_processor.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417829973 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_6 = ../source/adc_package.vhd
-Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417829973 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_7 = version.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418045516 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_8 = ../../../trbnet/trb_net_components.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1407154210 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_9 = ../../../trbnet/trb_net_std.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417012890 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418724991 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_1 = ../config.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1417783704 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_2 = ../source/adc_processor.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418835675 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_3 = ../../../trbnet/trb_net_components.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1406911647 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = dummyADC.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418831126 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = tb_adcprocessor.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418825986 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_6 = ../../../trbnet/trb_net_std.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409927354 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_7 = /d/jspc22/trb/git/trb3/ADC/cores/mulacc2.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418830031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_8 = txt_util.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409066711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_9 = ../source/adc_package.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418320381 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_10 = version.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418724991 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick =
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick =
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
-Project_Minor_Version = 0
+Project_Minor_Version = 1
variable s : std_logic_vector(47 downto 0);
variable toggle : std_logic := '0';
variable s1, s2, s3, s4 : std_logic_vector(9 downto 0);
+variable cnt : unsigned(9 downto 0) := (others => '0');
file stimulus: TEXT;
begin
UNIFORM(seed1, seed2, rand);
random4 := to_unsigned(INTEGER(TRUNC(rand*randrange*2.0)),10);
-
s1 := std_logic_vector(unsigned(s( 9 downto 0))+random1-to_unsigned(integer(randrange),10));
s2 := std_logic_vector(unsigned(s(21 downto 12))+random2-to_unsigned(integer(randrange),10));
s3 := std_logic_vector(unsigned(s(33 downto 24))+random3-to_unsigned(integer(randrange),10));
s4 := std_logic_vector(unsigned(s(45 downto 36))+random4-to_unsigned(integer(randrange),10));
+ s1 := std_logic_vector(cnt);
+ cnt := cnt + 1;
DATA <= s4 & s3 & s2 & s1;
VALID <= '1';
CONTROL : in std_logic_vector(63 downto 0);
CONFIG : in cfg_t;
-
+ PSA_DATA : in std_logic_vector(8 downto 0);
+ PSA_DATA_OUT : out std_logic_vector(8 downto 0);
+ PSA_WRITE : in std_logic;
+ PSA_ADDR : in std_logic_vector(7 downto 0);
+
DEBUG_BUFFER_READ : in std_logic;
DEBUG_BUFFER_ADDR : in std_logic_vector(4 downto 0);
DEBUG_BUFFER_DATA : out std_logic_vector(31 downto 0);
signal readout_tx : READOUT_TX;
signal control : std_logic_vector(63 downto 0);
+signal psa_data : std_logic_vector(8 downto 0);
+signal psa_write : std_logic;
+signal psa_addr : std_logic_vector(7 downto 0);
+
begin
clock <= not clock after 5 ns;
config.trigger_enable <= x"0000_0000_0000", x"ffff_ffff_fff1" after 5 us;
config.baseline_always_on <= '0'; --'1', '0' after 10 us;
-
+config.processing_mode <= 1;
config.buffer_depth <= to_unsigned(24 ,11);
config.samples_after <= to_unsigned(8 ,11);
config.block_count <= to_unsigned(2 , 2);
config.trigger_threshold <= to_unsigned(40 ,18);
config.readout_threshold <= to_unsigned(40 ,18);
config.presum <= to_unsigned(0 , 8);
-config.averaging <= to_unsigned(8 , 4);
-config.block_avg(0) <= to_unsigned(1 , 8);
+config.averaging <= to_unsigned(6 , 4);
+config.block_avg(0) <= to_unsigned(4 , 8);
config.block_avg(1) <= to_unsigned(1 , 8);
config.block_avg(2) <= to_unsigned(1 , 8);
config.block_avg(3) <= to_unsigned(1 , 8);
-config.block_sums(0) <= to_unsigned(15 , 8);
+config.block_sums(0) <= to_unsigned(5 , 8);
config.block_sums(1) <= to_unsigned(7 , 8);
config.block_sums(2) <= to_unsigned(4 , 8);
config.block_sums(3) <= to_unsigned(2 , 8);
config.block_scale(1) <= to_unsigned(0 , 8);
config.block_scale(2) <= to_unsigned(0 , 8);
config.block_scale(3) <= to_unsigned(0 , 8);
-config.baseline_reset_value <= to_unsigned(1023*32, 32);
+config.baseline_reset_value <= to_unsigned(2**6*1024-1, 32);
config.channel_disable <= (others => '0');
config.check_word1 <= (others => '0');
config.check_word2 <= (others => '0');
control <= (others => '0'), (8 => '1',others => '0') after 1 us, (others => '0') after 1.01 us,(5 => '1',others => '0') after 5 us, (others => '0') after 5.01 us ;
+proc_write_psa : process begin
+ wait for 1 us;
+ wait until rising_edge(clock); wait for 0.5 ns;
+ psa_write <= '1';
+ psa_addr <= x"00";
+ psa_data <= "0"&x"01";
+ wait until rising_edge(clock); wait for 0.5 ns;
+ psa_addr <= x"01";
+ psa_data <= "0"&x"02";
+ wait until rising_edge(clock); wait for 0.5 ns;
+ psa_addr <= x"02";
+ psa_data <= "0"&x"03";
+ wait until rising_edge(clock); wait for 0.5 ns;
+ psa_addr <= x"03";
+ psa_data <= "1"&x"ff";
+ wait until rising_edge(clock); wait for 0.5 ns;
+ psa_write <= '0';
+ wait;
+end process;
+
+
proc_rdo : process begin
readout_rx.data_valid <= '0';
readout_rx.valid_timing_trg <= '0';
readout_rx.valid_timing_trg <= '1';
wait until rising_edge(clock); wait for 0.5 ns;
readout_rx.valid_timing_trg <= '0';
- wait for 300 ns; wait until rising_edge(clock); wait for 0.5 ns;
+ wait for 250 ns; wait until rising_edge(clock); wait for 0.5 ns;
readout_rx.data_valid <= '1';
wait until readout_tx.busy_release = '1';
wait for 10 ns; wait until rising_edge(clock); wait for 0.5 ns;
CONTROL => control,
CONFIG => config,
+
+ PSA_DATA => psa_data,
+ PSA_DATA_OUT => open,
+ PSA_ADDR => psa_addr,
+ PSA_WRITE => psa_write,
DEBUG_BUFFER_READ => '0',
DEBUG_BUFFER_ADDR => (others => '0'),
add wave -noupdate -radix hexadecimal /tb/UUT/reg2_ram_remove
add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/ram_data_out(0)(17) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(16) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(15) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(14) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(13) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(12) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(11) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(10) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(9) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(8) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(7) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(6) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(5) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(4) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(3) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(2) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(1) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/ram_data_out(0)(17) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(16) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(15) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(14) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(13) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(12) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(11) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(10) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(9) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(8) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(7) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(6) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(5) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(4) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(3) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(2) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(1) {-height 16 -radix hexadecimal} /tb/UUT/ram_data_out(0)(0) {-height 16 -radix hexadecimal}} /tb/UUT/ram_data_out(0)
add wave -noupdate -divider Baseline
+add wave -noupdate /tb/UUT/ram_read
+add wave -noupdate /tb/UUT/baseline_reset
add wave -noupdate -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/UUT/baseline(0)
add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline(0) -radix hexadecimal} {/tb/UUT/baseline(1) -radix hexadecimal} {/tb/UUT/baseline(2) -radix hexadecimal} {/tb/UUT/baseline(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline(0) {-height 16 -radix hexadecimal} /tb/UUT/baseline(1) {-height 16 -radix hexadecimal} /tb/UUT/baseline(2) {-height 16 -radix hexadecimal} /tb/UUT/baseline(3) {-height 16 -radix hexadecimal}} /tb/UUT/baseline
add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline_averages(0) -radix hexadecimal} {/tb/UUT/baseline_averages(1) -radix hexadecimal} {/tb/UUT/baseline_averages(2) -radix hexadecimal} {/tb/UUT/baseline_averages(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline_averages(0) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(1) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(2) {-height 16 -radix hexadecimal} /tb/UUT/baseline_averages(3) {-height 16 -radix hexadecimal}} /tb/UUT/baseline_averages
-add wave -noupdate -expand /tb/UUT/readout_flag
-add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/thresh_counter(3) -radix hexadecimal} {/tb/UUT/thresh_counter(2) -radix hexadecimal} {/tb/UUT/thresh_counter(1) -radix hexadecimal} {/tb/UUT/thresh_counter(0) -radix hexadecimal}} -expand -subitemconfig {/tb/UUT/thresh_counter(3) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(2) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(1) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(0) {-height 16 -radix hexadecimal}} /tb/UUT/thresh_counter
+add wave -noupdate /tb/UUT/readout_flag
+add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/thresh_counter(3) -radix hexadecimal} {/tb/UUT/thresh_counter(2) -radix hexadecimal} {/tb/UUT/thresh_counter(1) -radix hexadecimal} {/tb/UUT/thresh_counter(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/thresh_counter(3) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(2) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(1) {-height 16 -radix hexadecimal} /tb/UUT/thresh_counter(0) {-height 16 -radix hexadecimal}} /tb/UUT/thresh_counter
add wave -noupdate -divider Readout
add wave -noupdate /tb/UUT/READOUT_RX.data_valid
add wave -noupdate /tb/UUT/READOUT_RX.valid_timing_trg
add wave -noupdate -radix hexadecimal /tb/UUT/RDO_data_proc
add wave -noupdate /tb/UUT/READOUT_TX.data_finished
add wave -noupdate /tb/UUT/READOUT_TX.busy_release
+add wave -noupdate -divider PSA
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_adcdata
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_ram_out
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_output
+add wave -noupdate /tb/UUT/ram_read_psa
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_addr_i
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_clear
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_data_i
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_enable
+add wave -noupdate -radix hexadecimal /tb/UUT/psa_pointer
+add wave -noupdate /tb/UUT/psa_state
+add wave -noupdate -divider MULACC
+add wave -noupdate /tb/UUT/THE_MULACC/Aclr
+add wave -noupdate /tb/UUT/THE_MULACC/ClkEn
+add wave -noupdate -radix hexadecimal /tb/UUT/THE_MULACC/DataA
+add wave -noupdate -radix hexadecimal /tb/UUT/THE_MULACC/DataB
+add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/THE_MULACC/Result(25) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(24) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(23) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(22) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(21) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(20) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(19) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(18) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(17) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(16) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(15) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(14) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(13) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(12) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(11) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(10) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(9) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(8) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(7) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(6) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(5) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(4) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(3) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(2) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(1) -radix hexadecimal} {/tb/UUT/THE_MULACC/Result(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/THE_MULACC/Result(25) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(24) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(23) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(22) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(21) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(20) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(19) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(18) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(17) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(16) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(15) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(14) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(13) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(12) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(11) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(10) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(9) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(8) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(7) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(6) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(5) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(4) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(3) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(2) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(1) {-height 16 -radix hexadecimal} /tb/UUT/THE_MULACC/Result(0) {-height 16 -radix hexadecimal}} /tb/UUT/THE_MULACC/Result
add wave -noupdate -divider -height 100 Config
-add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/CONFIG.buffer_depth -radix hexadecimal} {/tb/UUT/CONFIG.samples_after -radix hexadecimal} {/tb/UUT/CONFIG.block_count -radix hexadecimal} {/tb/UUT/CONFIG.trigger_threshold -radix hexadecimal} {/tb/UUT/CONFIG.readout_threshold -radix hexadecimal} {/tb/UUT/CONFIG.presum -radix hexadecimal} {/tb/UUT/CONFIG.averaging -radix hexadecimal} {/tb/UUT/CONFIG.trigger_enable -radix hexadecimal} {/tb/UUT/CONFIG.baseline_always_on -radix hexadecimal} {/tb/UUT/CONFIG.baseline_reset_value -radix hexadecimal} {/tb/UUT/CONFIG.block_avg -radix hexadecimal} {/tb/UUT/CONFIG.block_sums -radix hexadecimal} {/tb/UUT/CONFIG.block_scale -radix hexadecimal}} -subitemconfig {/tb/UUT/CONFIG.buffer_depth {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.samples_after {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_count {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.readout_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.presum {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.averaging {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_enable {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_always_on {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_reset_value {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_avg {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_sums {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_scale {-height 16 -radix hexadecimal}} /tb/UUT/CONFIG
+add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/CONFIG.processing_mode -radix hexadecimal} {/tb/UUT/CONFIG.buffer_depth -radix hexadecimal} {/tb/UUT/CONFIG.samples_after -radix hexadecimal} {/tb/UUT/CONFIG.block_count -radix hexadecimal} {/tb/UUT/CONFIG.trigger_threshold -radix hexadecimal} {/tb/UUT/CONFIG.readout_threshold -radix hexadecimal} {/tb/UUT/CONFIG.presum -radix hexadecimal} {/tb/UUT/CONFIG.averaging -radix hexadecimal} {/tb/UUT/CONFIG.trigger_enable -radix hexadecimal} {/tb/UUT/CONFIG.channel_disable -radix hexadecimal} {/tb/UUT/CONFIG.baseline_always_on -radix hexadecimal} {/tb/UUT/CONFIG.baseline_reset_value -radix hexadecimal} {/tb/UUT/CONFIG.block_avg -radix hexadecimal} {/tb/UUT/CONFIG.block_sums -radix hexadecimal} {/tb/UUT/CONFIG.block_scale -radix hexadecimal} {/tb/UUT/CONFIG.check_word1 -radix hexadecimal} {/tb/UUT/CONFIG.check_word2 -radix hexadecimal} {/tb/UUT/CONFIG.check_word_enable -radix hexadecimal}} -subitemconfig {/tb/UUT/CONFIG.processing_mode {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.buffer_depth {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.samples_after {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_count {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.readout_threshold {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.presum {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.averaging {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.trigger_enable {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.channel_disable {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_always_on {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.baseline_reset_value {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_avg {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_sums {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.block_scale {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.check_word1 {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.check_word2 {-height 16 -radix hexadecimal} /tb/UUT/CONFIG.check_word_enable {-height 16 -radix hexadecimal}} /tb/UUT/CONFIG
add wave -noupdate /tb/UUT/TRIGGER_OUT
add wave -noupdate -expand /tb/UUT/trigger_gen
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {16520 ns} 0}
+WaveRestoreCursors {{Cursor 1} {15187 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 107
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {16394 ns} {17102 ns}
+WaveRestoreZoom {15092 ns} {15308 ns}
attribute syn_hier : string;
attribute syn_hier of adc_handler_arch : architecture is "hard";
+type psa_data_t is array(0 to DEVICES-1) of std_logic_vector(8 downto 0);
+
signal adc_data_out : std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
signal adc_fco_out : std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
signal adc_valid_out : std_logic_vector(DEVICES-1 downto 0);
signal buffer_ready : std_logic_vector(DEVICES-1 downto 0);
signal buffer_device : integer range 0 to DEVICES-1;
+signal psa_data : std_logic_vector(8 downto 0);
+signal psa_data_out : psa_data_t;
+signal psa_write : std_logic;
+signal psa_addr : std_logic_vector(7 downto 0);
+
type arr_4_32_t is array (0 to 3) of unsigned(31 downto 0);
signal baseline_reset_value : arr_4_32_t := (others => (others => '0'));
-- 000 - 0ff configuration
-- 000 reset, buffer clear strobes
-- 001 buffer control reg
--- 002 - 003 trigger generation channel enable
-- 010 buffer depth (1-1023)
-- 011 number of samples after trigger arrived (0-1023 * 25ns)
-- 012 number of blocks to process (1-4)
-- 014 read-out threshold (0-1023 from baseline, polarity)
-- 015 number of values to sum before storing
-- 016 baseline averaging (2**N)
+-- 017 - 018 trigger generation channel enable
+-- 019 check words
+-- 01a - 01b channel disable
+-- 01c processing mode: 0: normal block mode, 1: pulse shape processing
-- 020 - 023 number of values to sum (1-255)
-- 024 - 027 number of sums (1-255)
-- 028 - 02b 2^k scaling factor (0-8)
-- 100 clock valid (1 bit per ADC)
-- 101 fco valid (1 bit per ADC)
-- 102 readout state
+-- 200 - 2ff pulse shape multiplicators
-- 800 - 83f last ADC values (local 0x0 - 0x3)
-- 840 - 87f long-term average / baseline (local 0x4 - 0x7)
-- 880 - 8bf fifo access (debugging only) (local 0x8 - 0xb)
+-- 8c0 - 8ff invalid word count (local 0xc - 0xf)
-- 900 - 9ff processor registers (local 0x10 - 0x1f)
CONTROL(63 downto 32) => buffer_ctrl_reg,
CONFIG => config, --trigger offset, zero sup offset, depth,
+ PSA_DATA => psa_data,
+ PSA_DATA_OUT => psa_data_out(i),
+ PSA_ADDR => psa_addr,
+ PSA_WRITE => psa_write,
+
DEBUG_BUFFER_ADDR => buffer_addr,
DEBUG_BUFFER_READ => buffer_read(i),
DEBUG_BUFFER_DATA => buffer_data(i),
BUS_TX.unknown <= '0';
buffer_read <= (others => '0');
strobe_reg <= (others => '0');
+ psa_write <= '0';
if or_all(buffer_ready) = '1' then
BUS_TX.data <= buffer_data(buffer_device);
BUS_TX.ack <= '1';
BUS_TX.data(31) <= config.check_word_enable;
when x"1a" => BUS_TX.data(31 downto 0) <= config.channel_disable(31 downto 0);
when x"1b" => BUS_TX.data(15 downto 0) <= config.channel_disable(47 downto 32);
+ when x"1c" => BUS_TX.data(1 downto 0) <= std_logic_vector(to_unsigned(config.processing_mode,2));
when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end case;
elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then
when x"19" => config.check_word1 <= BUS_RX.data(RESOLUTION-1 downto 0);
config.check_word2 <= BUS_RX.data(RESOLUTION-1+16 downto 16);
config.check_word_enable <= BUS_RX.data(31);
- when x"1a" => config.channel_disable(31 downto 0) <= BUS_RX.data(31 downto 0);
- when x"1b" => config.channel_disable(47 downto 32) <= BUS_RX.data(15 downto 0);
+ when x"1a" => config.channel_disable(31 downto 0) <= BUS_RX.data(31 downto 0);
+ when x"1b" => config.channel_disable(47 downto 32) <= BUS_RX.data(15 downto 0);
+ when x"1c" => config.processing_mode <= to_integer(unsigned(BUS_RX.data(1 downto 0)));
when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end case;
elsif BUS_RX.addr >= x"0020" and BUS_RX.addr <= x"002f" then
elsif BUS_RX.addr = x"0080" then
ctrl_reg <= BUS_RX.data;
BUS_TX.ack <= '1';
+ elsif BUS_RX.addr >= x"0200" and BUS_RX.addr <= x"02FF" then
+ psa_data <= BUS_RX.data(8 downto 0);
+ psa_write <= '1';
+ psa_addr <= BUS_RX.addr(7 downto 0);
+ BUS_TX.ack <= '1';
else
BUS_TX.unknown <= '1';
end if;
type cfg_t is record
+ processing_mode : integer range 0 to 3; --0: normal block processing, 1: pulse shape processing
buffer_depth : unsigned(10 downto 0);
samples_after : unsigned(10 downto 0);
block_count : unsigned( 1 downto 0);
CONTROL : in std_logic_vector(63 downto 0);
CONFIG : in cfg_t;
-
+
+ PSA_DATA : in std_logic_vector(8 downto 0);
+ PSA_DATA_OUT : out std_logic_vector(8 downto 0);
+ PSA_WRITE : in std_logic;
+ PSA_ADDR : in std_logic_vector(7 downto 0);
+
DEBUG_BUFFER_READ : in std_logic;
DEBUG_BUFFER_ADDR : in std_logic_vector(4 downto 0);
DEBUG_BUFFER_DATA : out std_logic_vector(31 downto 0);
type ram_arr_t is array (0 to 3) of ram_t;
type arr_values_t is array (0 to CHANNELS-1) of unsigned(15 downto 0);
type arr_CHAN_RES_t is array (0 to CHANNELS-1) of unsigned(31 downto 0);
+type psa_ram_t is array (0 to 256) of std_logic_vector(8 downto 0);
signal ram : ram_arr_t := (others => (others => (others => '0')));
attribute syn_ramstyle of ram : signal is "block_ram";
signal reg_buffer_read : std_logic;
signal last_ramread : std_logic := '0';
signal ram_valid : std_logic := '0';
+signal ram_rd_move : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+signal ram_rd_move_value : unsigned(9 downto 0) := (others => '0');
signal CONF : cfg_t;
attribute syn_keep of CONF : signal is true;
signal after_trg_cnt : unsigned(11 downto 0) := (others => '1');
-type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, START, SEND_STATUS, READOUT);
+type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, START, SEND_STATUS, READOUT, PSA_READOUT);
signal state : state_t;
signal statebits : std_logic_vector(7 downto 0);
signal word_counter : unsigned(7 downto 0);
signal readout_state : rdo_state_t;
signal rdostatebits : std_logic_vector(3 downto 0);
signal readout_finished : std_logic := '0';
+signal readout_psa_finished : std_logic := '0';
signal channelselect, last_channelselect, channelselect_valid : integer range 0 to 3 := 0;
signal prepare_header, last_prepare_header, prepare_header_valid : std_logic := '0';
signal blockcurrent, last_blockcurrent : integer range 0 to 3 := 0;
signal myavg : unsigned(7 downto 0);
+signal ram_read_rdo : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+
+signal psa_data_i : std_logic_vector(8 downto 0);
+signal psa_write_i : std_logic;
+signal psa_addr_i : std_logic_vector(7 downto 0);
+signal psa_ram : psa_ram_t := (others => (others => '0'));
+signal psa_ram_out, psa_ram_out_t : std_logic_vector(8 downto 0);
+signal psa_ram_out_ti : std_logic_vector(8 downto 0);
+signal psa_output : std_logic_vector(40 downto 0);
+signal psa_clear : std_logic;
+signal psa_enable : std_logic;
+signal psa_pointer : integer range 0 to 256 := 0;
+signal ram_read_psa : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+type psa_state_t is (PSA_IDLE, PSA_START_CHANNEL, PSA_WAIT_RAM, PSA_WAIT_RAM2, PSA_CALC, PSA_WAITWRITE, PSA_WAITWRITE2, PSA_DOWRITE, PSA_FINISH, PSA_WAIT_AFTER);
+signal psa_state : psa_state_t := PSA_IDLE;
+signal psa_adcdata : std_logic_vector(15 downto 0);
+signal RDO_write_psa : std_logic := '0';
+signal RDO_data_psa : std_logic_vector(31 downto 0) := (others => '0');
+
signal invalid_word_count : arr_CHAN_RES_t := (others => (others => '0'));
when "01" => DEBUG_BUFFER_DATA(15 downto 0) <= std_logic_vector(baseline(c));
when "10" => DEBUG_BUFFER_DATA(17 downto 0) <= std_logic_vector(reg_ram_data_out(to_integer(unsigned(reg_buffer_addr(1 downto 0)))));
ram_debug_read(to_integer(unsigned(reg_buffer_addr(1 downto 0)))) <= '1';
- when "11" =>
- DEBUG_BUFFER_DATA <= std_logic_vector(invalid_word_count(c));
+ when "11" => DEBUG_BUFFER_DATA <= std_logic_vector(invalid_word_count(c));
when others => null;
end case;
else
ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
elsif ram_remove = '1' then
ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
+ elsif ram_rd_move(i) = '1' then
+ ram_rd_pointer(i) <= ram_rd_pointer(i) - ram_rd_move_value;
end if;
end process;
end generate;
+-------------------------------------------------------------------------------
+-- Memory for PSA coefficients
+-------------------------------------------------------------------------------
+psa_write_i <= PSA_WRITE when rising_edge(CLK);
+psa_addr_i <= PSA_ADDR when rising_edge(CLK);
+psa_data_i <= PSA_DATA when rising_edge(CLK);
+PSA_DATA_OUT<= psa_ram_out_ti when rising_edge(CLK);
+psa_ram_out <= psa_ram_out_t when rising_edge(CLK);
+
+THE_PSA_MEMORY: process begin
+ wait until rising_edge(CLK);
+ if psa_write_i = '1' then
+ psa_ram(to_integer(unsigned('0' & psa_addr_i))) <= psa_data_i;
+ end if;
+ psa_ram_out_ti <= psa_ram(to_integer(unsigned('0' & psa_addr_i)));
+ psa_ram_out_t <= psa_ram(psa_pointer);
+end process;
+
+-------------------------------------------------------------------------------
+-- Multiply Accumulate for PSA
+-------------------------------------------------------------------------------
+THE_MULACC : entity work.mulacc2
+ port map(
+ CLK0 => CLK,
+ CE0 => psa_enable,
+ RST0 => psa_clear,
+ ACCUMSLOAD => '0',
+ A => psa_ram_out,
+ B => psa_adcdata,
+ LD => (others => '0'),
+ OVERFLOW => open,
+ ACCUM => psa_output
+ );
+
-------------------------------------------------------------------------------
-- Readout State Machine
-------------------------------------------------------------------------------
end if;
when START =>
- if stop_writing_rdo = '1' then
+ if stop_writing_rdo = '1' and CONF.processing_mode = 0 then
state <= READOUT;
+ elsif stop_writing_rdo = '1' and CONF.processing_mode = 1 then
+ state <= PSA_READOUT;
end if;
when READOUT =>
if readout_finished = '1' then
state <= RELEASE_DIRECT;
end if;
+
+ when PSA_READOUT =>
+ if readout_psa_finished = '1' then
+ state <= RELEASE_DIRECT;
+ end if;
when SEND_STATUS =>
RDO_write_main <= '1';
begin
wait until rising_edge(CLK);
readout_finished <= '0';
- ram_read <= (others => '0');
+ ram_read_rdo <= (others => '0');
prepare_header <= '0';
case readout_state is
end if;
when READ_CHANNEL =>
- ram_read(channelselect) <= '1';
+ ram_read_rdo(channelselect) <= '1';
if readcount = 1 or ram_count(channelselect) = 1 then
if blockcurrent < to_integer(CONF.block_count)-1 then
readout_state <= NEXT_BLOCK;
readout_state <= RDO_IDLE;
end case;
-
-
end process;
last_ramread <= ram_read(channelselect) when rising_edge(CLK);
cnt := 0;
end if;
- if ram_valid = '1' then
+ if ram_valid = '1' and readout_state /= RDO_IDLE then
if cnt = 0 then
RDO_data_proc(15 downto 0) <= std_logic_vector(reg_ram_data_out(channelselect_valid)(15 downto 0));
RDO_data_proc(19 downto 16) <= std_logic_vector(to_unsigned(channelselect_valid,4));
cnt := cnt + 1;
end if;
end if;
+
+ if readout_state = RDO_IDLE then
+ RDO_data_proc <= (others => '0');
+ RDO_write_proc <= '0';
+ end if;
end process;
+-------------------------------------------------------------------------------
+-- Data Reading State Machine
+-------------------------------------------------------------------------------
+PROC_PULSE_SHAPE_READOUT : process
+ variable wordcount : integer range 0 to 256 := 0;
+ variable readcount : integer range 0 to 255 := 0;
+ variable channel : integer range 0 to CHANNELS-1 := 0;
+ variable time_cnt : integer range 0 to 5 := 0;
+begin
+ wait until rising_edge(CLK);
+ ram_read_psa <= (others => '0');
+ ram_rd_move <= (others => '0');
+ readout_psa_finished <= '0';
+ psa_adcdata <= std_logic_vector(reg_ram_data_out(channel)(15 downto 0));
+ psa_clear <= '0';
+ psa_enable <= '1';
+ RDO_write_psa <= '0';
+ case psa_state is
+ when PSA_IDLE =>
+ channel := 0;
+ readcount := to_integer(CONF.block_avg(0));
+ wordcount := to_integer(CONF.block_sums(0));
+ psa_pointer <= 256;
+ psa_clear <= '1';
+ if state = PSA_READOUT then
+ psa_state <= PSA_START_CHANNEL;
+ end if;
+ when PSA_START_CHANNEL =>
+ ram_read_psa(channel) <= '1';
+ readcount := readcount - 1;
+ psa_clear <= '1';
+ psa_state <= PSA_WAIT_RAM;
+ when PSA_WAIT_RAM =>
+ ram_read_psa(channel) <= '1';
+ readcount := readcount - 1;
+ psa_clear <= '1';
+ psa_state <= PSA_WAIT_RAM2;
+ when PSA_WAIT_RAM2 =>
+ ram_read_psa(channel) <= '1';
+ psa_pointer <= 0;
+ psa_clear <= '1';
+ psa_state <= PSA_CALC;
+ when PSA_CALC =>
+ if readcount = 1 then
+ psa_pointer <= psa_pointer + 1;
+ psa_state <= PSA_WAITWRITE;
+ else
+ ram_read_psa(channel) <= '1';
+ psa_pointer <= psa_pointer + 1;
+ readcount := readcount - 1;
+ end if;
+ when PSA_WAITWRITE =>
+ time_cnt := 4;
+ psa_pointer <= psa_pointer + 1;
+ psa_state <= PSA_WAITWRITE2;
+
+ when PSA_WAITWRITE2 =>
+ psa_pointer <= 256;
+ time_cnt := time_cnt -1;
+ if time_cnt = 0 then
+ psa_state <= PSA_DOWRITE;
+ end if;
+ when PSA_DOWRITE =>
+ RDO_write_psa <= '1';
+ RDO_data_psa(15 downto 0) <= psa_output(to_integer(CONF.block_scale(0))+15 downto to_integer(CONF.block_scale(0)));
+ RDO_data_psa(19 downto 16) <= std_logic_vector(to_unsigned(channel,4));
+ RDO_data_psa(23 downto 20) <= std_logic_vector(to_unsigned(DEVICE,4));
+ RDO_data_psa(27 downto 24) <= x"0";
+ RDO_data_psa(31 downto 28) <= x"3";
+ if wordcount > 1 then
+ wordcount := wordcount - 1;
+ readcount := to_integer(CONF.block_avg(0));
+ psa_state <= PSA_START_CHANNEL;
+ ram_rd_move(channel) <= '1';
+ ram_rd_move_value <= ("00" & CONF.block_avg(0)) - 1;
+ elsif channel < 3 then
+ channel := channel + 1;
+ readcount := to_integer(CONF.block_avg(0));
+ wordcount := to_integer(CONF.block_sums(0));
+ psa_state <= PSA_START_CHANNEL;
+ else
+ psa_state <= PSA_FINISH;
+ end if;
+
+ when PSA_FINISH =>
+ readout_psa_finished <= '1';
+ psa_state <= PSA_WAIT_AFTER;
+
+ when PSA_WAIT_AFTER =>
+ psa_state <= PSA_IDLE;
+
+
+ end case;
+end process;
+
+-------------------------------------------------------------------------------
+-- Data Output
+-------------------------------------------------------------------------------
-READOUT_TX.data_write <= RDO_write_main or RDO_write_proc when rising_edge(CLK);
-READOUT_TX.data <= RDO_data_main or RDO_data_proc when rising_edge(CLK);
+ram_read <= ram_read_rdo or ram_read_psa;
+READOUT_TX.data_write <= RDO_write_main or RDO_write_proc or RDO_write_psa when rising_edge(CLK);
+READOUT_TX.data <= RDO_data_main or RDO_data_proc or RDO_data_psa when rising_edge(CLK);
add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
+
+add_file -vhdl -lib "work" "cores/mulacc2.vhd"
add_file -vhdl -lib "work" "source/adc_package.vhd"
add_file -vhdl -lib "work" "source/adc_processor.vhd"
add_file -vhdl -lib "work" "source/adc_ad9219.vhd"
jspc29 / trb3.git / commitdiff