before TDC

diff --git a/special/phaser_core.vhd b/special/phaser_core.vhd
index db368675d92f80c4cc495dfe0eb0818db082e38c..7f11e3607c66376514cbdac132f65f092e0e15bd 100644 (file)
--- a/special/phaser_core.vhd
+++ b/special/phaser_core.vhd
@@ -1,6 +1,8 @@
 library ieee;\r
 use ieee.std_logic_1164.all;\r
 use ieee.numeric_std.all;\r
+library ECP3;\r
+use ECP3.components.all;\r
 \r
 library work;\r
 \r
@@ -24,13 +26,14 @@ architecture phaser_core_arch of phaser_core is
 -- Signals\r
   signal ping_i         : std_logic;\r
   signal pong_i         : std_logic;\r
+  signal ping_i_q       : std_logic;\r
+  signal pong_i_q       : std_logic;\r
   signal phase_x        : std_logic;\r
-  signal phase          : std_logic;\r
 \r
   attribute HGROUP : string;\r
   attribute BBOX   : string;\r
   attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";\r
-  attribute BBOX   of phaser_core_arch : architecture is "1,1";\r
+  attribute BBOX   of phaser_core_arch : architecture is "1,2";\r
   attribute syn_sharing : string;\r
   attribute syn_sharing of phaser_core_arch : architecture is "off";\r
   attribute syn_hier : string;\r
@@ -42,14 +45,25 @@ begin
 -- we want all logic in here in one PFU (defined timing)!\r
 ---------------------------------------------------------------------------\r
 \r
+--  PINGFF : FD1S3AX port map ( CK => CLK_PING, D => PING_IN, Q => ping_i );\r
+--  PONGFF : FD1S3AX port map ( CK => CLK_PONG, D => PONG_IN, Q => pong_i );\r
+--\r
+--  PINQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => ping_i, Q => ping_i_q );\r
+--  PONQFF : FD1S3AX port map ( CK => SAMPLE_CLK, D => pong_i, Q => pong_i_q );\r
+--\r
+--  PHXLUT: LUT4 generic map ( INIT => b"0000_0000_0000_0110")\r
+--    port map ( A => ping_i_q, B => pong_i_q, C => '0', D => '0', Z => phase_x );\r
+        \r
   -- slice 0\r
-  ping_i  <= PING_IN when rising_edge(CLK_PING);   -- FF\r
+  ping_i   <= PING_IN when rising_edge(CLK_PING);   -- FF\r
   -- slice 1\r
-  pong_i  <= PONG_IN when rising_edge(CLK_PONG);   -- FF\r
+  pong_i   <= PONG_IN when rising_edge(CLK_PONG);   -- FF\r
   -- slice 2\r
-  phase_x <= ping_i xor pong_i;                    -- LUT4\r
-  phase   <= phase_x when rising_edge(SAMPLE_CLK); -- FF\r
+  ping_i_q <= ping_i  when rising_edge(SAMPLE_CLK); -- FF\r
+  pong_i_q <= pong_i  when rising_edge(SAMPLE_CLK); -- FF\r
+  -- slice 3\r
+  phase_x  <= ping_i_q xor pong_i_q;                -- LUT4\r
 \r
-  PHASE_OUT <= phase;\r
+  PHASE_OUT <= phase_x;\r
 \r
 end architecture;\r

diff --git a/special/phaser_core_ORIG.vhd b/special/phaser_core_ORIG.vhd
new file mode 100644 (file)
index 0000000..db36867
--- /dev/null
+++ b/special/phaser_core_ORIG.vhd
@@ -0,0 +1,55 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity phaser_core is\r
+  port(\r
+    SAMPLE_CLK    : in  std_logic;\r
+    PING_IN       : in  std_logic; -- TX K\r
+    CLK_PING      : in  std_logic; -- TX CLK\r
+    PONG_IN       : in  std_logic; -- RX K\r
+    CLK_PONG      : in  std_logic; -- RX CLK\r
+    PHASE_OUT     : out std_logic\r
+  );\r
+end entity phaser_core;\r
+\r
+architecture phaser_core_arch of phaser_core is\r
+\r
+-- Components\r
+\r
+-- state machine signals\r
+\r
+-- Signals\r
+  signal ping_i         : std_logic;\r
+  signal pong_i         : std_logic;\r
+  signal phase_x        : std_logic;\r
+  signal phase          : std_logic;\r
+\r
+  attribute HGROUP : string;\r
+  attribute BBOX   : string;\r
+  attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group";\r
+  attribute BBOX   of phaser_core_arch : architecture is "1,1";\r
+  attribute syn_sharing : string;\r
+  attribute syn_sharing of phaser_core_arch : architecture is "off";\r
+  attribute syn_hier : string;\r
+  attribute syn_hier of phaser_core_arch : architecture is "hard";\r
+  \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- we want all logic in here in one PFU (defined timing)!\r
+---------------------------------------------------------------------------\r
+\r
+  -- slice 0\r
+  ping_i  <= PING_IN when rising_edge(CLK_PING);   -- FF\r
+  -- slice 1\r
+  pong_i  <= PONG_IN when rising_edge(CLK_PONG);   -- FF\r
+  -- slice 2\r
+  phase_x <= ping_i xor pong_i;                    -- LUT4\r
+  phase   <= phase_x when rising_edge(SAMPLE_CLK); -- FF\r
+\r
+  PHASE_OUT <= phase;\r
+\r
+end architecture;\r