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diff --git a/special/phaser.vhd b/special/phaser.vhd
new file mode 100644 (file)
index 0000000..59f6e8d
--- /dev/null
+++ b/special/phaser.vhd
@@ -0,0 +1,123 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity phaser is\r
+  port( \r
+    SAMPLE_CLK    : in  std_logic;\r
+    RESET         : in  std_logic;\r
+    SIGNAL_A_IN   : in  std_logic;\r
+    SIGNAL_B_IN   : in  std_logic;\r
+    LOW_CNT_OUT   : out std_logic_vector(15 downto 0);\r
+    HI_CNT_OUT    : out std_logic_vector(15 downto 0);\r
+    UPDATE_OUT    : out std_logic\r
+  );\r
+end entity phaser;\r
+\r
+architecture arch of phaser is\r
+\r
+-- Components\r
+\r
+-- state machine signals\r
+\r
+-- Signals\r
+  signal low_cnt      : unsigned(15 downto 0);\r
+  signal hi_cnt       : unsigned(15 downto 0);\r
+  signal cyc_cnt      : unsigned(15 downto 0);\r
+  signal update       : std_logic;\r
+  signal cycle_done_x : std_logic;\r
+  signal cycle_done   : std_logic;\r
+  signal phase_x      : std_logic;\r
+  signal phase        : std_logic;\r
+\r
+  signal low_cnt_int  : std_logic_vector(15 downto 0);\r
+  signal hi_cnt_int   : std_logic_vector(15 downto 0);\r
+\r
+--attribute HGROUP: string;\r
+--attribute BBOX: string;\r
+--attribute HGROUP of behavioural: architecture is "phaser";\r
+--attribute BBOX   of behavioural: architecture is "5,5";\r
+\r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Sync process\r
+---------------------------------------------------------------------------\r
+  THE_SYNC_PROCESS: process( SAMPLE_CLK ) \r
+  begin\r
+    if( rising_edge(SAMPLE_CLK) ) then\r
+      cycle_done  <= cycle_done_x;\r
+      update      <= cycle_done;\r
+      phase       <= phase_x;\r
+    end if;\r
+  end process THE_SYNC_PROCESS;\r
+\r
+  phase_x <= SIGNAL_A_IN xor SIGNAL_B_IN;\r
+\r
+  -- Cycle counter\r
+  THE_CYC_CNT_PROC: process( SAMPLE_CLK, RESET )\r
+  begin\r
+    if( RESET = '1' ) then\r
+      cyc_cnt <= (others => '0');\r
+    elsif( rising_edge(SAMPLE_CLK) ) then\r
+      if( cycle_done = '1' ) then\r
+        cyc_cnt <= (others => '0');\r
+      else\r
+        cyc_cnt <= cyc_cnt + 1;\r
+      end if;\r
+    end if;\r
+  end process THE_CYC_CNT_PROC;\r
+\r
+  cycle_done_x <= '1' when (cyc_cnt = x"fffc") else '0';\r
+\r
+  -- low signal count\r
+  THE_LOW_CNT_PROC: process( SAMPLE_CLK, RESET )\r
+  begin\r
+    if( RESET = '1' ) then\r
+      low_cnt <= (others => '0');\r
+    elsif( rising_edge(SAMPLE_CLK) ) then\r
+      if( cycle_done = '1' ) then\r
+        low_cnt <= (others => '0');\r
+      elsif( phase = '0') then\r
+        low_cnt <= low_cnt + 1;\r
+      end if;\r
+    end if;\r
+  end process THE_LOW_CNT_PROC;\r
+\r
+  -- high signal count\r
+  THE_HI_CNT_PROC: process( SAMPLE_CLK, RESET )\r
+  begin\r
+    if( RESET = '1' ) then\r
+      hi_cnt <= (others => '0');\r
+    elsif( rising_edge(SAMPLE_CLK) ) then\r
+      if( cycle_done = '1' ) then\r
+        hi_cnt <= (others => '0');\r
+      elsif( phase = '1') then\r
+        hi_cnt <= hi_cnt + 1;\r
+      end if;\r
+    end if;\r
+  end process THE_HI_CNT_PROC;\r
+\r
+  THE_COUNTER_STORE_PROC: process( SAMPLE_CLK, RESET )\r
+  begin\r
+    if( RESET = '1' ) then\r
+      low_cnt_int <= (others => '0');\r
+      hi_cnt_int  <= (others => '0');\r
+    elsif( rising_edge(SAMPLE_CLK) ) then -- added\r
+      if( cycle_done = '1' ) then\r
+        low_cnt_int <= std_logic_vector(low_cnt);\r
+        hi_cnt_int  <= std_logic_vector(hi_cnt);\r
+      end if;\r
+    end if;\r
+  end process THE_COUNTER_STORE_PROC;\r
+\r
+---------------------------------------------------------------------------\r
+---------------------------------------------------------------------------\r
+\r
+  LOW_CNT_OUT <= low_cnt_int;\r
+  HI_CNT_OUT  <= hi_cnt_int;\r
+  UPDATE_OUT  <= update;\r
+\r
+end architecture;\r