\r
entity thresholds is\r
port(\r
- ID : in std_logic;\r
- OUTPUT : out std_logic_vector(15 downto 0);\r
+ DAC_FLAG : in std_logic; --ID\r
+ OUTPUT : out std_logic_vector(16 downto 1);\r
MISO_OUT : out std_logic;\r
MOSI_IN : in std_logic;\r
SCLK_IN : in std_logic;\r
- CS_IN : in std_logic \r
+ CS_IN : in std_logic--;\r
+ --LED : out std_logic_vector(7 downto 0);\r
+ --DIPSW : in std_logic_vector(3 downto 0)\r
);\r
end entity;\r
\r
signal sed_debug : std_logic_vector(31 downto 0);\r
signal controlsed_i : std_logic_vector(3 downto 0);\r
\r
- signal pwm_data_i : std_logic_vector(15 downto 0);\r
- signal pwm_write_i : std_logic;\r
- signal pwm_addr_i : std_logic_vector(4 downto 0);\r
- signal pwm_data_ii : std_logic_vector(15 downto 0);\r
- signal pwm_write_ii : std_logic;\r
- signal pwm_addr_ii : std_logic_vector(4 downto 0);\r
+ signal pwm_data_i : std_logic_vector(15 downto 0):= x"6000";\r
+ signal pwm_write_i : std_logic;\r
+ signal pwm_addr_i : std_logic_vector(4 downto 0);\r
+ signal pwm_data_ii : std_logic_vector(15 downto 0);\r
+ signal pwm_write_ii : std_logic;\r
+ signal pwm_addr_ii : std_logic_vector(4 downto 0);\r
+ signal pwm_data_iii : std_logic_vector(15 downto 0);\r
+ signal pwm_write_iii : std_logic;\r
+ signal pwm_addr_iii : std_logic_vector(4 downto 0);\r
\r
-- signal flashram_reset : std_logic;\r
--signal flashram_write_i: std_logic;\r
signal flashram_data_i : std_logic_vector(7 downto 0);\r
- signal flashram_data_o : std_logic_vector(7 downto 0);\r
- signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0);\r
+ signal flashram_data_o : std_logic_vector(7 downto 0) := "00000010";\r
+ signal ram_data : ram_t := (others =>("0000000000100001"));--: std_logic_vector(15 downto 0);\r
--signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0);\r
\r
signal flash_command : std_logic;\r
signal flash_busy : std_logic;\r
signal flash_err : std_logic;\r
\r
- signal compensate_i : signed(15 downto 0);\r
- signal pwm_i : std_logic_vector(15 downto 0);\r
+ signal compensate_i : signed(15 downto 0) := (others =>'0');\r
+ signal pwm_i : std_logic_vector(16 downto 1);\r
signal ufm_bus_ready_in : std_logic;\r
signal ufm_bus_ready_out : std_logic;\r
signal ufm_databyte_counter : unsigned(14 downto 0);\r
\r
- signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0);\r
- signal ram_data_f_spi_data : std_logic_vector(15 downto 0);\r
- signal ram_data_f_spi_write : std_logic;\r
+ signal ram_spi_addr : std_logic_vector( 7 downto 0);\r
+ signal ram_spi_data : std_logic_vector(15 downto 0):= "0000111100001111";\r
+ signal ram_spi_write : std_logic;\r
\r
+ signal show_flash_err : std_logic := '0';\r
+ signal ram_spi_read :std_logic := '0';\r
+ signal flash_temp : std_logic_vector(7 downto 0);\r
+ \r
+ --type state_type is (Start,IDLE,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15); --type of state machine.\r
+ --signal state: state_type := Start;\r
+ --signal init : std_logic:='1';\r
+ \r
+-- signal temp : std_logic_vector(3 downto 0):= "0000";\r
\r
component OSCH\r
generic (NOM_FREQ: string := "33.25");\r
\r
DEBUG => open\r
);\r
- \r
- \r
-PROC_REGS : process begin\r
- wait until rising_edge(clk_i);\r
- bus_ready <= '0';\r
- pwm_write_i <= '0';\r
- flash_go <= '0';\r
- ram_data_f_spi_write <= '0';\r
+\r
\r
- if pwm_write_ii = '1' then\r
- pwm_data_i <= pwm_data_ii;\r
- pwm_addr_i <= pwm_addr_ii;\r
- pwm_write_i <= pwm_write_ii;\r
- \r
- elsif bus_read = '1' then\r
- bus_ready <= '1';\r
- if spi_addr >= x"10" and spi_addr < x"20" then \r
- spi_tx_data <= ram_data(to_integer(unsigned(spi_addr)));\r
+-- count : process (clk_i)\r
+-- begin\r
+-- if rising_edge(clk_i) then\r
+-- if temp="1001" then\r
+-- temp<="0000";\r
+-- else\r
+-- temp <= std_logic_vector(unsigned(temp) + 1);\r
+-- end if;\r
+-- end if;\r
+-- \r
+-- end process;\r
+ \r
+-- state_machine : process (clk_i)\r
+-- begin\r
+-- if rising_edge(clk_i) then\r
+-- pwm_write_i <= '0';\r
+-- --pwm_data_i <= x"6000";\r
+-- case state is\r
+-- when Start => --when current state is "s0"\r
+-- if init = '1' then\r
+-- pwm_write_i <= '0';\r
+-- state <= c0;\r
+-- end if;\r
+-- \r
+-- when c0 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00000";\r
+-- state <= c1;\r
+-- \r
+-- when c1 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00001";\r
+-- state <= c2;\r
+-- \r
+-- when c2 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00010";\r
+-- state <= c3;\r
+-- \r
+-- when c3 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00011";\r
+-- state <= c4;\r
+-- \r
+-- when c4 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00100";\r
+-- state <= c5;\r
+-- \r
+-- when c5 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00101";\r
+-- state <= c6;\r
+-- \r
+-- when c6 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00110";\r
+-- state <= c7;\r
+-- \r
+-- when c7 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00111";\r
+-- state <= c8;\r
+-- \r
+-- when c8 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01000";\r
+-- state <= c9;\r
+-- \r
+-- when c9 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01001";\r
+-- state <= c10;\r
+-- \r
+-- when c10 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01010";\r
+-- state <= c11;\r
+-- \r
+-- when c11 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01011";\r
+-- state <= c12;\r
+-- \r
+-- when c12 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01100";\r
+-- state <= c13;\r
+-- \r
+-- when c13 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01101";\r
+-- state <= c14;\r
+-- \r
+-- when c14 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01110";\r
+-- state <= c15;\r
+-- \r
+-- when c15 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01111";\r
+-- init <= '0';\r
+-- state <= IDLE;\r
+-- init <= '0';\r
+-- \r
+-- when IDLE => pwm_write_i <= pwm_write_ii;\r
+-- pwm_addr_i <= pwm_addr_ii;\r
+-- pwm_data_i <= pwm_data_ii;\r
+-- \r
+-- end case;\r
+-- \r
+-- end if;\r
+-- end process;\r
+\r
+\r
+PWM_select : process begin\r
+ wait until rising_edge(clk_i);\r
+ \r
+ pwm_write_i <= '0';\r
+ if pwm_write_ii = '1' then\r
+ pwm_data_i <= pwm_data_ii;\r
+ pwm_addr_i <= pwm_addr_ii;\r
+ pwm_write_i <= pwm_write_ii;\r
else\r
- case spi_addr is\r
- when x"30" => spi_tx_data <= std_logic_vector(compensate_i);\r
- when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
- when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
- when others => null;\r
- end case;\r
+ pwm_data_i <= pwm_data_iii;\r
+ pwm_addr_i <= pwm_addr_iii;\r
+ pwm_write_i <= pwm_write_iii;\r
end if;\r
+\r
+end process;\r
+\r
\r
- elsif bus_write = '1' then\r
- if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm\r
- if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash\r
- pwm_data_i <= spi_rx_data(15 downto 0);\r
- pwm_addr_i <= spi_addr(4 downto 0);\r
- pwm_write_i <= '1';\r
- end if;\r
- elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram\r
- --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; \r
- ram_data_f_spi_write <= '1';\r
- ram_data_f_spi_addr <= spi_addr;\r
- ram_data_f_spi_data <= spi_rx_data;\r
- else\r
- case spi_addr is\r
- -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash;\r
- -- flash_go <= '1';\r
- when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0);\r
- when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
- end case;\r
+PROC_REGS : process begin\r
+ wait until rising_edge(clk_i);\r
+ bus_ready <= '0';\r
+ pwm_write_iii <= '0';\r
+ flash_go <= '0';\r
+ ram_spi_write <= '0';\r
+ ram_spi_read <= '0';\r
+ \r
+ if bus_read = '1' then\r
+ bus_ready <= '1';\r
+\r
+ if (spi_addr >= x"10") and (spi_addr < X"20") then\r
+ spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(4 downto 0)))); -- Read RAM\r
+ else\r
+ case spi_addr is\r
+ --when x"10" => spi_tx_data <= reg_spi_o(15 downto 0);\r
+ --when x"11" => spi_tx_data <= reg_spi_o(31 downto 16);\r
+ when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+ when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+ -- \r
+ when others => null;\r
+ end case; \r
+ end if;\r
+ elsif bus_write = '1' then\r
+ if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM\r
+ pwm_data_iii <= spi_rx_data;\r
+ pwm_addr_iii <= spi_addr(4 downto 0);\r
+ pwm_write_iii <= '1';\r
+ elsif ( spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM\r
+ ram_spi_data(15 downto 0) <= spi_rx_data;\r
+ ram_spi_write <= '1';\r
+ ram_spi_addr <= "0000" & spi_addr(3 downto 0);\r
+ pwm_data_iii <= spi_rx_data;\r
+ pwm_addr_iii <= spi_addr(4 downto 0);\r
+ pwm_write_iii <= '1';\r
+ else\r
+ case spi_addr is\r
+ when x"20" => flash_command <= '1'; --write to flash;\r
+ flash_go <= '1';\r
+ when x"21" => flash_command <= '0'; --read from flash;\r
+ flash_go <= '1';\r
+ when x"22" => compensate_i <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0);\r
+ when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
+ when others => null;\r
+ end case;\r
+ end if;\r
end if; \r
- end if;\r
end process;\r
\r
+-- ManSel : process begin\r
+-- wait until rising_edge(clk_i);\r
+-- flash_go <= '0';\r
+-- ram_spi_write <= '0';\r
+-- --ram_spi_read <= '0';\r
+-- if pwm_write_ii = '1' then\r
+-- pwm_data_i <= pwm_data_ii;\r
+-- pwm_addr_i <= pwm_addr_ii;\r
+-- pwm_write_i <= pwm_write_ii;\r
+-- elsif DIPSW(0) = '0' then\r
+-- case DIPSW(3 downto 1) is\r
+-- when "000" => ram_spi_data(15 downto 0) <= "1100011100111000";\r
+-- ram_spi_write <= '1';\r
+-- ram_spi_addr <= "00000" & DIPSW(3 downto 1);\r
+-- --when "010" => ram_spi_read <= '1';\r
+-- when "011" => flash_command <= '0'; --read from flash;\r
+-- flash_go <= '1';\r
+-- when "100" => flash_command <= '1'; --write to flash;\r
+-- flash_go <= '1';\r
+-- when "101" => ram_spi_data(15 downto 0) <= "0000011000101010";\r
+-- ram_spi_write <= '1';\r
+-- ram_spi_addr <= "00000" & DIPSW(3 downto 1);\r
+-- when others => null;\r
+-- end case;\r
+-- else \r
+-- LED <= not ram_data(to_integer(unsigned(DIPSW(3 downto 1))))(7 downto 0);\r
+-- end if;\r
+-- \r
+-- \r
+-- end process;\r
+\r
\r
THE_SED : entity work.sedcheck\r
port map(\r
); \r
\r
--TODO connect to output according to ID\r
-OUTPUT <= pwm_i;\r
-\r
+process(pwm_i,DAC_FLAG)\r
+ begin\r
+ if DAC_FLAG = '1' then\r
+ OUTPUT <= pwm_i;\r
+ else\r
+ OUTPUT(1) <= pwm_i(15);\r
+ OUTPUT(2) <= pwm_i(13);\r
+ OUTPUT(3) <= pwm_i(8);\r
+ OUTPUT(4) <= pwm_i(5);\r
+ OUTPUT(5) <= pwm_i(16);\r
+ OUTPUT(6) <= pwm_i(4);\r
+ OUTPUT(7) <= pwm_i(3);\r
+ OUTPUT(8) <= pwm_i(6);\r
+ OUTPUT(9) <= pwm_i(2);\r
+ OUTPUT(10) <= pwm_i(1);\r
+ OUTPUT(11) <= pwm_i(7);\r
+ OUTPUT(12) <= pwm_i(9);\r
+ OUTPUT(13) <= pwm_i(14);\r
+ OUTPUT(14) <= pwm_i(12);\r
+ OUTPUT(15) <= pwm_i(10);\r
+ OUTPUT(16) <= pwm_i(11); \r
+ \r
+ end if;\r
+ end process; \r
\r
\r
---------------------------------------------------------------------------\r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
---THE_UFM : entity work.UFM_control\r
--- generic map(\r
--- NO_DATAPAGES => 2,\r
--- UFM_STARTPAGE => "00"&x"00"\r
--- )\r
--- port map(\r
--- CLK => clk_i,\r
--- CMD => flash_command,\r
--- GO => flash_go,\r
--- BUSY => flash_busy,\r
--- RESET => '0',\r
--- DATA_IN => flashram_data_i,\r
--- DATA_OUT => flashram_data_o,\r
--- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte \r
--- BUS_READY_IN => ufm_bus_ready_in,\r
--- BUS_READY_OUT => ufm_bus_ready_out,\r
--- FLASH_ERROR => flash_err\r
--- );\r
-\r
+THE_UFM : entity work.UFM_control\r
+ generic map(\r
+ NO_DATAPAGES => 2,\r
+ UFM_STARTPAGE => "00"&x"00"\r
+ )\r
+ port map(\r
+ CLK => clk_i,\r
+ CMD => flash_command,\r
+ GO => flash_go,\r
+ BUSY => flash_busy,\r
+ RESET => '0',\r
+ DATA_IN => flashram_data_i,\r
+ DATA_OUT => flashram_data_o,\r
+ DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte \r
+ BUS_READY_IN => ufm_bus_ready_in,\r
+ BUS_READY_OUT => ufm_bus_ready_out,\r
+ FLASH_ERROR => flash_err\r
+ );\r
\r
---PROC_REGS_FLASH: process begin\r
---wait until rising_edge( clk_i );\r
+ \r
+-- PROC_REGS_FLASH: process begin\r
+-- wait until rising_edge( clk_i );\r
-- ufm_bus_ready_in <= '0';\r
-- pwm_write_ii <= '0';\r
--- if flash_command = '0' and ufm_bus_ready_out = '1' then\r
--- -- copy data from UFM to registers\r
--- ufm_bus_ready_in <= '1';\r
--- case to_integer ( ufm_databyte_counter ) is\r
--- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00000";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00001";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00010";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00011";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00100";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00101";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00110";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00111";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01000";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01001";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01010";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01011";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01100";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01101";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01110";\r
--- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
--- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01111";\r
--- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
+-- \r
+-- if flash_command = '0' and ufm_bus_ready_out = '1' then\r
+-- -- copy data from UFM to registers\r
+-- ufm_bus_ready_in <= '1';\r
+-- case to_integer ( ufm_databyte_counter ) is\r
+-- when 0 => ram_temp <= flashram_data_o;\r
+-- when 1 => ram_data(0)(15 downto 0) <= flashram_data_o & ram_temp;\r
+-- when 2 => ram_temp <= flashram_data_o;\r
+-- when 3 => ram_data(1)(15 downto 0) <= flashram_data_o & ram_temp;\r
-- when others => null;\r
-- end case ;\r
-- \r
-- -- save data from registers to UFM\r
-- ufm_bus_ready_in <= '1';\r
-- case to_integer ( ufm_databyte_counter ) is\r
--- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0);\r
--- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8);\r
--- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0);\r
--- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8);\r
--- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0);\r
--- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8);\r
--- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0);\r
--- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8);\r
--- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0);\r
--- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8);\r
--- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0);\r
--- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8);\r
--- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0);\r
--- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8);\r
--- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0);\r
--- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8);\r
--- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0);\r
--- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8);\r
--- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0);\r
--- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8);\r
--- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0);\r
--- when 21 => flashram_data_i <= ram_data(10)(15 downto 8);\r
--- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0);\r
--- when 23 => flashram_data_i <= ram_data(11)(15 downto 8);\r
--- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0);\r
--- when 25 => flashram_data_i <= ram_data(12)(15 downto 8);\r
--- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0);\r
--- when 27 => flashram_data_i <= ram_data(13)(15 downto 8);\r
--- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0);\r
--- when 29 => flashram_data_i <= ram_data(14)(15 downto 8);\r
--- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0);\r
--- when 31 => flashram_data_i <= ram_data(15)(15 downto 8);\r
+-- when 0 => flashram_data_i <= ram_data(1)( 7 downto 0);\r
+-- when 1 => flashram_data_i <= ram_data(1)(15 downto 8);\r
+-- --when 2 => flashram_data_i <= ram_data(1)( 7 downto 0);\r
+-- --when 3 => flashram_data_i <= ram_data(1)(15 downto 8);\r
-- when others => null ;\r
-- end case ;\r
-- \r
-- elsif ram_data_f_spi_write = '1' then\r
--- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data;\r
+-- ram_data(1) <= reg_spi;\r
+-- elsif ram_data_f_spi_read = '1' then\r
+-- reg_spi_o <= ram_data(1);\r
-- end if ;\r
--- end process ;\r
+ \r
+ \r
+\r
+PROC_REGS_FLASH: process begin\r
+wait until rising_edge( clk_i );\r
+ ufm_bus_ready_in <= '0';\r
+ pwm_write_ii <= '0';\r
+ if flash_command = '0' and ufm_bus_ready_out = '1' then\r
+ -- copy data from UFM to registers\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer ( ufm_databyte_counter ) is\r
+ when 0 => flash_temp <= flashram_data_o;\r
+ when 1 => ram_data( 0) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00000";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 2 => flash_temp <= flashram_data_o;\r
+ when 3 => ram_data( 1) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00001";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 4 => flash_temp <= flashram_data_o;\r
+ when 5 => ram_data( 2) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00010";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 6 => flash_temp <= flashram_data_o;\r
+ when 7 => ram_data( 3) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00011";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 8 => flash_temp <= flashram_data_o;\r
+ when 9 => ram_data( 4) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00100";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 10 => flash_temp <= flashram_data_o;\r
+ when 11 => ram_data( 5) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00101";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 12 => flash_temp <= flashram_data_o;\r
+ when 13 => ram_data( 6) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00110";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 14 => flash_temp <= flashram_data_o;\r
+ when 15 => ram_data( 7) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00111";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 16 => flash_temp <= flashram_data_o;\r
+ when 17 => ram_data( 8) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01000";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 18 => flash_temp <= flashram_data_o;\r
+ when 19 => ram_data( 9) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01001";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 20 => flash_temp <= flashram_data_o;\r
+ when 21 => ram_data(10) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01010";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 22 => flash_temp <= flashram_data_o;\r
+ when 23 => ram_data(11) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01011";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 24 => flash_temp <= flashram_data_o;\r
+ when 25 => ram_data(12) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01100";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 26 => flash_temp <= flashram_data_o;\r
+ when 27 => ram_data(13) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01101";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 28 => flash_temp <= flashram_data_o;\r
+ when 29 => ram_data(14) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01110";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 30 => flash_temp <= flashram_data_o;\r
+ when 31 => ram_data(15) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01111";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when others => null;\r
+ end case ;\r
+ \r
+ elsif flash_command = '1' and ufm_bus_ready_out = '1' then\r
+ -- save data from registers to UFM\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer ( ufm_databyte_counter ) is\r
+ when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0);\r
+ when 1 => flashram_data_i <= ram_data( 0)(15 downto 8);\r
+ when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0);\r
+ when 3 => flashram_data_i <= ram_data( 1)(15 downto 8);\r
+ when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0);\r
+ when 5 => flashram_data_i <= ram_data( 2)(15 downto 8);\r
+ when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0);\r
+ when 7 => flashram_data_i <= ram_data( 3)(15 downto 8);\r
+ when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0);\r
+ when 9 => flashram_data_i <= ram_data( 4)(15 downto 8);\r
+ when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0);\r
+ when 11 => flashram_data_i <= ram_data( 5)(15 downto 8);\r
+ when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0);\r
+ when 13 => flashram_data_i <= ram_data( 6)(15 downto 8);\r
+ when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0);\r
+ when 15 => flashram_data_i <= ram_data( 7)(15 downto 8);\r
+ when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0);\r
+ when 17 => flashram_data_i <= ram_data( 8)(15 downto 8);\r
+ when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0);\r
+ when 19 => flashram_data_i <= ram_data( 9)(15 downto 8);\r
+ when 20 => flashram_data_i <= ram_data(10)( 7 downto 0);\r
+ when 21 => flashram_data_i <= ram_data(10)(15 downto 8);\r
+ when 22 => flashram_data_i <= ram_data(11)( 7 downto 0);\r
+ when 23 => flashram_data_i <= ram_data(11)(15 downto 8);\r
+ when 24 => flashram_data_i <= ram_data(12)( 7 downto 0);\r
+ when 25 => flashram_data_i <= ram_data(12)(15 downto 8);\r
+ when 26 => flashram_data_i <= ram_data(13)( 7 downto 0);\r
+ when 27 => flashram_data_i <= ram_data(13)(15 downto 8);\r
+ when 28 => flashram_data_i <= ram_data(14)( 7 downto 0);\r
+ when 29 => flashram_data_i <= ram_data(14)(15 downto 8);\r
+ when 30 => flashram_data_i <= ram_data(15)( 7 downto 0);\r
+ when 31 => flashram_data_i <= ram_data(15)(15 downto 8);\r
+ when others => null ;\r
+ end case ;\r
+ \r
+ elsif ram_spi_write = '1' then\r
+ ram_data(to_integer(unsigned(ram_spi_addr))) <= ram_spi_data;\r
+ end if ;\r
+end process ;\r
\r
\r
\r
jspc29 / dirich.git / commitdiff