LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter
--FEE logic / Data Handler
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received
- LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received
+ LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected
+ LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);
LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE
LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE
signal invalid_trg : std_logic; -- invalid trigger: LVL1 missing, or wrong information
signal next_invalid_trg : std_logic;
+signal mult_trg_found : std_logic;
+
signal data_valid : std_logic;
signal next_data_valid : std_logic;
signal trg_num_match : std_logic;
signal next_trg_num_match : std_logic;
+signal error_pattern : std_logic_vector(31 downto 0);
+signal next_error_pattern : std_logic_vector(31 downto 0);
+
+signal lvl1_delay : std_logic_vector(15 downto 0);
+
signal debug : std_logic_vector(15 downto 0);
begin
timeout_found <= next_timeout_found;
trg_num_match <= next_trg_num_match;
data_valid <= next_data_valid;
+ error_pattern <= next_error_pattern;
end if;
end process THE_SYNC_PROC;
end process THE_RISING_EDGE_PROC;
-- latch the result for state machine
+-- detect multiple timing triggers
THE_LATCH_PROC: process( CLOCK )
begin
if( rising_edge(CLOCK) ) then
if ( (RESET = '1') or (trg_rst = '1') ) then
timing_trg_found <= '0';
+ mult_trg_found <= '0';
elsif( timing_trg_rising = '1' ) then
timing_trg_found <= '1';
+ mult_trg_found <= timing_trg_found;
end if;
end if;
end process THE_LATCH_PROC;
-- Jan, be fast :-)
next_timeout_found <= '1' when ( timeout_ctr = b"1_1111_1111" ) else '0';
+-- store measured delay
+-- BUG: register loading is not perfect!
+THE_MEASURED_DELAY_PROC: process( CLOCK )
+begin
+ if( rising_edge(CLOCK) ) then
+ if ( RESET = '1' ) then
+ lvl1_delay <= (others => '0');
+ elsif( toc_rst = '1' ) then
+ lvl1_delay(15 downto 9) <= (others => '0'); -- here we can store nice status bits
+ lvl1_delay(8 downto 0) <= std_logic_vector(timeout_ctr);
+ end if;
+ end if;
+end process THE_MEASURED_DELAY_PROC;
+
+LVL1_DELAY_OUT <= lvl1_delay;
+
---------------------------------------------------------------------------
-- State machine
---------------------------------------------------------------------------
-- state transitions
STATE_TRANSFORM: process( CURRENT_STATE, LVL1_TRG_RECEIVED_IN, LVL1_TRG_TYPE_IN(3), LVL1_TRG_INFORMATION_IN(7),
- LVL1_TRG_RELEASE_IN, timing_trg_found, timeout_found )
+ LVL1_TRG_RELEASE_IN, timing_trg_found, timing_trg_rising, timeout_found )
begin
NEXT_STATE <= IDLE; -- avoid latches
next_toc_ce <= '0';
(LVL1_TRG_TYPE_IN(3) = '1') and (LVL1_TRG_INFORMATION_IN(7) = '1')) then
-- timingtriggerless trigger found
NEXT_STATE <= LVL1FND;
+ next_toc_rst <= '1';
next_val_ttl_trg <= '1';
elsif( (timing_trg_found = '0') and (LVL1_TRG_RECEIVED_IN = '1') and
((LVL1_TRG_TYPE_IN(3) = '0') or (LVL1_TRG_INFORMATION_IN(7) = '0')) ) then
LVL1_VALID_TIMING_TRG_OUT <= val_trg;
LVL1_VALID_NOTIMING_TRG_OUT <= val_ttl_trg;
LVL1_INVALID_TRG_OUT <= invalid_trg;
+LVL1_MULTIPLE_TRG_OUT <= mult_trg_found;
---------------------------------------------------------------------------
-- Internal trigger counter, compare internal and external counters
LVL1_INT_TRG_NUMBER_OUT <= std_logic_vector(lvl1_int_trg_number);
-
-
---------------------------------------------------------------------------
+-- Error bits
---------------------------------------------------------------------------
+next_error_pattern(31 downto 19) <= LVL1_ERROR_PATTERN_IN(31 downto 19);
+next_error_pattern(18) <= LVL1_ERROR_PATTERN_IN(18) or mult_trg_found; -- multiple timing triggers
+next_error_pattern(17) <= LVL1_ERROR_PATTERN_IN(17) or invalid_trg; -- timing trigger missing
+next_error_pattern(16) <= LVL1_ERROR_PATTERN_IN(16) or trg_num_match; -- trigger counter mismatch
+next_error_pattern(15 downto 0) <= LVL1_ERROR_PATTERN_IN(15 downto 0);
+
+LVL1_ERROR_PATTERN_OUT <= error_pattern;
+
---------------------------------------------------------------------------
+-- Status bits
---------------------------------------------------------------------------
---This code is copied from endpoint_hades_full
-
--- proc_detect_trigger_receive : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
--- LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
--- LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT;
---
--- if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
--- got_timing_trigger <= '0';
--- got_timingless_trigger <= '0';
--- timing_trigger_missing <= '0';
--- elsif TRG_TIMING_TRG_RECEIVED_IN = '1' then
--- got_timing_trigger <= '1';
--- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then
--- got_timingless_trigger <= '1';
--- elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1')) then
--- timing_trigger_missing <= '1';
--- end if;
--- end if;
--- end process;
---
---
--- proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger )
--- begin
--- buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN;
--- buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16);
--- buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17);
--- end process;
---
--- buf_LVL1_VALID_TIMING_TRG_OUT <= TRG_TIMING_TRG_RECEIVED_IN;
--- buf_LVL1_VALID_NOTIMING_TRG_OUT <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger
--- and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7);
--- buf_LVL1_INVALID_TRG_OUT <= '0';
+STATUS_OUT(31 downto 0) <= (others => '0');
end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff