use warnings;
use strict;
-my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/';
+my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/';
#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/';
#my $synplify_path = '/home/hadaq/bin/';
use work.trb_net_components.all;
entity data_handler is
+ generic(
+ NUMBER_OF_STAT_WORDS : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(11,5))
+ );
port(
CLK : in std_logic;
RESET : in std_logic;
LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
START_READOUT_IN : in std_logic;
+ START_SEND_DATA_IN : in std_logic; --start sending data, e.g. status words
FINISHED_READOUT_IN : in std_logic;
+ FINISHED_CYCLE_IN : in std_logic; --All entities back to idle
--Config
SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on
SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal
HIT1_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
HIT0_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
SUPPRESS_SINGLE_HIT0_IN : in std_logic;
+ SUPPRESS_SINGLE_HIT1_IN : in std_logic;
--Data Input from FEE
DATA_BUS_IN : in std_logic_vector(23 downto 0);
DATA_VALID_IN : in std_logic;
FEE_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_WRITE_OUT : out std_logic;
FEE_DATA_FINISHED_OUT : out std_logic;
+ --Statistics
+ INC_DISCARDED_HIT0_OUT : out std_logic;
+ INC_DISCARDED_HIT1_OUT : out std_logic;
+ INC_TRUNCATED_WORD_OUT : out std_logic;
+ INC_TRUNCATED_EVENT_OUT : out std_logic;
+ INC_SINGLE_HIT0_OUT : out std_logic;
+ INC_SINGLE_HIT1_OUT : out std_logic;
+
+ STAT_ADDR_OUT : out std_logic_vector(4 downto 0);
+ STAT_DATA_IN : in std_logic_vector(23 downto 0);
--Debug
DEBUG_REGISTER : out std_logic_vector(31 downto 0)
);
architecture arch of data_handler is
- type state_t is (IDLE, SEND_DATA, SEND_LONG_DATA, SEND_DUMMY, FINISH);
+ type state_t is (IDLE, WRITE_DEBUG_WORD, SEND_DATA, SEND_LONG_DATA, SEND_DUMMY, FINISH,
+ STATUS_SET_ADDR, STATUS_WAIT, STATUS_CALC, STATUS_WRITE, STATUS_FINISHED);
signal current_state : state_t;
signal state_bits : std_logic_vector(3 downto 0);
signal data_write_i : std_logic;
signal data_finished_i : std_logic;
- signal dummy_counter : unsigned(11 downto 0);
+ signal dummy_counter : unsigned(11 downto 0) := (others => '0');
signal stored_hit_1 : std_logic;
signal stored_hit_0buf : std_logic;
signal data_buffer : std_logic_vector(31 downto 0);
- signal counter_data_i : unsigned(9 downto 0);
+ signal counter_data_i : unsigned(9 downto 0) := (others => '0');
signal too_many_words_i : std_logic;
+ signal word_debug : std_logic_vector(31 downto 0);
+ signal word_data_long : std_logic_vector(31 downto 0);
+ signal word_dummy : std_logic_vector(31 downto 0);
+ signal word_got_hit1_nothing_stored : std_logic_vector(31 downto 0);
+ signal word_additional_hit1 : std_logic_vector(31 downto 0);
+ signal word_additional_hit0 : std_logic_vector(31 downto 0);
+ signal word_different_hit0 : std_logic_vector(31 downto 0);
+ signal word_hit1_stored_got_hit0 : std_logic_vector(31 downto 0);
+ signal word_status : std_logic_vector(31 downto 0);
+
+ signal inc_discarded_hit0_ctr : std_logic;
+ signal inc_discarded_hit1_ctr : std_logic;
+ signal inc_truncated_events_ctr: std_logic;
+ signal inc_truncated_word_ctr : std_logic;
+ signal inc_single_hit0_ctr : std_logic;
+ signal inc_single_hit1_ctr : std_logic;
+
+
+ signal stat_addr_i : unsigned(4 downto 0) := (others => '0');
+ signal stat_data_diff_i : std_logic_vector(23 downto 0);
+
+ type statram_t is array(0 to 31) of std_logic_vector(23 downto 0);
+ signal statram : statram_t;
+ signal statram_dout : std_logic_vector(23 downto 0);
+ signal statram_din : std_logic_vector(23 downto 0);
+ signal statram_write : std_logic;
+
+
begin
+-------------------------------------------------------------------------------
+-- Build data words
+-------------------------------------------------------------------------------
+
+--Status word type 0x01: Debug word
+ word_debug(31 downto 29) <= "010";
+ word_debug(28 downto 24) <= "11111";
+ word_debug(23 downto 16) <= (others => '0');
+ word_debug(15 downto 0) <= LVL1_TRG_NUMBER_IN;
+
+--Status word type 0x00: Dummy Data
+ word_dummy(31 downto 29) <= "010";
+ word_dummy(28 downto 24) <= "11110";
+ word_dummy(23 downto 16) <= LVL1_TRG_NUMBER_IN(7 downto 0);
+ word_dummy(15 downto 12) <= (others => '0');
+ word_dummy(11 downto 0) <= std_logic_vector(dummy_counter);
+
+--Data word: debug format
+ word_data_long(31 downto 29) <= "000";
+ word_data_long(28 downto 22) <= DATA_BUS_IN(18 downto 12);
+ word_data_long(21) <= DATA_BUS_IN(11);
+ word_data_long(20 downto 16) <= (others => '0');
+ word_data_long(15 downto 12) <= LVL1_TRG_NUMBER_IN(3 downto 0);
+ word_data_long(11) <= '0';
+ word_data_long(10 downto 0) <= DATA_BUS_IN(10 downto 0);
+
+--Data word: nothing stored, getting hit 1
+ word_got_hit1_nothing_stored(31 downto 29) <= "100";
+ word_got_hit1_nothing_stored(28 downto 22) <= DATA_BUS_IN(18 downto 12);
+ word_got_hit1_nothing_stored(21 downto 11) <= DATA_BUS_IN(10 downto 0);
+ word_got_hit1_nothing_stored(10 downto 0) <= (others => '0');
+
+--Data word: hit1 stored, getting hit 1
+ word_additional_hit1(31 downto 29) <= "100";
+ word_additional_hit1(28 downto 22) <= DATA_BUS_IN(18 downto 12);
+ word_additional_hit1(21 downto 11) <= DATA_BUS_IN(10 downto 0);
+ word_additional_hit1(10 downto 0) <= (others => '0');
+
+--Data word: hit1 stored, getting different hit 0
+ word_different_hit0(31 downto 29) <= "100";
+ word_different_hit0(28 downto 22) <= DATA_BUS_IN(18 downto 12);
+ word_different_hit0(21 downto 11) <= (others => '0');
+ word_different_hit0(10 downto 0) <= DATA_BUS_IN(10 downto 0);
+
+--Data word: addtional or single hit0
+ word_additional_hit0(31 downto 29) <= "100";
+ word_additional_hit0(28 downto 22) <= DATA_BUS_IN(18 downto 12);
+ word_additional_hit0(21 downto 11) <= (others => '0');
+ word_additional_hit0(10 downto 0) <= DATA_BUS_IN(10 downto 0);
+
+--Dat word: hit1 stored, getting hit0
+ word_hit1_stored_got_hit0(10 downto 0) <= DATA_BUS_IN(10 downto 0);
+ word_hit1_stored_got_hit0(31 downto 11) <= data_i(31 downto 11);
+
+
+--Status word
+ word_status(23 downto 0) <= stat_data_diff_i;
+ word_status(28 downto 24) <= std_logic_vector(stat_addr_i);
+ word_status(31 downto 29) <= "010";
+
+
+
+
+
+
+
+
-------------------------------------------------------------------------------
-- Main State Machine
-------------------------------------------------------------------------------
THE_FSM : process(CLK)
+ variable data_write_buf : std_logic;
begin
if rising_edge(CLK) then
if RESET = '1' then
stored_hit_1buf <= '0';
stored_hit_0buf <= '0';
else
+ statram_write <= '0';
data_write_i <= '0';
+ data_write_buf := '0';
data_finished_i <= '0';
dummy_counter <= (others => '0');
+ inc_truncated_word_ctr <= '0';
+ inc_discarded_hit0_ctr <= '0';
+ inc_discarded_hit1_ctr <= '0';
+ inc_single_hit0_ctr <= '0';
+ inc_single_hit1_ctr <= '0';
case current_state is
when IDLE =>
- stored_hit_1 <= '0';
- stored_hit_1buf <= '0';
- stored_hit_0buf <= '0';
- data_buffer <= (others => '0');
- data_i <= (others => '0');
- if START_READOUT_IN = '1' then
- if SEND_DUMMY_DATA_IN = '1' then
+ stored_hit_1 <= '0';
+ stored_hit_1buf <= '0';
+ stored_hit_0buf <= '0';
+ data_buffer <= (others => '0');
+ data_i <= (others => '0');
+ if START_SEND_DATA_IN = '1' then
+-- if LVL1_TRG_TYPE_IN = x"E" then
+ current_state <= STATUS_SET_ADDR;
+ stat_addr_i <= (others => '1');
+-- end if;
+ elsif START_READOUT_IN = '1' then
+ if SEND_DEBUG_INFORMATION_IN = '1' then
+ current_state <= WRITE_DEBUG_WORD;
+ elsif SEND_DUMMY_DATA_IN = '1' then
current_state <= SEND_DUMMY;
elsif SELECT_DATA_FORMAT_IN = '1' then
current_state <= SEND_LONG_DATA;
end if;
end if;
+ when WRITE_DEBUG_WORD =>
+ data_i <= word_debug;
+ data_write_buf := '1';
+ if SEND_DUMMY_DATA_IN = '1' then
+ current_state <= SEND_DUMMY;
+ elsif SELECT_DATA_FORMAT_IN = '1' then
+ current_state <= SEND_LONG_DATA;
+ else
+ current_state <= SEND_DATA;
+ end if;
+
when SEND_LONG_DATA =>
- data_i(31 downto 29) <= "000";
- data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12);
- data_i(21) <= DATA_BUS_IN(11);
- data_i(20 downto 11) <= (others => '0');
- data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0);
- data_write_i <= DATA_VALID_IN and not too_many_words_i;
+ data_i <= word_data_long;
+ data_write_buf := DATA_VALID_IN;
if FINISHED_READOUT_IN = '1' then
current_state <= FINISH;
end if;
data_i <= data_buffer;
stored_hit_1buf <= '0';
stored_hit_1 <= '1';
- elsif stored_hit_0buf = '1' then --additional hit 0 stored
+ elsif stored_hit_0buf = '1' then --additional hit 0 stored
data_i <= data_buffer;
stored_hit_0buf <= '0';
- data_write_i <= '1';
- elsif data_write_i = '1' then
+ data_write_buf := not SUPPRESS_SINGLE_HIT0_IN;
+ elsif DATA_VALID_IN = '1' then
if DATA_BUS_IN(11) = '1' and stored_hit_1 = '0' then -- hit 1, nothing stored
- data_i(31 downto 29) <= "100";
- data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12);
- data_i(21 downto 11) <= DATA_BUS_IN(10 downto 0);
- data_i(10 downto 0) <= (others => '0');
+ data_i <= word_got_hit1_nothing_stored;
stored_hit_1 <= '1';
elsif DATA_BUS_IN(11) = '1' and stored_hit_1 = '1' then -- last channel had only hit 1
- data_buffer(31 downto 29) <= "100";
- data_buffer(28 downto 22) <= DATA_BUS_IN(18 downto 12);
- data_buffer(21 downto 11) <= DATA_BUS_IN(10 downto 0);
- data_buffer(10 downto 0) <= (others => '0');
- data_write_i <= '1';
+ data_i <= data_i;
+ data_buffer <= word_additional_hit1;
+ data_write_buf := not SUPPRESS_SINGLE_HIT1_IN;
stored_hit_1buf <= '1';
stored_hit_1 <= '0';
elsif DATA_BUS_IN(11) = '0' and stored_hit_1 = '1' then -- hit 0, hit1 stored
if DATA_BUS_IN(18 downto 12) = data_i(28 downto 22) then
- data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0);
- data_write_i <= '1';
+ data_i <= word_hit1_stored_got_hit0;
+ if DATA_BUS_IN(10 downto 0) < HIT0_LOWER_LIMIT_IN then
+ inc_discarded_hit0_ctr <= '1';
+ end if;
+ if data_i(21 downto 11) < HIT1_LOWER_LIMIT_IN then
+ inc_discarded_hit1_ctr <= '1';
+ end if;
+ if DATA_BUS_IN(10 downto 0) >= HIT0_LOWER_LIMIT_IN and data_i(21 downto 11) >= HIT1_LOWER_LIMIT_IN then
+ data_write_buf := '1';
+ end if;
stored_hit_1 <= '0';
else --hit 1 and hit 0 from different channels
data_i(10 downto 0) <= (others => '0');
- data_write_i <= '1';
+ data_write_buf := not SUPPRESS_SINGLE_HIT1_IN;
+ inc_single_hit1_ctr <= '1';
stored_hit_1 <= '0';
- data_buffer(31 downto 29) <= "100";
- data_buffer(28 downto 22) <= DATA_BUS_IN(18 downto 12);
- data_buffer(21 downto 11) <= (others => '0');
- data_buffer(10 downto 0) <= DATA_BUS_IN(10 downto 0);
- stored_hit_0buf <= '1';
+ data_buffer <= word_different_hit0;
+ stored_hit_0buf <= not SUPPRESS_SINGLE_HIT0_IN;
end if;
elsif DATA_BUS_IN(11) = '0' and stored_hit_1 = '0' then -- single / additional hit 0
- data_i(31 downto 29) <= "100";
- data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12);
- data_i(21 downto 11) <= (others => '0');
- data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0);
- data_write_i <= '1';
+ data_i <= word_additional_hit0;
+ data_write_buf := not SUPPRESS_SINGLE_HIT0_IN;
+ inc_single_hit0_ctr <= '1';
stored_hit_1 <= '0';
end if;
end if;
- if too_many_words_i = '1' then
- data_write_i <= '0';
- end if;
+
if FINISHED_READOUT_IN = '1' then
if stored_hit_1 = '0' then
- current_state <= FINISH;
+ current_state <= FINISH;
else
- data_write_i <= '1';
- current_state <= FINISH;
+ data_write_buf := '1';
+ current_state <= FINISH;
end if;
end if;
when SEND_DUMMY =>
if dummy_counter < unsigned(DUMMY_DATA_CONFIG_IN(11 downto 0)) then
- data_i(31 downto 29) <= "010";
- data_i(28 downto 12) <= (others => '0');
- data_i(11 downto 0) <= std_logic_vector(dummy_counter);
- data_write_i <= '1';
- dummy_counter <= dummy_counter + to_unsigned(1,1);
- else
- dummy_counter <= dummy_counter;
+ data_i <= word_dummy;
+ data_write_buf := '1';
+ dummy_counter <= dummy_counter + to_unsigned(1,1);
end if;
if FINISHED_READOUT_IN = '1' then
current_state <= FINISH;
end if;
+ when STATUS_SET_ADDR =>
+ stat_addr_i <= stat_addr_i + to_unsigned(1,1);
+ current_state <= STATUS_WAIT;
+
+ when STATUS_WAIT =>
+ current_state <= STATUS_CALC;
+
+ when STATUS_CALC =>
+ if stat_addr_i = 0 then
+ stat_data_diff_i <= STAT_DATA_IN;
+ else
+ stat_data_diff_i <= std_logic_vector(unsigned(STAT_DATA_IN) - unsigned(statram_dout));
+ end if;
+ current_state <= STATUS_WRITE;
+
+ when STATUS_WRITE =>
+ data_i <= word_status;
+ data_write_buf := '1';
+ statram_din <= stat_data_diff_i;
+ statram_write <= '1';
+ if stat_addr_i = unsigned(NUMBER_OF_STAT_WORDS) - to_unsigned(1,1) then
+ current_state <= STATUS_FINISHED;
+ else
+ current_state <= STATUS_SET_ADDR;
+ end if;
+
+ when STATUS_FINISHED =>
+ stat_addr_i <= (others => '1');
+ data_finished_i <= '1';
+ current_state <= IDLE;
+
when FINISH =>
data_finished_i <= '1';
current_state <= IDLE;
when others =>
current_state <= IDLE;
end case;
+
+ data_write_i <= data_write_buf and not too_many_words_i;
+ inc_truncated_word_ctr <= data_write_buf and too_many_words_i;
+
+ if FINISHED_CYCLE_IN = '1' then
+ current_state <= IDLE;
+ end if;
+
end if;
end if;
end process;
proc_word_counter : process(CLK)
begin
if rising_edge(CLK) then
+ inc_truncated_events_ctr <= '0';
if current_state = IDLE then
counter_data_i <= (others => '0');
elsif DATA_VALID_IN = '1' then
end if;
if counter_data_i >= unsigned(DATA_WORD_LIMIT_IN) then
too_many_words_i <= '1';
+ inc_truncated_events_ctr <= not too_many_words_i;
else
too_many_words_i <= '0';
end if;
end if;
end process;
+-------------------------------------------------------------------------------
+-- Statistics RAM
+-------------------------------------------------------------------------------
+
+ THE_RAM_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if statram_write = '1' then
+ statram((to_integer(stat_addr_i))) <= statram_din;
+ end if;
+ statram_dout <= statram(to_integer(stat_addr_i));
+ end if;
+ end process;
+
+
-------------------------------------------------------------------------------
-- I/O
FEE_DATA_OUT <= data_i;
FEE_DATA_WRITE_OUT <= data_write_i;
FEE_DATA_FINISHED_OUT <= data_finished_i;
-
+ INC_DISCARDED_HIT0_OUT <= inc_discarded_hit0_ctr;
+ INC_DISCARDED_HIT1_OUT <= inc_discarded_hit1_ctr;
+ INC_TRUNCATED_EVENT_OUT <= inc_truncated_events_ctr;
+ INC_TRUNCATED_WORD_OUT <= inc_truncated_word_ctr;
+ INC_SINGLE_HIT0_OUT <= inc_single_hit0_ctr;
+ INC_SINGLE_HIT1_OUT <= inc_single_hit1_ctr;
+ STAT_ADDR_OUT <= std_logic_vector(stat_addr_i);
-------------------------------------------------------------------------------
-- Debug
begin
if rising_edge(CLK) then
case current_state is
- when IDLE => state_bits <= x"0";
- when SEND_DATA => state_bits <= x"1";
- when SEND_LONG_DATA => state_bits <= x"2";
- when SEND_DUMMY => state_bits <= x"3";
- when FINISH => state_bits <= x"4";
- when others => state_bits <= x"F";
+ when IDLE => state_bits <= x"0";
+ when SEND_DATA => state_bits <= x"1";
+ when SEND_LONG_DATA => state_bits <= x"2";
+ when SEND_DUMMY => state_bits <= x"3";
+ when FINISH => state_bits <= x"4";
+ when WRITE_DEBUG_WORD => state_bits <= x"5";
+ when STATUS_SET_ADDR => state_bits <= x"6";
+ when STATUS_WAIT => state_bits <= x"7";
+ when STATUS_CALC => state_bits <= x"8";
+ when STATUS_WRITE => state_bits <= x"9";
+ when STATUS_FINISHED => state_bits <= x"A";
+ when others => state_bits <= x"F";
end case;
end if;
end process;
STAT_READ_ENABLE_IN : in std_logic;
STAT_READY_OUT : out std_logic;
+ STATISTIC_ADDR_IN : in std_logic_vector(3 downto 0);
+ STATISTIC_DATA_OUT : out std_logic_vector(31 downto 0);
+ STATISTIC_READ_IN : in std_logic;
+ STATISTIC_READY_OUT : out std_logic;
+
RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo
RB_READ_ENABLE_IN : in std_logic;
RB_READY_OUT : out std_logic;
COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0);
COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0);
STAT_REG_OUT : out std_logic_vector(63 downto 0);
- CTRL_REG_IN : in std_logic_vector(63 downto 0);
+ CTRL_REG_IN : in std_logic_vector(127 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
architecture arch of mdc_control is
-
-
signal add_out_i : std_logic_vector(8 downto 0);
signal aod_out_i : std_logic;
signal dst_out_i : std_logic;
signal trg_pulse_counter : unsigned(4 downto 0);
signal reg_timing_trigger : std_logic;
signal trigger_begin_run : std_logic;
--- signal trigger_reg_pulse_i : std_logic;
+ signal reset_mbo_i : std_logic;
signal reset_trigger_logic_i : std_logic;
signal reset_mbo_logic_i : std_logic;
signal start_calib_i : std_logic;
signal start_begrun_i : std_logic;
signal start_readout_i : std_logic;
+ signal start_send_data_i : std_logic;
signal finished_readout_i : std_logic;
signal finished_begrun_i : std_logic;
+ signal finished_cycle_i : std_logic;
signal cal1_loaded_i : std_logic;
signal token_missing_i : std_logic;
signal hit1_lower_limit_i : std_logic_vector(10 downto 0);
signal hit0_lower_limit_i : std_logic_vector(10 downto 0);
signal suppress_single_hit0_i : std_logic;
+ signal suppress_single_hit1_i : std_logic;
+ signal enable_reconfigure_i : std_logic;
+ signal fee_data_finished_i : std_logic;
+
+ signal reset_statistics_i : std_logic;
+ signal counter_reinit_i : unsigned(15 downto 0);
+ signal counter_calib_i : unsigned(15 downto 0);
+ signal counter_trigger_i : unsigned(23 downto 0);
+ signal counter_discarded_hit1_i : unsigned(23 downto 0);
+ signal counter_discarded_hit0_i : unsigned(23 downto 0);
+ signal counter_truncated_events_i : unsigned(23 downto 0);
+ signal counter_truncated_words_i : unsigned(23 downto 0);
+ signal counter_single_hit1_i : unsigned(23 downto 0);
+ signal counter_single_hit0_i : unsigned(23 downto 0);
+ signal counter_retransmit_received_i : unsigned(11 downto 0);
+ signal counter_retransmit_sent_i : unsigned(11 downto 0);
+
+ signal inc_reinit_counter : std_logic;
+ signal inc_calib_counter : std_logic;
+ signal inc_trigger_counter : std_logic;
+ signal inc_discarded_hit0_ctr : std_logic;
+ signal inc_discarded_hit1_ctr : std_logic;
+ signal inc_truncated_word_ctr : std_logic;
+ signal inc_trunc_ctr : std_logic;
+ signal inc_single_hit0_ctr : std_logic;
+ signal inc_single_hit1_ctr : std_logic;
+
+ signal data_handler_stat_addr_i: std_logic_vector(4 downto 0);
+ signal data_handler_stat_data_i: std_logic_vector(23 downto 0);
+
begin
-------------------------------------------------------------------------------
TRIGGER_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long;
- TRIGGER_MONITOR_OUT <= ((TRIGGER_IN xor switch_polarity)) or trigger_pseudo_tmg_long;
+ TRIGGER_MONITOR_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long;
PULSE_PSEUDO_TIMING : process(CLK)
-
----------------------------------------------------------------------
--- Status Register
----------------------------------------------------------------------
-
-STAT_REG_OUT(STAT_REG_OUT'left downto 0) <= (others => '0');
-
-------------------------------------------------------------------------------
-- Trigger Handler
-------------------------------------------------------------------------------
LVL1_RELEASE_OUT => LVL1_RELEASE_OUT,
LVL1_STATUSBITS_OUT => lvl1_statusbits_i,
DO_BEGIN_RUN_IN => trigger_begin_run,
+ ENABLE_REINIT_IN => enable_reconfigure_i,
--FSM control
START_TRIGGER_OUT => start_trigger_i,
START_CALIB_OUT => start_calib_i,
START_BEGRUN_OUT => start_begrun_i,
START_READOUT_OUT => start_readout_i,
+ START_SEND_DATA_OUT => start_send_data_i,
FINISHED_READOUT_OUT => finished_readout_i,
+ FINISHED_CYCLE_OUT => finished_cycle_i,
+ RESET_MBO_OUT => reset_mbo_i,
--FSM status
FINISHED_BEGRUN_IN => finished_begrun_i,
CAL1_LOADED_IN => cal1_loaded_i,
TOKEN_MISSING_IN => token_missing_i,
TOKEN_BACK_IN => token_back_i,
+ FINISHED_STORING_DATA_IN => fee_data_finished_i,
+ --Statistics
+ INC_REINIT_OUT => inc_reinit_counter,
+ INC_CALIB_OUT => inc_calib_counter,
+ INC_TRIGGER_OUT => inc_trigger_counter,
--debug
DEBUG_REGISTER => debug_trigger_handler_i
);
RESET => reset_trigger_logic_i,
--LVL1
LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
- LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,
+ LVL1_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN,
LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
--Readout
START_READOUT_IN => start_readout_i,
+ START_SEND_DATA_IN => start_send_data_i,
FINISHED_READOUT_IN => finished_readout_i,
+ FINISHED_CYCLE_IN => finished_cycle_i,
--Config
SELECT_DATA_FORMAT_IN => data_format_i,
SEND_DEBUG_INFORMATION_IN => data_debug_i,
HIT1_LOWER_LIMIT_IN => hit1_lower_limit_i,
HIT0_LOWER_LIMIT_IN => hit0_lower_limit_i,
SUPPRESS_SINGLE_HIT0_IN => suppress_single_hit0_i,
+ SUPPRESS_SINGLE_HIT1_IN => suppress_single_hit1_i,
--Data Input from FEE
DATA_BUS_IN => data_bus_i,
DATA_VALID_IN => data_bus_valid_i,
--Data Output to Endpoint
FEE_DATA_OUT => FEE_DATA_OUT,
FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
- FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i,
+ --Statistics
+ INC_DISCARDED_HIT0_OUT => inc_discarded_hit0_ctr,
+ INC_DISCARDED_HIT1_OUT => inc_discarded_hit1_ctr,
+ INC_TRUNCATED_WORD_OUT => inc_truncated_word_ctr,
+ INC_TRUNCATED_EVENT_OUT => inc_trunc_ctr,
+ INC_SINGLE_HIT0_OUT => inc_single_hit0_ctr,
+ INC_SINGLE_HIT1_OUT => inc_single_hit1_ctr,
+ STAT_ADDR_OUT => data_handler_stat_addr_i,
+ STAT_DATA_IN => data_handler_stat_data_i,
--Debug
DEBUG_REGISTER => debug_data_handler_i
);
the_tdc_readout : tdc_readout
port map(
CLK => CLK,
- RESET => reset_trigger_logic_i,
+ RESET => reset_mbo_logic_i,
--MBO
A_ADD_IN => add_in_i,
A_AOD_IN => aod_in_i,
--Control
START_READOUT_IN => start_readout_i,
TOKEN_IN => A_RDO,
- FINISHED_IN => finished_readout_i,
+ FINISHED_IN => finished_cycle_i,
FLAG_EVENT_COUNTER_IN => LVL1_INT_TRG_NUMBER_IN(3 downto 0),
--Data
DATA_BUS_OUT => data_bus_i,
START_CALIB_IN => start_calib_i,
START_BEGRUN_IN => start_begrun_i,
START_READOUT_IN => start_readout_i,
- FINISHED_READOUT_IN => finished_readout_i,
+ FINISHED_READOUT_IN => finished_cycle_i,
--Status
TOKEN_MISSING_OUT => token_missing_i,
TOKEN_BACK_OUT => token_back_i,
end if;
end process;
+ proc_statistic_regs : process(CLK)
+ variable tmp : integer range 0 to 15;
+ begin
+ if rising_edge(CLK) then
+ STATISTIC_READY_OUT <= STATISTIC_READ_IN;
+ if STATISTIC_READ_IN = '1' then
+ tmp := to_integer(unsigned(STATISTIC_ADDR_IN));
+ case tmp is
+ when 0 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_reinit_i);
+ when 1 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_reinit_i);
+ when 2 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_trigger_i);
+ when 3 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_calib_i);
+ when 4 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_discarded_hit1_i);
+ when 5 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_discarded_hit0_i);
+ when 6 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_truncated_words_i);
+ when 7 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_truncated_events_i);
+ when 8 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_single_hit1_i);
+ when 9 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_single_hit0_i);
+ when 10 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_retransmit_received_i)
+ & std_logic_vector(counter_retransmit_sent_i);
+ when others =>
+ STATISTIC_DATA_OUT <= (others => '0');
+ end case;
+ end if;
+ end if;
+ end process;
+
+ proc_statistic_words : process(CLK)
+ variable tmp : integer range 0 to 31;
+ begin
+ if rising_edge(CLK) then
+ tmp := to_integer(unsigned(data_handler_stat_addr_i));
+ case tmp is
+ when 0 => data_handler_stat_data_i <= "00000" & cms_active_i & motherboard_type_i(1 downto 0) & LVL1_INT_TRG_NUMBER_IN;
+ when 1 => data_handler_stat_data_i <= x"00" & std_logic_vector(counter_reinit_i);
+ when 2 => data_handler_stat_data_i <= std_logic_vector(counter_trigger_i);
+ when 3 => data_handler_stat_data_i <= x"00" & std_logic_vector(counter_calib_i);
+ when 4 => data_handler_stat_data_i <= std_logic_vector(counter_discarded_hit1_i);
+ when 5 => data_handler_stat_data_i <= std_logic_vector(counter_discarded_hit0_i);
+ when 6 => data_handler_stat_data_i <= std_logic_vector(counter_truncated_words_i);
+ when 7 => data_handler_stat_data_i <= std_logic_vector(counter_truncated_events_i);
+ when 8 => data_handler_stat_data_i <= std_logic_vector(counter_single_hit1_i);
+ when 9 => data_handler_stat_data_i <= std_logic_vector(counter_single_hit0_i);
+ when 10 => data_handler_stat_data_i <= std_logic_vector(counter_retransmit_received_i)
+ & std_logic_vector(counter_retransmit_sent_i);
+ when others =>
+ data_handler_stat_data_i <= (others => '0');
+ end case;
+ end if;
+ end process;
+
-- -------------------------------------------------------------------------------
-- -- Readback FiFo
-- -------------------------------------------------------------------------------
--- THE_TDC_READBACK_MEM : fifo_18x256_oreg
--- port map (
--- Data(7 downto 0) => add_in_i(8 downto 1),
--- Data(8) => add_in_i(0),
--- Data(15 downto 9) => (others => '0'),
--- Data(16) => dst_in_i,
--- Data(17) => aod_in_i,
--- Clock => CLK,
--- AmFullThresh => (others => '0'),
--- WrEn => readback_mem_write,
--- RdEn => RB_READ_ENABLE_IN,
--- Reset => RESET,
--- Q => RB_DATA_OUT(17 downto 0),
--- Empty => RB_EMPTY_OUT,
--- Full => readback_mem_full
--- );
---
--- PULSE_DEBUG_WRITE : edge_to_pulse
--- port map (
--- CLOCK => CLK,
--- en_clk => '1',
--- signal_in => dst_in_i,
--- PULSE => readback_mem_write
--- );
---
---
--- -- RB_EMPTY_OUT <= '0';
--- process(CLK)
--- begin
--- if rising_edge(CLK) then
--- last_rb_read_enable_in <= RB_READ_ENABLE_IN;
--- RB_READY_OUT <= last_rb_read_enable_in;
--- end if;
--- end process;
--- RB_DATA_OUT(31 downto 18) <= (others => '0');
---
---
+ THE_TDC_READBACK_MEM : fifo_18x256_oreg
+ port map (
+ Data(7 downto 0) => add_in_i(8 downto 1),
+ Data(8) => add_in_i(0),
+ Data(15 downto 9) => (others => '0'),
+ Data(16) => dst_in_i,
+ Data(17) => aod_in_i,
+ Clock => CLK,
+ AmFullThresh => (others => '0'),
+ WrEn => readback_mem_write,
+ RdEn => RB_READ_ENABLE_IN,
+ Reset => RESET,
+ Q => RB_DATA_OUT(17 downto 0),
+ Empty => RB_EMPTY_OUT,
+ Full => readback_mem_full
+ );
+
+ PULSE_DEBUG_WRITE : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ en_clk => '1',
+ signal_in => dst_in_i,
+ PULSE => readback_mem_write
+ );
+
+
+ -- RB_EMPTY_OUT <= '0';
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_rb_read_enable_in <= RB_READ_ENABLE_IN;
+ RB_READY_OUT <= last_rb_read_enable_in;
+ end if;
+ end process;
+ RB_DATA_OUT(31 downto 18) <= (others => '0');
+
+
-------------------------------------------------------------------------------
-- Other settings
PROC_REG_SETTINGS : process(CLK)
begin
if rising_edge(CLK) then
- reset_mbo_logic_i <= RESET or COMMON_CTRL_REG_IN(0);
+ reset_mbo_logic_i <= RESET or COMMON_CTRL_REG_IN(0) or reset_mbo_i;
reset_trigger_logic_i <= RESET or COMMON_CTRL_REG_IN(1);
+ reset_statistics_i <= RESET or COMMON_CTRL_REG_IN(5);
motherboard_type_i <= CTRL_REG_IN(7 downto 4);
+ data_word_limit_i <= CTRL_REG_IN(25 downto 16);
+ suppress_single_hit0_i <= CTRL_REG_IN(40);
+ suppress_single_hit1_i <= CTRL_REG_IN(41);
+ enable_reconfigure_i <= CTRL_REG_IN(42);
dummy_data_config_i <= CTRL_REG_IN(63 downto 48);
+ hit0_lower_limit_i <= CTRL_REG_IN(74 downto 64);
+ hit1_lower_limit_i <= CTRL_REG_IN(90 downto 80);
trigger_pseudo_timing <= COMMON_CTRL_REG_IN(16);
trigger_begin_run <= COMMON_CTRL_REG_IN(22);
data_format_i <= COMMON_CTRL_REG_IN(84);
end if;
end process;
- data_word_limit_i <= std_logic_vector(to_unsigned(768,10));
- hit1_lower_limit_i <= std_logic_vector(to_unsigned(0,11));
- hit0_lower_limit_i <= std_logic_vector(to_unsigned(0,11));
- suppress_single_hit0_i <= '0';
+
+-------------------------------------------------------------------------------
+-- Statistics
+-------------------------------------------------------------------------------
+
+ proc_statistics_ctr : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_statistics_i = '1' then
+ counter_discarded_hit1_i <= (others => '0');
+ counter_discarded_hit0_i <= (others => '0');
+ counter_calib_i <= (others => '0');
+ counter_reinit_i <= (others => '0');
+ counter_truncated_events_i <= (others => '0');
+ counter_trigger_i <= (others => '0');
+ counter_truncated_words_i <= (others => '0');
+ counter_single_hit1_i <= (others => '0');
+ counter_single_hit0_i <= (others => '0');
+ else
+ if inc_discarded_hit0_ctr = '1' then
+ counter_discarded_hit0_i <= counter_discarded_hit0_i + to_unsigned(1,1);
+ end if;
+ if inc_calib_counter = '1' then
+ counter_calib_i <= counter_calib_i + to_unsigned(1,1);
+ end if;
+ if inc_discarded_hit1_ctr = '1' then
+ counter_discarded_hit1_i <= counter_discarded_hit1_i + to_unsigned(1,1);
+ end if;
+ if inc_reinit_counter = '1' then
+ counter_reinit_i <= counter_reinit_i + to_unsigned(1,1);
+ end if;
+ if inc_trunc_ctr = '1' then
+ counter_truncated_events_i <= counter_truncated_events_i + to_unsigned(1,1);
+ end if;
+ if inc_trigger_counter = '1' then
+ counter_trigger_i <= counter_trigger_i + to_unsigned(1,1);
+ end if;
+ if inc_truncated_word_ctr = '1' then
+ counter_truncated_words_i <= counter_truncated_words_i + to_unsigned(1,1);
+ end if;
+ if inc_single_hit0_ctr = '1' then
+ counter_single_hit0_i <= counter_single_hit0_i + to_unsigned(1,1);
+ end if;
+ if inc_single_hit1_ctr = '1' then
+ counter_single_hit1_i <= counter_single_hit1_i + to_unsigned(1,1);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
- debug_control_i(0) <= token_back_i;
- debug_control_i(1) <= token_missing_i;
- debug_control_i(2) <= cms_active_i;
-
- debug_control_i(31 downto 3) <= (others => '0');
-
DEBUG_OUT <= debug_control_i;
+ FEE_DATA_FINISHED_OUT <= fee_data_finished_i;
- process(lvl1_statusbits_i)
+ process(lvl1_statusbits_i, debug_ctrl_line_handle_i)
begin
LVL1_STATUSBITS_OUT <= lvl1_statusbits_i;
LVL1_STATUSBITS_OUT(22) <= not debug_ctrl_line_handle_i(8);
process(CLK)
begin
if rising_edge(CLK) then
- token_missing_reg_i <= (token_missing_i or token_missing_reg_i) and not reset_mbo_logic_i;
+ token_missing_reg_i <= (token_missing_i or token_missing_reg_i) and not reset_statistics_i;
COMMON_STAT_REG_OUT <= (others => '0');
COMMON_STAT_REG_OUT(6) <= not debug_ctrl_line_handle_i(8);
end if;
end process;
+
+---------------------------------------------------------------------
+-- Status Register
+---------------------------------------------------------------------
+
+STAT_REG_OUT(STAT_REG_OUT'left downto 0) <= (others => '0');
+
+
+-------------------------------------------------------------------------------
+-- Debug
+-------------------------------------------------------------------------------
+ debug_control_i(0) <= token_back_i;
+ debug_control_i(1) <= token_missing_i;
+ debug_control_i(2) <= cms_active_i;
+
+ debug_control_i(31 downto 3) <= (others => '0');
+
+
end architecture;
\ No newline at end of file
LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
START_READOUT_IN : in std_logic;
+ START_SEND_DATA_IN : in std_logic; --start sending data, e.g. status words
FINISHED_READOUT_IN : in std_logic;
+ FINISHED_CYCLE_IN : in std_logic; --All entities back to idle
--Config
SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on
SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal
HIT1_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
HIT0_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
SUPPRESS_SINGLE_HIT0_IN : in std_logic;
+ SUPPRESS_SINGLE_HIT1_IN : in std_logic;
--Data Input from FEE
DATA_BUS_IN : in std_logic_vector(23 downto 0);
DATA_VALID_IN : in std_logic;
FEE_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_WRITE_OUT : out std_logic;
FEE_DATA_FINISHED_OUT : out std_logic;
+ --Statistics
+ INC_DISCARDED_HIT0_OUT : out std_logic;
+ INC_DISCARDED_HIT1_OUT : out std_logic;
+ INC_TRUNCATED_WORD_OUT : out std_logic;
+ INC_TRUNCATED_EVENT_OUT : out std_logic;
+ INC_SINGLE_HIT0_OUT : out std_logic;
+ INC_SINGLE_HIT1_OUT : out std_logic;
+
+ STAT_ADDR_OUT : out std_logic_vector(4 downto 0);
+ STAT_DATA_IN : in std_logic_vector(23 downto 0);
--Debug
DEBUG_REGISTER : out std_logic_vector(31 downto 0)
);
STAT_READ_ENABLE_IN : in std_logic;
STAT_READY_OUT : out std_logic;
+ STATISTIC_ADDR_IN : in std_logic_vector(3 downto 0);
+ STATISTIC_DATA_OUT : out std_logic_vector(31 downto 0);
+ STATISTIC_READ_IN : in std_logic;
+ STATISTIC_READY_OUT : out std_logic;
+
RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo
RB_READ_ENABLE_IN : in std_logic;
RB_READY_OUT : out std_logic;
COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0);
COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0);
STAT_REG_OUT : out std_logic_vector(63 downto 0);
- CTRL_REG_IN : in std_logic_vector(63 downto 0);
+ CTRL_REG_IN : in std_logic_vector(127 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
DO_BEGIN_RUN_IN : in std_logic;
+ ENABLE_REINIT_IN : in std_logic;
--FSM control
START_TRIGGER_OUT : out std_logic; --start normal trigger
START_CALIB_OUT : out std_logic; --start calibration trigger
START_BEGRUN_OUT : out std_logic; --start begrun trigger
START_READOUT_OUT : out std_logic; --begin tdc readout aka send token and read data
- FINISHED_READOUT_OUT : out std_logic; --All entities back to idle
+ START_SEND_DATA_OUT : out std_logic; --start sending data, e.g. status words
+ FINISHED_READOUT_OUT : out std_logic; --Readout if finished
+ FINISHED_CYCLE_OUT : out std_logic; --All entities back to idle
+ RESET_MBO_OUT : out std_logic;
--FSM status
FINISHED_BEGRUN_IN : in std_logic; --loading settings finished
CAL1_LOADED_IN : in std_logic; --calibration settings have been loaded
TOKEN_MISSING_IN : in std_logic; --token timeout - not received back
TOKEN_BACK_IN : in std_logic; --token back, readout finished
+ FINISHED_STORING_DATA_IN : in std_logic; --data_handler finished writing data to buffer
+ --Statistics
+ INC_REINIT_OUT : out std_logic;
+ INC_CALIB_OUT : out std_logic;
+ INC_TRIGGER_OUT : out std_logic;
--debug
DEBUG_REGISTER : out std_logic_vector(31 downto 0)
-- hex 64
next_MOD_RES_TOK_WRM_RDM_GDE <= "010101";
next_not_token_back <= '1'; --token NOT back
- next_finished_readout <= '1';
+ next_finished_readout <= '0';
if FINISH_IN = '1' then
next_state <= idle_state;
end if;
LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
DO_BEGIN_RUN_IN : in std_logic;
-
+ ENABLE_REINIT_IN : in std_logic;
--FSM control
START_TRIGGER_OUT : out std_logic; --start normal trigger
START_CALIB_OUT : out std_logic; --start calibration trigger
START_BEGRUN_OUT : out std_logic; --start begrun trigger
START_READOUT_OUT : out std_logic; --begin tdc readout aka send token and read data
- FINISHED_READOUT_OUT : out std_logic; --All entities back to idle
+ START_SEND_DATA_OUT : out std_logic; --start sending data, e.g. status words
+ FINISHED_READOUT_OUT : out std_logic; --readout is finished
+ FINISHED_CYCLE_OUT : out std_logic; --All entities back to idle
+ RESET_MBO_OUT : out std_logic;
--FSM status
FINISHED_BEGRUN_IN : in std_logic; --loading settings finished
CAL1_LOADED_IN : in std_logic; --calibration settings have been loaded
TOKEN_MISSING_IN : in std_logic; --token timeout - not received back
TOKEN_BACK_IN : in std_logic; --token back, readout finished
+ FINISHED_STORING_DATA_IN : in std_logic; --data_handler finished writing data to buffer
+ --Statistics
+ INC_REINIT_OUT : out std_logic;
+ INC_CALIB_OUT : out std_logic;
+ INC_TRIGGER_OUT : out std_logic;
--debug
DEBUG_REGISTER : out std_logic_vector(31 downto 0)
architecture trigger_handle_trg_arch of trigger_handler is
constant WAIT_AFTER_BEGRUN : unsigned(11 downto 0) := x"7D0";
- type state_type is (IDLE, BEGRUN, TIMING_TRIGGER, CALIB_TRIGGER, DO_READOUT, RELEASE_LVL1);
+ type state_type is (IDLE, BEGRUN, DO_REINIT, DO_REINIT2, TIMING_TRIGGER, CALIB_TRIGGER,
+ DO_READOUT, RELEASE_LVL1, WAIT_FOR_FINISHED_STORING);
signal current_state : state_type;
signal start_trigger_i : std_logic;
signal start_readout_i : std_logic;
+ signal start_send_data_i : std_logic;
signal start_calib_i : std_logic;
signal start_begrun_i : std_logic;
signal finished_readout_i : std_logic;
+ signal finished_cycle_i : std_logic;
signal lvl1_release_i : std_logic;
signal timer : unsigned(11 downto 0);
signal state_bits : std_logic_vector(3 downto 0);
signal lvl1_statusbits_i : std_logic_vector(31 downto 0);
+ signal storing_data_is_finished: std_logic;
+ signal inc_reinit_counter : std_logic;
+ signal inc_calib_counter : std_logic;
+ signal inc_trigger_counter : std_logic;
+
+ signal reinit_running : std_logic;
+ signal reset_mbo_i : std_logic;
+ signal mbo_configured_i : std_logic;
begin
start_begrun_i <= '0';
finished_readout_i <= '0';
lvl1_release_i <= '0';
+ reinit_running <= '0';
+ reset_mbo_i <= '0';
+ mbo_configured_i <= '0';
else
start_trigger_i <= '0';
start_readout_i <= '0';
+ start_send_data_i <= '0';
start_calib_i <= '0';
start_begrun_i <= '0';
finished_readout_i <= '0';
+ finished_cycle_i <= '0';
lvl1_release_i <= '0';
timer_clear <= '0';
+ inc_reinit_counter <= '0';
+ inc_calib_counter <= '0';
+ inc_trigger_counter <= '0';
+ reset_mbo_i <= '0';
case current_state is
when IDLE =>
if DO_BEGIN_RUN_IN = '1' then
current_state <= BEGRUN;
start_begrun_i <= '1';
- elsif LVL1_VALID_TIMING_TRG_IN = '1' then
- current_state <= TIMING_TRIGGER;
- timer_clear <= '1';
- start_trigger_i <= '1';
- elsif LVL1_VALID_NOTIMING_TRG_IN = '1' then -- and LVL1_TRG_TYPE_IN = x"9"
- current_state <= CALIB_TRIGGER;
- start_calib_i <= '1';
+ elsif mbo_configured_i = '1' then
+ if LVL1_VALID_TIMING_TRG_IN = '1' then
+ current_state <= TIMING_TRIGGER;
+ timer_clear <= '1';
+ start_trigger_i <= '1';
+ elsif LVL1_VALID_NOTIMING_TRG_IN = '1' and LVL1_TRG_TYPE_IN = x"9" then
+ current_state <= CALIB_TRIGGER;
+ start_calib_i <= '1';
+ elsif LVL1_VALID_NOTIMING_TRG_IN = '1' and LVL1_TRG_TYPE_IN = x"E" then
+ current_state <= WAIT_FOR_FINISHED_STORING;
+ start_send_data_i <= '1';
+ elsif LVL1_VALID_NOTIMING_TRG_IN = '1' then
+ current_state <= RELEASE_LVL1;
+ end if;
+ elsif LVL1_VALID_NOTIMING_TRG_IN = '1' or LVL1_VALID_TIMING_TRG_IN = '1' then
+ current_state <= RELEASE_LVL1;
end if;
when BEGRUN =>
if FINISHED_BEGRUN_IN = '1' then
- current_state <= IDLE;
- finished_readout_i <= '1';
+ if reinit_running = '1' then
+ reinit_running <= '0';
+ current_state <= WAIT_FOR_FINISHED_STORING;
+ else
+ current_state <= IDLE;
+ end if;
+ mbo_configured_i <= '1';
+ finished_readout_i <= '1';
end if;
+ when DO_REINIT =>
+ current_state <= DO_REINIT2;
+
+ when DO_REINIT2 =>
+ start_begrun_i <= '1';
+ current_state <= BEGRUN;
+
when TIMING_TRIGGER =>
if timer = x"02" then
current_state <= DO_READOUT;
when DO_READOUT =>
if TOKEN_BACK_IN = '1' then
+ current_state <= WAIT_FOR_FINISHED_STORING;
finished_readout_i <= '1';
- current_state <= RELEASE_LVL1;
elsif TOKEN_MISSING_IN = '1' then
finished_readout_i <= '1';
+ if ENABLE_REINIT_IN = '1' then
+ mbo_configured_i <= '0';
+ reinit_running <= '1';
+ inc_reinit_counter <= '1';
+ reset_mbo_i <= '1';
+ current_state <= DO_REINIT;
+ else
+ inc_reinit_counter <= '1';
+ current_state <= WAIT_FOR_FINISHED_STORING;
+ end if;
+ end if;
+
+ when WAIT_FOR_FINISHED_STORING =>
+ if storing_data_is_finished = '1' then
current_state <= RELEASE_LVL1;
+ lvl1_release_i <= '1';
end if;
when RELEASE_LVL1 =>
lvl1_release_i <= '1';
if LVL1_TRG_DATA_VALID_IN = '0' then
current_state <= IDLE;
+ finished_cycle_i <= '1';
end if;
when others =>
end if;
end process;
-
+ proc_data_finished : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or current_state = IDLE then
+ storing_data_is_finished <= '0';
+ elsif FINISHED_STORING_DATA_IN = '1' then
+ storing_data_is_finished <= '1';
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
-- I/O
START_CALIB_OUT <= start_calib_i;
START_BEGRUN_OUT <= start_begrun_i;
START_READOUT_OUT <= start_readout_i;
+ START_SEND_DATA_OUT <= start_send_data_i;
FINISHED_READOUT_OUT <= finished_readout_i;
+ FINISHED_CYCLE_OUT <= finished_cycle_i;
+ RESET_MBO_OUT <= reset_mbo_i;
LVL1_RELEASE_OUT <= lvl1_release_i;
LVL1_STATUSBITS_OUT <= lvl1_statusbits_i;
- process(CLK)
+ INC_REINIT_OUT <= inc_reinit_counter;
+ INC_CALIB_OUT <= inc_calib_counter;
+ INC_TRIGGER_OUT <= inc_trigger_counter;
+
+ proc_statusbits : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' or current_state = IDLE then
end if;
end process;
-
-------------------------------------------------------------------------------
-- Debugging
-------------------------------------------------------------------------------
when TIMING_TRIGGER => state_bits <= x"2";
when CALIB_TRIGGER => state_bits <= x"3";
when DO_READOUT => state_bits <= x"4";
+ when WAIT_FOR_FINISHED_STORING => state_bits <= x"5";
+ when RELEASE_LVL1 => state_bits <= x"6";
+ when DO_REINIT => state_bits <= x"D";
+ when DO_REINIT2 => state_bits <= x"E";
when others => state_bits <= x"F";
end case;
end if;
end process;
-
DEBUG_REGISTER(3 downto 0) <= state_bits;
DEBUG_REGISTER(31 downto 4) <= (others => '0');
add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
add_file -vhdl -lib work "../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../trbnet/basics/state_sync.vhd"
add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd"
add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot_old.vhd"
add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_tx_control.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_rx_control.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_rx_full_packets.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_rx_checker.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_rx_comma_handler.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_data.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_8bit_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_16bit_bram_dualport.vhd"
add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
-- D000 - D13F SPI (2-3)
-- D200 Flash Select (4)
-- A000 - A0FF Threshold Bytes (0)
+-- E000 Readback Memory
+-- E100 Debugging Memory
--
-- 0x20 Bit 0 -> reset internal logic
-- 0x20 Bit 15 -> reboot fpga
entity mdc_oepb is
generic(
REGIO_NUM_STAT_REGS : integer := 1;
- REGIO_NUM_CTRL_REGS : integer := 1
+ REGIO_NUM_CTRL_REGS : integer := 2
);
port(
--Clocks
signal readback_mem_empty : std_logic;
signal readback_mem_ready : std_logic;
signal readback_mem_data_out : std_logic_vector(31 downto 0);
- signal readback_mem_write : std_logic;
- signal last_rb_read_enable_in : std_logic;
signal readback_mem_write_handler : std_logic;
signal readback_mem_full : std_logic;
- signal rb_fifo_input : std_logic_vector(17 downto 0);
- signal last_rb_fifo_input : std_logic_vector(17 downto 0);
+ --Debug Fifo
+ signal dbf_mem_read : std_logic;
+ signal dbf_mem_empty : std_logic;
+ signal dbf_mem_ready : std_logic;
+ signal dbf_mem_data_out : std_logic_vector(35 downto 0);
+ signal dbf_mem_write : std_logic;
+ signal last_dbf_read_enable_in : std_logic;
+ signal dbf_mem_write_handler : std_logic;
+ signal dbf_mem_full : std_logic;
+ signal dbf_fifo_input : std_logic_vector(35 downto 0);
+ signal last_dbf_fifo_input : std_logic_vector(35 downto 0);
--Status Registers
signal statreg_read : std_logic;
signal statreg_addr : std_logic_vector(3 downto 0);
signal statreg_data : std_logic_vector(31 downto 0);
+ --Statistic Registers
+ signal statisticreg_read : std_logic;
+ signal statisticreg_write : std_logic;
+ signal statisticreg_ready : std_logic;
+ signal statisticreg_addr : std_logic_vector(3 downto 0);
+ signal statisticreg_data : std_logic_vector(31 downto 0);
+
signal debug_mdc_control_i : std_logic_vector(31 downto 0);
signal debug_lvl1_handler : std_logic_vector(15 downto 0);
signal blink_enable : std_logic;
signal time_counter : unsigned(9 downto 0);
+ signal debug_data_handler_i : std_logic_vector(31 downto 0);
+ signal debug_ipu_handler_i : std_logic_vector(31 downto 0);
+ signal med_stat_reg_i : std_logic_vector(31 downto 0);
+ signal buf_reset_led : std_logic;
+ signal buf_restart_led : std_logic;
+ signal buf_request_led : std_logic;
+
begin
---------------------------------------------------------------------
LOCK => pll_locked
);
+ reset_async <= not pll_locked;
+
---------------------------------------------------------------------
-- Reset handler
---------------------------------------------------------------------
begin
if rising_edge(CLK) then
if MED_STAT_OP(13) = '1' or pll_locked = '0' then --pll not locked or reset request received
- reset_counter <= x"000F00";
+ reset_counter <= x"00000E";
reset_internal <= '1';
reset_startup <= '1';
- elsif MED_STAT_OP(14) = '1' then --no cable connected
+ elsif MED_STAT_OP(14) = '1' and reset_counter >= x"000F00" then --no cable connected
reset_counter <= x"000F00";
reset_startup <= '0';
reset_internal <= '1';
elsif( reset_counter = x"000FEF" ) then --end of reset cycle reached
- reset_startup <= '0';
+ reset_startup <= '0';
reset_internal <= '0';
reset_counter <= x"000FEF";
else --update reset counter
CLK_25 => CLK,
CLK_EN => '1',
RESET => reset_startup, --reset_internal,
- CLEAR => reset_startup,
+ CLEAR => reset_async,
--Internal Connection
MED_DATA_IN => MED_DATA_OUT,
-- Status and control port
STAT_OP => MED_STAT_OP,
CTRL_OP => MED_CTRL_OP,
+ STAT_REG_OUT => med_stat_reg_i,
STAT_DEBUG => MED_STAT_DEBUG,
CTRL_DEBUG => (others => '0')
);
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13,
+ DATA_BUFFER_DEPTH => 13, --13
DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-1024,
+ DATA_BUFFER_FULL_THRESH => 2**11-600, --2**13-1024
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
STAT_DEBUG_IPU => open,
STAT_DEBUG_1 => open,
STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT=> open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_DEBUG_DATA_HANDLER_OUT=> debug_data_handler_i,
+ STAT_DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i,
CTRL_MPLEX => (others => '0'),
IOBUF_CTRL_GEN => (others => '0'),
STAT_ONEWIRE => open,
THE_REG_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 7,
- PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", 5 => x"e000", 6 => x"9000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0, 5 => 0, 6 => 4, others => 0)
+ PORT_NUMBER => 9,
+ PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200",
+ 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0,
+ 5 => 0, 6 => 4, 7 => 0, 8 => 4, others => 0)
)
port map(
CLK => clk_100,
BUS_WRITE_ACK_IN(4) => flash_rom_write,
BUS_NO_MORE_DATA_IN(4) => '0',
BUS_UNKNOWN_ADDR_IN(4) => '0',
- --Debugging memory
+ --Readback memory
BUS_READ_ENABLE_OUT(5) => readback_mem_read,
BUS_WRITE_ENABLE_OUT(5) => readback_mem_write_handler,
BUS_DATA_OUT(5*32+31 downto 5*32) => open,
BUS_ADDR_OUT(5*16+15 downto 5*16) => open,
BUS_TIMEOUT_OUT(5) => open,
- BUS_DATA_IN(5*32+31 downto 5*32) => readback_mem_data_out,
+ BUS_DATA_IN(5*32+31 downto 5*32) => readback_mem_data_out(31 downto 0),
BUS_DATAREADY_IN(5) => readback_mem_ready,
BUS_WRITE_ACK_IN(5) => '0',
BUS_NO_MORE_DATA_IN(5) => readback_mem_empty,
BUS_WRITE_ACK_IN(6) => '0',
BUS_NO_MORE_DATA_IN(6) => '0',
BUS_UNKNOWN_ADDR_IN(6) => statreg_write,
+ --Debugging memory
+ BUS_READ_ENABLE_OUT(7) => dbf_mem_read,
+ BUS_WRITE_ENABLE_OUT(7) => dbf_mem_write_handler,
+ BUS_DATA_OUT(7*32+31 downto 7*32) => open,
+ BUS_ADDR_OUT(7*16+15 downto 7*16) => open,
+ BUS_TIMEOUT_OUT(7) => open,
+ BUS_DATA_IN(7*32+31 downto 7*32) => dbf_mem_data_out(31 downto 0),
+ BUS_DATAREADY_IN(7) => dbf_mem_ready,
+ BUS_WRITE_ACK_IN(7) => '0',
+ BUS_NO_MORE_DATA_IN(7) => dbf_mem_empty,
+ BUS_UNKNOWN_ADDR_IN(7) => dbf_mem_write_handler,
+ --Statistics Registers
+ BUS_READ_ENABLE_OUT(8) => statisticreg_read,
+ BUS_WRITE_ENABLE_OUT(8) => statisticreg_write,
+ BUS_DATA_OUT(8*32+31 downto 8*32) => open,
+ BUS_ADDR_OUT(8*16+3 downto 8*16) => statisticreg_addr,
+ BUS_ADDR_OUT(8*16+15 downto 8*16+4) => open,
+ BUS_TIMEOUT_OUT(8) => open,
+ BUS_DATA_IN(8*32+31 downto 8*32) => statisticreg_data,
+ BUS_DATAREADY_IN(8) => statisticreg_ready,
+ BUS_WRITE_ACK_IN(8) => '0',
+ BUS_NO_MORE_DATA_IN(8) => '0',
+ BUS_UNKNOWN_ADDR_IN(8) => statisticreg_write,
--Debugging
STAT_DEBUG => open
);
-------------------------------------------------------------------------------
--- Readback FiFo (used for LVL1 trigger handler)
+-- Readback FiFo (used for Debugging)
-------------------------------------------------------------------------------
- THE_TDC_READBACK_MEM : fifo_18x2k_oreg
+ THE_TDC_READBACK_MEM : fifo_36x4k_oreg
port map (
- Data(17 downto 0) => last_rb_fifo_input,
+ Data => dbf_fifo_input,
Clock => clk_100,
AmFullThresh => (others => '1'),
- WrEn => readback_mem_write,
- RdEn => readback_mem_read,
+ WrEn => dbf_mem_write,
+ RdEn => dbf_mem_read,
Reset => reset_internal,
- Q => readback_mem_data_out(17 downto 0),
- Empty => readback_mem_empty,
- Full => readback_mem_full
+ Q => dbf_mem_data_out(35 downto 0),
+ Empty => dbf_mem_empty,
+ Full => dbf_mem_full
);
- rb_fifo_input(15 downto 0) <= debug_lvl1_handler;
- rb_fifo_input(17 downto 16) <= "00";
+ dbf_fifo_input(3 downto 0) <= debug_ipu_handler_i(7 downto 4);
+ dbf_fifo_input(7 downto 4) <= debug_ipu_handler_i(11 downto 8);
+ dbf_fifo_input(11 downto 8) <= debug_ipu_handler_i(3 downto 0);
+ dbf_fifo_input(14 downto 12) <= debug_data_handler_i(14 downto 12);
+ dbf_fifo_input(15) <= '0';
+ dbf_fifo_input(17 downto 16) <= debug_data_handler_i(1 downto 0);
+ dbf_fifo_input(19 downto 18) <= (others => '0');
+ dbf_fifo_input(23 downto 20) <= debug_data_handler_i(7 downto 4);
+ dbf_fifo_input(31 downto 24) <= debug_ipu_handler_i(23 downto 16);
process(clk_100)
begin
if rising_edge(clk_100) then
- last_rb_fifo_input <= rb_fifo_input;
- if rb_fifo_input /= last_rb_fifo_input and readback_mem_full = '0' then
- readback_mem_write <= '1';
+ last_dbf_fifo_input <= dbf_fifo_input;
+ if dbf_mem_full = '0' and (debug_ipu_handler_i(3 downto 0) /= "0000") then
+ dbf_mem_write <= '1';
else
- readback_mem_write <= '0';
+ dbf_mem_write <= '0';
end if;
- last_rb_read_enable_in <= readback_mem_read;
- readback_mem_ready <= last_rb_read_enable_in;
+ last_dbf_read_enable_in <= dbf_mem_read;
+ dbf_mem_ready <= last_dbf_read_enable_in;
end if;
end process;
- readback_mem_data_out(31 downto 18) <= (others => '0');
+-- DEBUG_OUT( 0) <= dat_fifo_read(0);
+-- DEBUG_OUT( 1) <= dat_fifo_valid_read;
+-- DEBUG_OUT( 2) <= ipu_dataready_i;
+-- DEBUG_OUT( 3) <= ipu_read_in;
+-- DEBUG_OUT( 7 downto 4) <= DAT_DATA_FLAGS_IN(3 downto 0);
+-- DEBUG_OUT(11 downto 8) <= state_bits;
+-- DEBUG_OUT(16) <= data_buffer_write(0);
+-- DEBUG_OUT(17) <= IPU_DATA_READ_IN(0);
+-- DEBUG_OUT(23 downto 20) <= data_buffer_data_in(35 downto 32);
+
+-- handler_ipu
+-- STATUS_OUT( 3 downto 0) <= state_bits;
+-- STATUS_OUT( 4) <= dat_fifo_read(0);
+-- STATUS_OUT( 5) <= dat_fifo_valid_read;
+-- STATUS_OUT( 6) <= ipu_dataready_i;
+-- STATUS_OUT( 7) <= ipu_read_in;
+-- STATUS_OUT(11 downto 8) <= DAT_DATA_FLAGS_IN(3 downto 0);
+-- STATUS_OUT(11 downto 4) <= (others => '0');
+-- STATUS_OUT(12) <= error_not_found;
+-- STATUS_OUT(13) <= error_missing;
+-- STATUS_OUT(14) <= error_sync;
+-- STATUS_OUT(15) <= error_not_configured;
+-- STATUS_OUT(31 downto 16) <= (others => '0');
+--
+--
+-- handler_data
+-- DEBUG_OUT(0) <= data_buffer_write(0);
+-- DEBUG_OUT(1) <= IPU_DATA_READ_IN(0);
+-- DEBUG_OUT(3 downto 2) <= "00";
+-- DEBUG_OUT(7 downto 4) <= data_buffer_data_in(35 downto 32);
+-- DEBUG_OUT(10 downto 8) <= lvl1_state_bits;
+-- DEBUG_OUT(11) <= '0';
+-- DEBUG_OUT(14 downto 12) <= buffer_state_bits(0);
+-- DEBUG_OUT(31 downto 15) <= (others => '0');
---------------------------------------------------------------------
STAT_READ_ENABLE_IN => statreg_read,
STAT_READY_OUT => statreg_ready,
- RB_DATA_OUT => open, --readback_mem_data_out,
- RB_READ_ENABLE_IN => '0', --readback_mem_read,
- RB_READY_OUT => open, --readback_mem_ready,
- RB_EMPTY_OUT => open, --readback_mem_empty,
+ STATISTIC_ADDR_IN => statisticreg_addr,
+ STATISTIC_DATA_OUT => statisticreg_data,
+ STATISTIC_READ_IN => statisticreg_read,
+ STATISTIC_READY_OUT => statisticreg_ready,
+
+ RB_DATA_OUT => readback_mem_data_out,
+ RB_READ_ENABLE_IN => readback_mem_read,
+ RB_READY_OUT => readback_mem_ready,
+ RB_EMPTY_OUT => readback_mem_empty,
COMMON_STAT_REG_OUT => mdccontrol_common_stat_reg_out(63 downto 0),
COMMON_CTRL_REG_IN => reg_common_ctrl_reg_out,
-------------------------------------------------------------------------------
-- LED
-------------------------------------------------------------------------------
- D(4) <= not led_blink;
- D(3) <= not led_blink;
- D(2) <= not led_blink;
- D(1) <= not led_blink;
+ D(4) <= not buf_restart_led; -- toggle with restart
+ D(3) <= not buf_request_led; -- toggle with request
+ D(2) <= not buf_reset_led; -- toggle with network reset
+ D(1) <= med_stat_debug(51); -- not comma locked
+
process(clk_100)
begin
if timer_ticks(1) = '1' then
time_counter <= time_counter + to_unsigned(1,1);
end if;
+
if blink_enable = '1' then
led_blink <= time_counter(8);
else
led_blink <= '0';
end if;
+
+ if med_stat_op(13) = '1' then
+ buf_reset_led <= not buf_reset_led;
+ end if;
+ if med_stat_debug(17) = '1' then
+ buf_restart_led <= not buf_restart_led;
+ end if;
+ if med_stat_debug(16) = '1' then
+ buf_request_led <= not buf_request_led;
+ end if;
+
+-- TAD <= MED_STAT_DEBUG(26 downto 18); --rx data & k
+-- TAOD<= MED_STAT_DEBUG(52); --c_reset
+-- TDST<= MED_STAT_DEBUG(53); --cnt(4)
+-- GDE <= reset_internal;
+-- RDYI <= reset_startup;
+-- MODD <= MED_STAT_OP(14);
+-- RES <= MED_STAT_OP(15);
+-- TOK <= MED_STAT_OP(13);
+
end if;
end process;
- reg_common_stat_reg_in(13 downto 0) <= mdccontrol_common_stat_reg_out(13 downto 0);
- reg_common_stat_reg_in(14) <= sederr_i;
- reg_common_stat_reg_in(63 downto 15) <= mdccontrol_common_stat_reg_out(63 downto 15);
- blink_enable <= reg_registers_out(32);
+
+ reg_common_stat_reg_in(13 downto 0) <= mdccontrol_common_stat_reg_out(13 downto 0);
+ reg_common_stat_reg_in(14) <= sederr_i;
+ reg_common_stat_reg_in(63 downto 15) <= mdccontrol_common_stat_reg_out(63 downto 15);
+ reg_common_stat_reg_in(143 downto 64) <= (others => '0');
+ reg_common_stat_reg_in(159 downto 144) <= (others => '0');
+ blink_enable <= reg_registers_out(32);
-------------------------------------------------------------------------------
-- pins not used
-------------------------------------------------------------------------------
-
+-- STAT_DEBUG(16) <= request_retransmit_i;
+-- STAT_DEBUG(17) <= start_retransmit_i;
+-- STAT_DEBUG(25 downto 18) <= rx_data;
+-- STAT_DEBUG(26) <= rx_k;
+-- STAT_DEBUG(31 downto 27) <= (others => '0');
-------------------------------------------------------------------------------
-- SEU circuit
-------------------------------------------------------------------------------
signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
signal common_ctrl_reg : std_logic_vector(95 downto 0);
- signal ctrl_reg : std_logic_vector(63 downto 0);
+ signal ctrl_reg : std_logic_vector(127 downto 0);
signal token_back_i : std_logic;
signal ram_address : std_logic_vector(8 downto 0);
reset_internal <= '0' after 100 ns;
CLK <= not CLK after 5 ns;
- ctrl_reg <= x"0000000000000010";
+ ctrl_reg <= (4 => '1', 42 => '1', others => '0');
TRSV <= '0';
trg_number_i <= (others => '0');
trg_type_i <= x"1";
trg_information_i<= (others => '0');
- wait for 1 ms;
+ wait for 4.1 ms;
+ COM_STOP_P <= '1';
+ wait for 100 ns;
+ COM_STOP_P <= '0';
+ wait for 50 ns;
+ wait until rising_edge(CLK);
+ trg_timing_valid_i <= '1';
+ wait until rising_edge(CLK);
+ trg_timing_valid_i <= '0';
+ trg_int_number_i <= std_logic_vector(to_unsigned(1,16));
+ wait for 200 us;
+ wait until rising_edge(CLK);
COM_STOP_P <= '1';
wait for 100 ns;
COM_STOP_P <= '0';
trg_timing_valid_i <= '0';
wait for 400 us;
wait until rising_edge(CLK);
- trg_type_i <= x"9";
+ trg_type_i <= x"E";
trg_data_valid_i <= '1';
+ trg_number_i <= std_logic_vector(to_unsigned(1,16));
trg_notiming_valid_i <= '1';
wait for 50 ns;
wait until rising_edge(CLK);
TDST <= '0';
wait for 20 ns;
end loop;
+ if j = 2 then
+ wait;
+ end if;
token_back_i <= '1';
wait for 30 ns;
token_back_i <= '0';
STAT_READ_ENABLE_IN => '0',
STAT_READY_OUT => open,
+ STATISTIC_ADDR_IN => (others => '0'),
+ STATISTIC_DATA_OUT => open,
+ STATISTIC_READ_IN => '0',
+ STATISTIC_READY_OUT => open,
+
RB_DATA_OUT => open,
RB_READ_ENABLE_IN => '0',
RB_READY_OUT => open,
jspc29 / mdcoep.git / commitdiff