Uplink serdesses are all the same on 'A3', Folder structure modified. VHDL is in...

diff --git a/code/ip/serdes_4_sync_downstream.txt b/code/ip/serdes_4_sync_downstream.txt
new file mode 100644 (file)
index 0000000..bf7c29c
--- /dev/null
+++ b/code/ip/serdes_4_sync_downstream.txt
@@ -0,0 +1,163 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH1_PROTOCOL            "G8B10B"
+CH2_PROTOCOL            "G8B10B"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "RXTX"
+CH2_MODE                "RXTX"
+CH3_MODE                "RXTX"
+CH0_CDR_SRC       "REFCLK_CORE"
+CH1_CDR_SRC       "REFCLK_CORE"
+CH2_CDR_SRC       "REFCLK_CORE"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+CH1_RX_DATARATE_RANGE   "MEDHIGH"
+CH2_RX_DATARATE_RANGE   "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH0_RX_DATA_RATE        "FULL"
+CH1_RX_DATA_RATE        "FULL"
+CH2_RX_DATA_RATE        "FULL"
+CH3_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH1_TX_DATA_RATE        "FULL"
+CH2_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH1_TX_DATA_WIDTH       "8"
+CH2_TX_DATA_WIDTH       "8"
+CH3_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH1_RX_DATA_WIDTH        "8"
+CH2_RX_DATA_WIDTH        "8"
+CH3_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH1_TX_FIFO       "DISABLED"
+CH2_TX_FIFO       "DISABLED"
+CH3_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "DISABLED"
+CH1_RX_FIFO        "DISABLED"
+CH2_RX_FIFO        "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH0_TDRV      "0"
+CH1_TDRV      "0"
+CH2_TDRV      "0"
+CH3_TDRV      "0"
+#CH0_TX_FICLK_RATE      200
+#CH1_TX_FICLK_RATE      200
+#CH2_TX_FICLK_RATE      200
+#CH3_TX_FICLK_RATE      200
+#CH0_RXREFCLK_RATE        "200"
+#CH1_RXREFCLK_RATE        "200"
+#CH2_RXREFCLK_RATE        "200"
+#CH3_RXREFCLK_RATE        "200"
+#CH0_RX_FICLK_RATE      200
+#CH1_RX_FICLK_RATE      200
+#CH2_RX_FICLK_RATE      200
+#CH3_RX_FICLK_RATE      200
+CH0_TX_PRE              "DISABLED"
+CH1_TX_PRE              "DISABLED"
+CH2_TX_PRE              "DISABLED"
+CH3_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH1_RTERM_TX            "50"
+CH2_RTERM_TX            "50"
+CH3_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH1_RX_EQ               "DISABLED"
+CH2_RX_EQ               "DISABLED"
+CH3_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH1_RTERM_RX            "50"
+CH2_RTERM_RX            "50"
+CH3_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH1_RX_DCC              "DC"
+CH2_RX_DCC              "DC"
+CH3_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "2"
+CH1_LOS_THRESHOLD_LO       "2"
+CH2_LOS_THRESHOLD_LO       "2"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "DC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH1_TX_SB               "DISABLED"
+CH2_TX_SB               "DISABLED"
+CH3_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH1_RX_SB               "DISABLED"
+CH2_RX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH1_TX_8B10B            "ENABLED"
+CH2_TX_8B10B            "ENABLED"
+CH3_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH1_RX_8B10B            "ENABLED"
+CH2_RX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH1_COMMA_A             "1100000101"
+CH2_COMMA_A             "1100000101"
+CH3_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH1_COMMA_B             "0011111010"
+CH2_COMMA_B             "0011111010"
+CH3_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH1_COMMA_M             "1111111100"
+CH2_COMMA_M             "1111111100"
+CH3_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH1_RXWA                "ENABLED"
+CH2_RXWA                "ENABLED"
+CH3_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH1_ILSM                "ENABLED"
+CH2_ILSM                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH1_CTC                 "DISABLED"
+CH2_CTC                 "DISABLED"
+CH3_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0100011100"
+CH1_CC_MATCH4           "0100011100"
+CH2_CC_MATCH4           "0100011100"
+CH3_CC_MATCH4           "0100011100"
+CH0_CC_MATCH_MODE       "1"
+CH1_CC_MATCH_MODE       "1"
+CH2_CC_MATCH_MODE       "1"
+CH3_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CH1_CC_MIN_IPG          "3"
+CH2_CC_MIN_IPG          "3"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH1_SSLB                "DISABLED"
+CH2_SSLB                "DISABLED"
+CH3_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH1_SPLBPORTS           "DISABLED"
+CH2_SPLBPORTS           "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+CH1_PCSLBPORTS          "DISABLED"
+CH2_PCSLBPORTS          "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/code/ip/serdes_4_sync_hub_downstream.txt b/code/ip/serdes_4_sync_hub_downstream.txt
new file mode 100644 (file)
index 0000000..c22d59e
--- /dev/null
+++ b/code/ip/serdes_4_sync_hub_downstream.txt
@@ -0,0 +1,163 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH1_PROTOCOL            "G8B10B"
+CH2_PROTOCOL            "G8B10B"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "RXTX"
+CH2_MODE                "RXTX"
+CH3_MODE                "RXTX"
+CH0_CDR_SRC       "REFCLK_CORE"
+CH1_CDR_SRC       "REFCLK_CORE"
+CH2_CDR_SRC       "REFCLK_CORE"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+CH1_RX_DATARATE_RANGE   "MEDHIGH"
+CH2_RX_DATARATE_RANGE   "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH0_RX_DATA_RATE        "FULL"
+CH1_RX_DATA_RATE        "FULL"
+CH2_RX_DATA_RATE        "FULL"
+CH3_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH1_TX_DATA_RATE        "FULL"
+CH2_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH1_TX_DATA_WIDTH       "8"
+CH2_TX_DATA_WIDTH       "8"
+CH3_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH1_RX_DATA_WIDTH        "8"
+CH2_RX_DATA_WIDTH        "8"
+CH3_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH1_TX_FIFO       "DISABLED"
+CH2_TX_FIFO       "DISABLED"
+CH3_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "DISABLED"
+CH1_RX_FIFO        "DISABLED"
+CH2_RX_FIFO        "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH0_TDRV      "0"
+CH1_TDRV      "0"
+CH2_TDRV      "0"
+CH3_TDRV      "0"
+#CH0_TX_FICLK_RATE      200
+#CH1_TX_FICLK_RATE      200
+#CH2_TX_FICLK_RATE      200
+#CH3_TX_FICLK_RATE      200
+#CH0_RXREFCLK_RATE        "200"
+#CH1_RXREFCLK_RATE        "200"
+#CH2_RXREFCLK_RATE        "200"
+#CH3_RXREFCLK_RATE        "200"
+#CH0_RX_FICLK_RATE      200
+#CH1_RX_FICLK_RATE      200
+#CH2_RX_FICLK_RATE      200
+#CH3_RX_FICLK_RATE      200
+CH0_TX_PRE              "DISABLED"
+CH1_TX_PRE              "DISABLED"
+CH2_TX_PRE              "DISABLED"
+CH3_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH1_RTERM_TX            "50"
+CH2_RTERM_TX            "50"
+CH3_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH1_RX_EQ               "DISABLED"
+CH2_RX_EQ               "DISABLED"
+CH3_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH1_RTERM_RX            "50"
+CH2_RTERM_RX            "50"
+CH3_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH1_RX_DCC              "DC"
+CH2_RX_DCC              "DC"
+CH3_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "2"
+CH1_LOS_THRESHOLD_LO       "2"
+CH2_LOS_THRESHOLD_LO       "2"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH1_TX_SB               "DISABLED"
+CH2_TX_SB               "DISABLED"
+CH3_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH1_RX_SB               "DISABLED"
+CH2_RX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH1_TX_8B10B            "ENABLED"
+CH2_TX_8B10B            "ENABLED"
+CH3_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH1_RX_8B10B            "ENABLED"
+CH2_RX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH1_COMMA_A             "1100000101"
+CH2_COMMA_A             "1100000101"
+CH3_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH1_COMMA_B             "0011111010"
+CH2_COMMA_B             "0011111010"
+CH3_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH1_COMMA_M             "1111111100"
+CH2_COMMA_M             "1111111100"
+CH3_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH1_RXWA                "ENABLED"
+CH2_RXWA                "ENABLED"
+CH3_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH1_ILSM                "ENABLED"
+CH2_ILSM                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH1_CTC                 "DISABLED"
+CH2_CTC                 "DISABLED"
+CH3_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0100011100"
+CH1_CC_MATCH4           "010000000000011100"
+CH2_CC_MATCH4           "010000000000011100"
+CH3_CC_MATCH4           "010000000000011100"
+CH0_CC_MATCH_MODE       "1"
+CH1_CC_MATCH_MODE       "1"
+CH2_CC_MATCH_MODE       "1"
+CH3_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CH1_CC_MIN_IPG          "3"
+CH2_CC_MIN_IPG          "3"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH1_SSLB                "DISABLED"
+CH2_SSLB                "DISABLED"
+CH3_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH1_SPLBPORTS           "DISABLED"
+CH2_SPLBPORTS           "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+CH1_PCSLBPORTS          "DISABLED"
+CH2_PCSLBPORTS          "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/code/ip/serdes_sync_client_upstream.txt b/code/ip/serdes_sync_client_upstream.txt
new file mode 100644 (file)
index 0000000..b6d5e8e
--- /dev/null
+++ b/code/ip/serdes_sync_client_upstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "DISABLED"
+CH0_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200.0
+CH0_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "DISABLED"
+CH0_TDRV      "0"
+#CH0_TX_FICLK_RATE      200.0
+#CH0_RXREFCLK_RATE        "200.0"
+#CH0_RX_FICLK_RATE      200.0
+CH0_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "3"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0000000000"
+CH0_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+INT_ALL                 "ENABLED"
+QD_REFCK2CORE           "DISABLED"
+
+

diff --git a/code/ip/serdes_sync_hub_upstream.txt b/code/ip/serdes_sync_hub_upstream.txt
new file mode 100644 (file)
index 0000000..a057cb3
--- /dev/null
+++ b/code/ip/serdes_sync_hub_upstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "RXTX"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH3_RX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH        "8"
+CH3_TX_FIFO       "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH3_TDRV      "0"
+#CH3_TX_FICLK_RATE      200
+#CH3_RXREFCLK_RATE        "200"
+#CH3_RX_FICLK_RATE      200
+CH3_TX_PRE              "DISABLED"
+CH3_RTERM_TX            "50"
+CH3_RX_EQ               "DISABLED"
+CH3_RTERM_RX            "50"
+CH3_RX_DCC              "DC"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH3_TX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH3_TX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH3_COMMA_A             "1100000101"
+CH3_COMMA_B             "0011111010"
+CH3_COMMA_M             "1111111100"
+CH3_RXWA                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH3_CTC                 "DISABLED"
+CH3_CC_MATCH4           "0100011100"
+CH3_CC_MATCH_MODE       "1"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH3_SSLB                "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt
new file mode 100644 (file)
index 0000000..ec77632
--- /dev/null
+++ b/code/ip/serdes_sync_source_downstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH0_PROTOCOL            "G8B10B"
+CH0_MODE                "RXTX"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "DISABLED"
+CH0_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH0_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH0_RX_DATA_RATE        "FULL"
+CH0_TX_DATA_RATE        "FULL"
+CH0_TX_DATA_WIDTH       "8"
+CH0_RX_DATA_WIDTH        "8"
+CH0_TX_FIFO       "DISABLED"
+CH0_RX_FIFO        "DISABLED"
+CH0_TDRV      "0"
+#CH0_TX_FICLK_RATE      200
+#CH0_RXREFCLK_RATE        "200"
+#CH0_RX_FICLK_RATE      200
+CH0_TX_PRE              "DISABLED"
+CH0_RTERM_TX            "50"
+CH0_RX_EQ               "DISABLED"
+CH0_RTERM_RX            "50"
+CH0_RX_DCC              "DC"
+CH0_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH0_TX_SB               "DISABLED"
+CH0_RX_SB               "DISABLED"
+CH0_TX_8B10B            "ENABLED"
+CH0_RX_8B10B            "ENABLED"
+CH0_COMMA_A             "1100000101"
+CH0_COMMA_B             "0011111010"
+CH0_COMMA_M             "1111111100"
+CH0_RXWA                "ENABLED"
+CH0_ILSM                "ENABLED"
+CH0_CTC                 "DISABLED"
+CH0_CC_MATCH4           "0100011100"
+CH0_CC_MATCH_MODE       "1"
+CH0_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH0_SSLB                "DISABLED"
+CH0_SPLBPORTS           "DISABLED"
+CH0_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+

diff --git a/code/ip/serdes_sync_upstream.txt b/code/ip/serdes_sync_upstream.txt
new file mode 100644 (file)
index 0000000..a057cb3
--- /dev/null
+++ b/code/ip/serdes_sync_upstream.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH3_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "DISABLED"
+CH3_MODE                "RXTX"
+CH3_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH3_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH3_RX_DATA_RATE        "FULL"
+CH3_TX_DATA_RATE        "FULL"
+CH3_TX_DATA_WIDTH       "8"
+CH3_RX_DATA_WIDTH        "8"
+CH3_TX_FIFO       "DISABLED"
+CH3_RX_FIFO        "DISABLED"
+CH3_TDRV      "0"
+#CH3_TX_FICLK_RATE      200
+#CH3_RXREFCLK_RATE        "200"
+#CH3_RX_FICLK_RATE      200
+CH3_TX_PRE              "DISABLED"
+CH3_RTERM_TX            "50"
+CH3_RX_EQ               "DISABLED"
+CH3_RTERM_RX            "50"
+CH3_RX_DCC              "DC"
+CH3_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH3_TX_SB               "DISABLED"
+CH3_RX_SB               "DISABLED"
+CH3_TX_8B10B            "ENABLED"
+CH3_RX_8B10B            "ENABLED"
+CH3_COMMA_A             "1100000101"
+CH3_COMMA_B             "0011111010"
+CH3_COMMA_M             "1111111100"
+CH3_RXWA                "ENABLED"
+CH3_ILSM                "ENABLED"
+CH3_CTC                 "DISABLED"
+CH3_CC_MATCH4           "0100011100"
+CH3_CC_MATCH_MODE       "1"
+CH3_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH3_SSLB                "DISABLED"
+CH3_SPLBPORTS           "DISABLED"
+CH3_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "ENABLED"
+
+