ECP3 works well now, link seems stable

diff --git a/gbe_trb/base/gbe_lsm.vhd b/gbe_trb/base/gbe_lsm.vhd
index b91c0a8160a81544745c4b4bd22b42c392bd721f..03f9cc4c67efc416a34fce8bc6ff231c48d14300 100644 (file)
--- a/gbe_trb/base/gbe_lsm.vhd
+++ b/gbe_trb/base/gbe_lsm.vhd
@@ -16,6 +16,8 @@ entity gbe_lsm is
     AN_RESTART_OUT       : out std_logic;\r
     MAC_RECONF_OUT       : out std_logic;\r
     LINK_ACTIVE_OUT      : out std_logic;\r
+    LINK_START_OUT       : out std_logic;\r
+    LINK_STOP_OUT        : out std_logic;\r
     --\r
     DEBUG                : out std_logic_vector(15 downto 0)\r
   );\r
@@ -30,7 +32,7 @@ architecture gbe_lsm_arch of gbe_lsm is
   signal STATE, NEXT_STATE    : state_t;\r
 \r
 -- Signals\r
-  signal dly_ctr         : unsigned(24 downto 0);\r
+  signal dly_ctr         : unsigned(28 downto 0); -- was 24\r
   signal dly_ctr_done    : std_logic;\r
   signal dly_ctr_rst_x   : std_logic;\r
   signal dly_ctr_rst     : std_logic;\r
@@ -38,7 +40,11 @@ architecture gbe_lsm_arch of gbe_lsm is
   signal reconf_mac      : std_logic;\r
   signal restart_an_x    : std_logic;\r
   signal restart_an      : std_logic;\r
-\r
+  signal link_start_x    : std_logic;\r
+  signal link_start      : std_logic;\r
+  signal link_stop_x     : std_logic;\r
+  signal link_stop       : std_logic;\r
+  \r
 begin\r
  \r
   THE_DLY_CTR: process( CLK, RESET )\r
@@ -66,11 +72,15 @@ begin
       restart_an <= '0';\r
       reconf_mac <= '0';\r
       dly_ctr_rst <= '1';\r
+      link_start <= '0';\r
+      link_stop <= '0';\r
     elsif( rising_edge(CLK) ) then\r
       STATE <= NEXT_STATE;\r
       restart_an <= restart_an_x;\r
       reconf_mac <= reconf_mac_x;\r
       dly_ctr_rst <= dly_ctr_rst_x;\r
+      link_start <= link_start_x;\r
+      link_stop <= link_stop_x;\r
     end if;\r
   end process THE_FSM;\r
 \r
@@ -79,6 +89,8 @@ begin
     restart_an_x <= '0';\r
     reconf_mac_x <= '0';\r
     dly_ctr_rst_x <= '1';\r
+    link_start_x <= '0';\r
+    link_stop_x <= '0';\r
     \r
     case STATE is\r
 \r
@@ -119,12 +131,13 @@ begin
         end if;\r
 \r
       when ENABLE_MAC =>\r
-        if   ( SERDES_ACTIVE_IN = '0' ) then\r
+        if   ( (SERDES_ACTIVE_IN = '0') or (AN_COMPLETE_IN = '0') ) then\r
           -- SerDes broken\r
           NEXT_STATE <= INACTIVE;\r
         else\r
           if( MAC_READY_CONF_IN = '1' ) then\r
             NEXT_STATE <= ACTIVATED;\r
+            link_start_x <= '1';\r
           else \r
             NEXT_STATE <= ENABLE_MAC;\r
             reconf_mac_x <= '1';\r
@@ -132,9 +145,10 @@ begin
         end if;\r
 \r
       when ACTIVATED =>\r
-        if   ( SERDES_ACTIVE_IN = '0' ) then\r
+        if   ( (SERDES_ACTIVE_IN = '0') or (AN_COMPLETE_IN = '0') ) then\r
           -- SerDes broken\r
           NEXT_STATE <= INACTIVE;\r
+          link_stop_x <= '1';\r
         else\r
           NEXT_STATE <= ACTIVATED;\r
         end if;\r
@@ -147,5 +161,7 @@ begin
   AN_RESTART_OUT  <= restart_an;\r
   MAC_RECONF_OUT  <= reconf_mac;\r
   LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0';\r
+  LINK_START_OUT  <= link_start;\r
+  LINK_STOP_OUT   <= link_stop;\r
 \r
 end architecture;\r

diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
index 1d28e09b23ef5e4c4dcb96ff0e3331a16baa54d1..84ca503459e85584d9549722da702f6b41f4c3a2 100644 (file)
--- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd
@@ -54,12 +54,15 @@ entity gbe_med_fifo is
     MAC_RX_ERROR_OUT      : out std_logic;
     -- SerDes control
     TX_PLOL_LOL_OUT       : out std_logic;
+    RST_QD_C_IN           : in  std_logic;
     TX_PCS_RST_IN         : in  std_logic;
     RX_LINK_READY_OUT     : out std_logic_vector(3 downto 0);
     TX_LINK_READY_IN      : in  std_logic;
     -- Status
     PCS_AN_READY_OUT      : out std_logic_vector(3 downto 0); -- for internal SCTRL
     LINK_ACTIVE_OUT       : out std_logic_vector(3 downto 0); -- for internal SCTRL
+--    LINK_START_OUT        : out std_logic;
+--    LINK_STOP_OUT         : out std_logic;    
     TICK_MS_IN            : in  std_logic;
     -- syntonous operation
     MASTER_CLK_IN         : in  std_logic; -- master clock for TX parts
@@ -488,7 +491,7 @@ begin
     fpga_txrefclk        => MASTER_CLK_IN,
     tx_serdes_rst_c      => '0',
     tx_pll_lol_qd_s      => TX_PLOL_LOL_OUT,
-    rst_qd_c             => CLEAR, -- ONLY ONCE
+    rst_qd_c             => RST_QD_C_IN, --CLEAR, -- ONLY ONCE
     serdes_rst_qd_c      => '0',
     tx_sync_qd_c         => SYNC_TX_PLL_IN,
     -- SCI interface
@@ -535,65 +538,65 @@ begin
     
     CHANNEL_ACTIVE_GEN : if ((LINK_MODE(i) = c_IS_SLAVE) or (LINK_MODE(i) = c_IS_MASTER)) generate
 
-      THE_TX_PARSER: entity parser
-      port map(
-        CLK           => MASTER_CLK_IN,
-        RESET         => CLEAR,
-        --
-        PHY_D_IN      => sd_tx_data_src(i * 8 + 7 downto i * 8),
-        PHY_K_IN      => sd_tx_kcntl_src(i),
-        --
-        UNKNOWN_OUT   => unknown_tx_int(i),
-        IDLE_OUT      => idle_tx_int(i),
-        CFG_OUT       => cfg_tx_int(i)
-      );
-
-      THE_RX_PARSER: entity parser
-      port map(
-        CLK           => sd_rx_clk(i),
-        RESET         => CLEAR,
-        --
-        PHY_D_IN      => sd_rx_data_dst(i * 8 + 7 downto i * 8),
-        PHY_K_IN      => sd_rx_kcntl_dst(i),
-        --
-        UNKNOWN_OUT   => unknown_rx_int(i),
-        IDLE_OUT      => idle_rx_int(i),
-        CFG_OUT       => cfg_rx_int(i)
-      );
+--      THE_TX_PARSER: entity parser
+--      port map(
+--        CLK           => MASTER_CLK_IN,
+--        RESET         => CLEAR,
+--        --
+--        PHY_D_IN      => sd_tx_data_src(i * 8 + 7 downto i * 8),
+--        PHY_K_IN      => sd_tx_kcntl_src(i),
+--        --
+--        UNKNOWN_OUT   => unknown_tx_int(i),
+--        IDLE_OUT      => idle_tx_int(i),
+--        CFG_OUT       => cfg_tx_int(i)
+--      );
+--
+--      THE_RX_PARSER: entity parser
+--      port map(
+--        CLK           => sd_rx_clk(i),
+--        RESET         => CLEAR,
+--        --
+--        PHY_D_IN      => sd_rx_data_dst(i * 8 + 7 downto i * 8),
+--        PHY_K_IN      => sd_rx_kcntl_dst(i),
+--        --
+--        UNKNOWN_OUT   => unknown_rx_int(i),
+--        IDLE_OUT      => idle_rx_int(i),
+--        CFG_OUT       => cfg_rx_int(i)
+--      );
 
       -- Debug signals, MSB to LSB
-      DEBUG_OUT((i + 1) * 32 - 1)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 2)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 3)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 4)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 5)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 6)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 7)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 8)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 9)  <= '0';
-      DEBUG_OUT((i + 1) * 32 - 10) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 11) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 12) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 13) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 14) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 15) <= '0';
-      DEBUG_OUT((i + 1) * 32 - 16) <= mr_an_complete_i(i); -- (16)
-      DEBUG_OUT((i + 1) * 32 - 17) <= mac_ready_conf(i); -- (15)
-      DEBUG_OUT((i + 1) * 32 - 18) <= mac_reconf(i); -- (14)
-      DEBUG_OUT((i + 1) * 32 - 19) <= an_restart_i(i); -- (13)
-      DEBUG_OUT((i + 1) * 32 - 20) <= an_link_ok_i(i); -- (12)
-      DEBUG_OUT((i + 1) * 32 - 21) <= mr_page_rx_i(i); -- (11)
-      DEBUG_OUT((i + 1) * 32 - 22) <= cfg_rx_int(i); -- (10)
-      DEBUG_OUT((i + 1) * 32 - 23) <= idle_rx_int(i); -- (9)
-      DEBUG_OUT((i + 1) * 32 - 24) <= unknown_rx_int(i); -- (8)
-      DEBUG_OUT((i + 1) * 32 - 25) <= cfg_tx_int(i); -- (7)
-      DEBUG_OUT((i + 1) * 32 - 26) <= idle_tx_int(i); -- (6)
-      DEBUG_OUT((i + 1) * 32 - 27) <= unknown_tx_int(i); --(5)
-      DEBUG_OUT((i + 1) * 32 - 28) <= link_active(i); -- (4)
-      DEBUG_OUT((i + 1) * 32 - 29) <= link_rx_ready(i); -- (3)
-      DEBUG_OUT((i + 1) * 32 - 30) <= TX_LINK_READY_IN; -- (2)
-      DEBUG_OUT((i + 1) * 32 - 31) <= RESET; -- (1)
-      DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR; -- (0)
+      DEBUG_OUT(i * 32 + 31) <= '0'; -- (31)
+      DEBUG_OUT(i * 32 + 30) <= '0'; -- (30)
+      DEBUG_OUT(i * 32 + 29) <= '0'; -- (29)
+      DEBUG_OUT(i * 32 + 28) <= '0'; -- (28)
+      DEBUG_OUT(i * 32 + 27) <= '0'; -- (27)
+      DEBUG_OUT(i * 32 + 26) <= '0'; -- (26)
+      DEBUG_OUT(i * 32 + 25) <= '0'; -- (25)
+      DEBUG_OUT(i * 32 + 24) <= '0'; -- (24)
+      DEBUG_OUT(i * 32 + 23) <= '0'; -- (23)
+      DEBUG_OUT(i * 32 + 22) <= '0'; -- (22)
+      DEBUG_OUT(i * 32 + 21) <= '0'; -- (21)
+      DEBUG_OUT(i * 32 + 20) <= '0'; -- (20)
+      DEBUG_OUT(i * 32 + 19) <= TX_PCS_RST_IN; -- (19)
+      DEBUG_OUT(i * 32 + 18) <= rx_pcs_rst(i); -- (18)
+      DEBUG_OUT(i * 32 + 17) <= rx_serdes_rst(i); -- (17)
+      DEBUG_OUT(i * 32 + 16) <= rx_los_low(i); -- (16)
+      DEBUG_OUT(i * 32 + 15) <= lsm_status(i); -- (15)
+      DEBUG_OUT(i * 32 + 14) <= sd_rx_cv_error(i); -- (14)
+      DEBUG_OUT(i * 32 + 13) <= rx_cdr_lol(i); -- (13)
+      DEBUG_OUT(i * 32 + 12) <= sci_ch_i(0); -- (12)
+      DEBUG_OUT(i * 32 + 11) <= is_wap_zero(i); -- (11)
+      DEBUG_OUT(i * 32 + 10) <= sci_read_i; -- (10)
+      DEBUG_OUT(i * 32 + 9)  <= mac_ready_conf(i); -- (9)
+      DEBUG_OUT(i * 32 + 8)  <= mac_reconf(i); -- (8)
+      DEBUG_OUT(i * 32 + 7)  <= an_restart_i(i); -- (7)
+      DEBUG_OUT(i * 32 + 6)  <= an_link_ok_i(i); -- (6)
+      DEBUG_OUT(i * 32 + 5)  <= mr_page_rx_i(i); --(5)
+      DEBUG_OUT(i * 32 + 4)  <= link_active(i); -- (4)
+      DEBUG_OUT(i * 32 + 3)  <= link_rx_ready(i); -- (3)
+      DEBUG_OUT(i * 32 + 2)  <= TX_LINK_READY_IN; -- (2)
+      DEBUG_OUT(i * 32 + 1)  <= RESET; -- (1)
+      DEBUG_OUT(i * 32 + 0)  <= CLEAR; -- (0)
       
       powerup_ch(i)      <= '1';
       SD_TXDIS_OUT(i)    <= '0';
@@ -618,8 +621,9 @@ begin
       );
 
       -- BUG, WAP_REQUESTED_IN to be replaced by wap_requested_i()
-      is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = WAP_REQUESTED_IN) else '0';
-      
+--      is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = WAP_REQUESTED_IN) else '0';
+      is_wap_zero(i) <= '1' when (wa_position_i(i * 4 + 3 downto i * 4) = wap_requested_i(i * 4 + 3 downto i * 4)) else '0';
+
       -- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
       SYNC_RST_SIGS: entity work.signal_sync 
       generic map( WIDTH => 2 )
@@ -830,20 +834,6 @@ begin
         DEBUG                => open
       );
       
---      THE_FW_GBE_LSM: entity gbe_lsm
---      port map(
---        CLK                  => MASTER_CLK_IN,
---        RESET                => RESET,
---        -- 
---        MAC_AN_COMPLETE_IN   => an_link_ok_i(i),
---        MAC_READY_CONF_IN    => mac_ready_conf(i),
---        MAC_RECONF_OUT       => mac_reconf(i),
---        --
---        LINK_ACTIVE_OUT      => link_active(i),
---        --
---        DEBUG                => open
---      );
-
       -- RX ringbuffer
       THE_FW_RB: entity rx_rb 
       port map(

diff --git a/media_interfaces/sync/main_tx_reset_RS.vhd b/media_interfaces/sync/main_tx_reset_RS.vhd
index ae1ac24eaaf910c0ca2ee9bc3ed6becce2346d56..803747da3b1040d19556c0236c7f74cc2d6d81bc 100644 (file)
--- a/media_interfaces/sync/main_tx_reset_RS.vhd
+++ b/media_interfaces/sync/main_tx_reset_RS.vhd
@@ -19,7 +19,7 @@ end entity;
 \r
 architecture main_tx_reset_RS_arch of main_tx_reset_RS is\r
 \r
-  constant count_index : integer := 15; -- end of timer\r
+  constant count_index : integer := 18; -- end of timer\r
 \r
   type statetype is ( IDLE, WAIT_FOR_TIMER, SYNC_ALL, SYNC_DONE, NORMAL );\r
 \r
@@ -116,8 +116,12 @@ begin
       when WAIT_FOR_TIMER =>\r
         STATE_OUT <= x"2";\r
         tx_pcs_rst_ch_c_int <= '1';\r
-        if( (timer = '1') and (tx_pll_lol_all_q = '0') ) then\r
-          NEXT_STATE <= SYNC_ALL;\r
+        if( timer = '1' ) then\r
+          if( tx_pll_lol_all_q = '0' ) then\r
+            NEXT_STATE <= SYNC_ALL;\r
+          else\r
+            NEXT_STATE <= IDLE; -- restart timer\r
+          end if;\r
         else\r
           NEXT_STATE <= WAIT_FOR_TIMER;\r
         end if;\r