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\title{Noise performance and ionizing radiation tolerance of CMOS Monolithic Active Pixel Sensors using the $0.18\mum$ CMOS process}
-\author{Dennis Doering$^a$\thanks{doering@physik.uni-frankfurt.de; Phone: +49 69 798-47118}, Jerome Baudot$^b$, Michael Deveaux$^a$, Benjamin Linnik$^a$, Serhiy Senyukov$^b$, Stefan Strohauer$^a$, Joachim Stroth$^a$ and Marc Winter$^b$\\
+\author{Dennis Doering$^a$\thanks{doering@physik.uni-frankfurt.de; Phone: +49 69 798-47118}, Jerome Baudot$^b$, Michael Deveaux$^a$, Benjamin Linnik$^a$, Mathieu Goffe$^b$, Serhiy Senyukov$^b$, Stefan Strohauer$^a$, Joachim Stroth$^a$ and Marc Winter$^b$\\
\llap{$^a$} Institut für Kernphysik, Goethe University Frankfurt, Germany\\
\llap{$^b$}IPHC Strasbourg, France\\
E-mail: \email{doering@physik.uni-frankfurt.de}}
\abstract{CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few $\rm \mu m$), a detection efficiency of $ \gtrsim 99.9\%$, very low material budget ($0.05\%~\rm X_0$) and good radiation tolerance ($\gtrsim 1 \Mrad$, $\gtrsim 10^{14} \neqcm$) \cite{RESMDD2012}. This makes them an interesting technology for various applications in heavy ion and particle physics.\newline
-For the vertex detectors of CBM and ALICE, we are aiming to develop large scale sensors with an integration time of $30\mus$. Reaching this goal is eased by features available in CMOS-processes with $0.18\mum$ feature size. To exploit this option, some sensor designs are being migrated from the previously used $0.35\mum$ processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.}
+For the vertex detectors of CBM and ALICE, we are aiming to develop large scale sensors with an integration time of $30\mus$. Reaching this goal is eased by features available in CMOS-processes with $0.18\mum$ feature size. To exploit this option, some sensor designs have been migrated from the previously used $0.35\mum$ processes to this novel process. We report about our first findings with the devices obtained with a focus on noise and the tolerance to ionizing radiation.}
\keywords{ Radiation-hard detectors; Particle tracking detectors (solid-state detectors); Monolithic pixel detectors; CMOS-sensors; Monolithic active pixel sensors; Radiation damage}
\end{minipage}
\hspace{0.2cm}
\begin{minipage}{6cm}
-\caption{Cross sectional view of a CMOS sensor. The trajectory of an impinging particle (red arrow) and the diffusion paths of diffusing free electrons are shown.}
+\caption{Cross sectional view of a CMOS sensor. The trajectory of an impinging particle (single-pointed arrow) and the diffusion paths of diffusing free electrons are shown.}
\end{minipage}
\end{figure}
-Since recently, dedicated imaging processes with $0.18~\rm \upmu m$ feature size became available in industry. Those CMOS-processes provide the high-resistivity epitaxial layer discussed above. Moreover, they feature deep P- and N-wells, which allows conceptually for using full CMOS also in the pixel area\footnote{Without this feature, the N-well implantation required for building PMOS-transistors would act as parasitic collection diode and therefore destroy the sensing abilities of the pixel.}, which is helpful for improving the readout speed of the device. Finally, CMOS-processes with $0.18\mum$ feature size are known for providing an improved tolerance to ionizing radiation. In order to exploit those features, we aim to migrate our successful sensor designs to this new CMOS-process.
+Since recently, a dedicated imaging process with $0.18~\rm \upmu m$ feature size became available for particle detectors. This CMOS-process provides the high-resistivity epitaxial layer discussed above. Moreover, it features deep P- and N-wells, which allows conceptually for using full CMOS also in the pixel area\footnote{Without this feature, the N-well implantation required for building PMOS-transistors would act as parasitic collection diode and therefore destroy the sensing abilities of the pixel.}, which is helpful for improving the readout speed of the device. Finally, CMOS-processes with a smaller feature size are known for providing an improved tolerance to ionizing radiation. In order to exploit those features, we aim to migrate our successful sensor designs to this new CMOS-process.
\section{Sensor design}
-In a first step, some imager chips were designed to study the properties of sensing nodes integrated in the novel CMOS process. The exploratory chips were named MIMOSA-32, MIMOSA-32ter and MIMOSA-34. Each of those chips hosts matrices with 32 different pixels types, which vary in terms of pixel pitch, the details of the sensing node and preamplifier layouts. The 1024 pixels of each pixel matrix are arranged in 16 columns with 64 pixels per column. The columns are readout in parallel and their signal is sent to 16 external ADCs\footnote{Only 8 out of 16 columns were read out due to the limited number of ADCs available in IKF readout system. This restriction remains without impact on the conclusions of our study.}. The readout time is $32~ \rm \upmu s$, which represents the design goal of the future sensors for CBM and ALICE.
+In a first step, some exploratory devices were designed to study the properties of sensing nodes integrated in the novel CMOS process. The chips were named MIMOSA-32, MIMOSA-32ter and MIMOSA-34. Each of those chips host matrices with 32 different pixels types, which vary in terms of pixel pitch, as well as in the sensing node and preamplifier layouts. The 1024 pixels of each pixel matrix are arranged in 16 columns with 64 pixels per column. The columns are readout in parallel and their signal is sent to 16 external ADCs\footnote{Only 8 out of 16 columns were read out due to the limited number of ADCs available in IKF readout system. This restriction remains without impact on the conclusions of our study.}. The readout time is $32~ \rm \upmu s$, which represents the design goal of the future sensors for CBM and ALICE.
-In the pixels discussed in the following, the charge collected by the P$_{\rm Epi~ Layer}$/N$_{\rm Well}$-diode is stored in the parasitic capacity of the sensing node and hereafter buffered by means of a source follower (see figure \ref{fig:preamplifier}). The signal charge as well as the accumulated charge generated by the leakage current of the collection diode is cleared by means of a continuous bias, which is realized by means of a permanently opened reset switch based on a NMOS transistor (labeled reset-transistor in figure \ref{fig:preamplifier}). In this particular mode of operation, the switch should act as a high resistivity forward biased diode and the pixel should be equivalent to the self-bias pixels discussed in \cite{Deveaux2010428}.
+In the pixels discussed in the following, the charge collected by the P$_{\rm Epi~ Layer}$/N$_{\rm Well}$-diode is stored in the parasitic capacitance C of the sensing node and hereafter buffered by means of a source follower (see figure \ref{fig:preamplifier}). The signal charge as well as the accumulated charge generated by the leakage current of the collection diode is cleared by means of a continuous bias, which is realized by means of a permanently opened reset switch based on a NMOS transistor (labeled reset-transistor in figure \ref{fig:preamplifier}). In this particular mode of operation, the switch should act as a high resistivity forward biased diode and the pixel should be equivalent to the self-bias pixels discussed in \cite{Deveaux2010428}.
-Obviously, the charge-to-voltage amplification gain of our CMOS-pixels depends crucially on the size of the parasitic capacity of the sensing node. Contributers to this parasitic capacity are in particular the P$_{\rm Epi~ Layer}$/N$_{\rm Well}$-junction, the drain of the reset transistor and the gate of the source follower transistor. The smaller feature size of the $0.18~\rm \upmu m$-process allows for reducing the size and such the capacity of those structures, which turns into a sizable potential for improving the amplification gain of the pixel. However, reducing the diode size may come with drawbacks in terms of charge collection efficiency and reducing the size of the transistor gates was reported to cause significant 1/f- and RTS-noise in MAPS used for optical imaging \cite{RTS0.18,RTS0.182}.
+The charge-to-voltage amplification gain of our CMOS-pixels depends predominantly on the size of the parasitic capacitance of the sensing node. Contributors to this parasitic capacitance are in particular the P$_{\rm Epi~ Layer}$/N$_{\rm Well}$-junction, the drain of the reset transistor and the gate of the source follower transistor. The smaller feature size of the $0.18~\rm \upmu m$-process allows for reducing the size and such the capacitance of those structures, which turns into a sizable potential for improving the amplification gain of the pixel. However, reducing the diode size may come with drawbacks in terms of charge collection efficiency and reducing the size of the transistor gates was reported to cause significant 1/f- and RTS-noise in MAPS used for optical imaging \cite{RTS0.18,RTS0.182}.
\begin{figure}
\begin{minipage}[t]{8cm}
\end{minipage}
\end{figure}
-In order to find the optimal compromise between the different parameters, we compared the noise performances of different pixels. A first comparison was made between the pixels labeled as Pixel A-C in Table \ref{tab:Mi32-1-f-noise-table}. Those pixels host an identical diode of $\sim 11 \rm \upmu m^2$, an identical reset transistor but the layout of the source follower transistor was varied as listed in the table. As a benchmark, we use Pixel R, a well performing pixel manufactured in a high-resistivity $0.35~\rm \upmu m$-process\footnote{From MIMOSA-18AHR, see \cite{RESMDD2012} for further information.}.
+In order to find the optimal compromise between the different parameters, we compared the noise performances of different pixels. A first comparison was made between the pixels labeled as Pixel A to C in Table \ref{tab:Mi32-1-f-noise-table}. Those pixels host an identical sensing diode with a size of $\sim 11 \rm \upmu m^2$, an identical reset transistor but the layout of the source follower transistor was varied as listed in the table. As a benchmark, we use Pixel R, a well performing pixel manufactured in a high-resistivity $0.35~\rm \upmu m$-process\footnote{From MIMOSA-18AHR, see \cite{RESMDD2012} for further information.}.
\begin{table}[tbp]
\centering
Difference A$\rightarrow$C & & & & +15\% & +10\% & +8\% & +54\%\\
\hline
\end{tabular}
-\caption{Noise and gain in dependence of the source follower gate size. The uncertainties of the absolute measurements are 5\% for the gain and 10\% for the median noise. The diode size of all pixels listed is $11~\rm \upmu m$. The width of the gate of all reset transistors is $0.25~\rm \upmu m$ and the length is $0.20~\rm \upmu m$ (pixel A-C) and $0.30~\rm \upmu m$ (pixel D). The source follower transistor of pixel R has an enclosed layout. Note that the gain includes the gain of the external readout chain. Therefore, only the gain of pixels of the same chip can be compared.}
+\caption{Noise and gain in dependence of the source follower gate size. The uncertainties of the absolute measurements are 5\% for the gain and 10\% for the median noise. The diode size of all pixels listed is $11~\rm \upmu m^2$. The width of the gate of all reset transistors is $0.25~\rm \upmu m$ and the length is $0.20~\rm \upmu m$ (pixel A-C) and $0.30~\rm \upmu m$ (pixel D). The source follower transistor of pixel R has an enclosed layout. Note that the gain includes the gain of the external readout chain. Therefore, only the gain of pixels of the same chip can be compared.}
\label{tab:Mi32-1-f-noise-table}
\end{table}
-According to our measurement standard, we defined the noise as the standard deviation of the dark signal of the individual pixel after performing correlated double sampling, pedestal correction and common mode correction. Details on the related measurement procedure were discussed in \cite{Dev07}. The noise of a pixel matrix is defined as the median of the noise of all individual pixels of this matrix and was measured at a temperature of $T=20\rm^{\circ}C$. Typically the number of $\lesssim 1\%$ "noisy" pixel could be tolerated. Therefore, in the following, we evaluate not only the median value of the pixel noise distribution but also the noise limit so that $\gtrsim99\%$ of the pixels have a lower noise.
+According to our measurement standard, we defined the noise as the standard deviation of the dark signal of the individual pixel after performing correlated double sampling, pedestal correction and common mode correction. Details on the related measurement procedure were discussed in \cite{Dev07}. The noise of a pixel matrix is defined as the median of the noise of all individual pixels of this matrix and was measured at a temperature of $T=+20\rm^{\circ}C$. Typically the number of $\lesssim 1\%$ "noisy" pixel could be tolerated. Therefore, in the following, we evaluate not only the median value of the pixel noise distribution but also the noise limit so that $\gtrsim99\%$ of the pixels have a lower noise.
\subsection{Impact of the transistor layout on the noise}
-The noise distributions observed the different pixels types are shown in figure \ref{fig:Mi18Mi32Mi34Noisevergleich}, which compares the performances of the \mbox{Pixel A} ($0.18\rm ~\upmu m$, biggest source follower transistor gate) with the one of the established \mbox{Pixel R} \mbox{($0.35\rm ~\upmu m$ feature} size). \mbox{Pixel R} shows a mostly Gaussian distribution with an median noise of $10.7 \rm \e$, and $\gtrsim 99\%$ of all pixels indicate a noise below $18 \rm \e$. The noise of \mbox{Pixel A} follows a broad distribution with a median of $19.8\rm \e$ and $\gtrsim 99\%$ of all pixels remain below a noise of $41\rm \e$. Based on the results for Pixel A-C, one may state that reducing the surface of the gate of the source follower transistor increases slightly the gain of the pixel. However, the median noise does also slightly increase, mostly because more pixels with very high individual noise are observed in the presence of a small gate: Once the width of the gate is reduced from $1.5 \mum$ to $0.5 \mum$, the ``99\%-noise'' raises from 41 to 63 electrons.
+Figure \ref{fig:Mi18Mi32Mi34Noisevergleich} compares the performances of the \mbox{Pixel A} ($0.18\rm ~\upmu m$, biggest source follower transistor gate) with the one of the established \mbox{Pixel R} \mbox{($0.35\rm ~\upmu m$ feature} size). \mbox{Pixel R} shows a small distribution with an median noise of $10.7 \rm \e$, and $\gtrsim 99\%$ of all pixels indicate a noise below $18 \rm \e$. The noise of \mbox{Pixel A} follows a broad distribution with a median of $19.8\rm \e$ and $\gtrsim 99\%$ of all pixels remain below a noise of $41\rm \e$. Based on the results for Pixel A-C, one may state that reducing the surface of the gate of the source follower transistor increases slightly the gain of the pixel. However, the median noise does also slightly increase, mostly because more pixels with very high individual noise are observed in the presence of a small gate: Once the width of the gate is reduced from $1.5 \mum$ to $0.5 \mum$, the ``99\%-noise'' raises from 41 to 63 electrons.
-This unintuitive finding can be understood by studying the detailed properties of noise pixels and comparing the results with the observations reported in \cite{RTS0.18,RTS0.182}. As shown in \mbox{figure \ref{fig:Mi32-1-f-noise-CDS-Signal}} and in \mbox{figure \ref{fig:Mi32-1-f-noise-Distribution}}, one observes that the dark signal of a representative noisy pixel varies between three well defined levels. This observation is compatible with the presence a Random Telegraph Signal in the source follower transistor. Random Telegraph Signal is most likely caused by individual defects in the silicon, which may absorb or emit an individual electron. The field of this electron adds to the field applied to the gate of the FET. Therefore, the current passing the FET is modulated to two well separated levels depending on the charge state of the defect. As we apply correlated double samples, which means subtracting the values of two consecutive samples, we observe three levels representing a stable state, the absorption, and the emission of an electron in the defect during the integration time.
+This unintuitive finding can be understood by studying the detailed properties of noise pixels and comparing the results with the observations reported in \cite{RTS0.18,RTS0.182}. As shown in \mbox{figure \ref{fig:Mi32-1-f-noise-CDS-Signal}} and in \mbox{figure \ref{fig:Mi32-1-f-noise-Distribution}}, one observes that the dark signal of a representative noisy pixel varies between three well defined levels. This observation is compatible with the presence a Random Telegraph Signal in the source follower transistor. Random Telegraph Signal is most likely caused by individual defects in the silicon, which may absorb or emit an individual electron. The field of this electron adds to the field applied to the gate of the FET. Therefore, the current passing the FET is modulated to two well separated levels depending on the charge state of the defect. As we apply correlated double sample, which means subtracting the values of two consecutive samples, we observe three levels representing a stable state, the absorption, and the emission of an electron in the defect during the integration time.
\begin{figure}
\begin{minipage}[t]{0.49 \textwidth}
\label{fig:StoNDiodeSize}
\end{minipage}
\end{figure}
-This RTS dominates the usual pixel noise, which determines the width of the individual peaks. Increasing the transistor gate seems to reduce the relative impact of the RTS and is therefore found to be beneficial. This holds also for the gate of the reset transistor, which was enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}.
+This RTS dominates the usual pixel noise, which determines the width of the individual peaks. Increasing the transistor gate surface seems to reduce the relative impact of the RTS and is therefore found to be beneficial. This holds also for the gate of the reset transistor, which was enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}.
Note that, while enlarging the transistor size reduces the RTS, cooling seems not to show a positive impact. This stands in contrast to our observations on RTS-noise originating from the pixel \mbox{diodes \cite{RTS}}.
\subsection{Impact of the transistor layout on the sensor performance}
%The next step is to move to more complex circuits which are necessary to achieve long pixel columns. \newline
\section{Summary and conclusion}
-Aiming for applications like the vertex detectors of CBM and ALICE, we are developing radiation tolerant large scale sensors with an integration time of $\lesssim 30\mus$. A $0.18\mum$ CMOS process providing a high-resistivity epitaxial layer, deep P- and N-wells and potentially a high tolerance to ionizing radiation is considered as a good suited technology for manufacturing those sensors. The process was explored by means of sensor prototypes hosting numerous different pixels, which were varied in different key parameters.
+Aiming for applications like the vertex detectors of CBM and ALICE, we are developing radiation tolerant large scale sensors with an integration time of $\lesssim 30\mus$. A $0.18\mum$ CMOS process providing a high-resistivity epitaxial layer, deep P- and N-wells and potentially a high tolerance to ionizing radiation is considered as a well suited technology for manufacturing those sensors. The process was explored by means of sensor prototypes hosting numerous pixels, which were varied in different key parameters.
-Guided by observations made previously in the field of optical imaging, we studied the relation between sensor capacity and the RTS - 1/f noise of the sensing diode. We find that the use of sensor gates with a length close to the minimum feature size introduces significant RTS-noise into some of the pixels. As the moderate amount of noisy pixels determines the threshold settings on future particle sensor, the advantages of the small gates in terms of reduced capacity and therefore the improved gain cannot be exploited. Concerning the optimal width of the sensing diode, we find that the increase of noise and of the CCE, which are caused by an increasing diode, do mostly cancel each other out and a very good S/N is reached with diode surfaces scaling from $2 \mum^2$ to $11 \mum^2$. The use of bigger diodes appears slightly preferable.
+Guided by observations made previously in the field of optical imaging, we studied the relation between sensor capacitance and the RTS - 1/f noise. We find that the use of sensor gates with a length close to the minimum feature size introduces significant RTS-noise into some of the pixels. As the moderate amount of noisy pixels determines the threshold settings on future particle sensor, the advantages of the small gates in terms of reduced capacitance and therefore the improved gain cannot be exploited. Concerning the optimal width of the sensing diode, we find that the increase of noise and of the CCE, which are caused by an increasing diode, do mostly cancel each other out and a very good S/N is reached with diode surfaces scaling from $2 \mum^2$ to $11 \mum^2$. The use of bigger diodes appears slightly preferable.
Concerning the radiation tolerance, we observe that the devices tolerate a dose of $3\Mrad$ without significant losses in performance while for a dose of $10\Mrad$ a tolerable drop of the gain of the pixels was observed. The origin of this finding is currently under investigation. In any case, the S/N of the device remains satisfactory (above 17 for 99\% of all pixels for the pixel type discussed in this work), which is considered as sufficient for a reliable sensor operation.
\acknowledgments
-This work has been supported by the BMBF (06FY9099I, 06FY7113I and 05P12RFFC7), HIC for FAIR and GSI.
-
+This work has been supported by BMBF (05P12RFFC7), HIC for FAIR and GSI.
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