MASTER_CLK_IN : in std_logic; -- recovered RX clock in (only master ports in quad)
MASTER_CLK_OUT : out std_logic; -- recovered RX clock out (slave port in quad)
QUAD_RST_IN : in std_logic; -- HANDLE WITH CARE
- GLOBAL_RESET_OUT : out std_logic; -- only available on MI with slave port
- SLAVE_ACTIVE_OUT : out std_logic; -- for delaying MPs in hub
- SLAVE_ACTIVE_IN : in std_logic; -- set to '1' on normal endpoints
- TX_PLL_LOL_IN : in std_logic; -- and'ed TX PLL LOL to sync startup
+ LINK_TX_NULL_IN : in std_logic; -- K_NULL reset handling
+ LINK_RX_NULL_OUT : out std_logic; -- K_NULL reset handling
TX_PLL_LOL_OUT : out std_logic; -- status signal of TX PLL
- TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available
+ TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available on port MASTER_CLK_OUT
TX_PCS_RST_IN : in std_logic; -- TX PCS reset signal
SYNC_TX_PLL_IN : in std_logic; -- bit0 alignment for TX serializer
LINK_TX_READY_IN : in std_logic; -- from TX reset generator
);
end entity;
-architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_125M_RS is
+architecture med_ecp3_sfp_sync_all_125M_RS_arch of med_ecp3_sfp_sync_all_RS is
-- Placer Directives
attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of med_ecp3_sfp_sync_all_RS_arch : architecture is "media_interface_group";
+ attribute HGROUP of med_ecp3_sfp_sync_all_125M_RS_arch : architecture is "media_interface_group";
attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_sync_all_RS_arch : architecture is "off";
+ attribute syn_sharing of med_ecp3_sfp_sync_all_125M_RS_arch : architecture is "off";
attribute syn_hier : string;
- attribute syn_hier of med_ecp3_sfp_sync_all_RS_arch : architecture is "hard";
+ attribute syn_hier of med_ecp3_sfp_sync_all_125M_RS_arch : architecture is "hard";
signal clk_rx_full : std_logic_vector(3 downto 0);
signal clk_rx_half : std_logic_vector(3 downto 0);
signal wap_requested_i : std_logic_vector(15 downto 0);
signal wap_req_i : std_logic_vector(3 downto 0);
signal wap_req_all : std_logic;
--- signal wap_req_all_q : std_logic;
signal wap_req_all_q : std_logic_vector(2 downto 0);
signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0);
type u8_arr is array (0 to 3) of unsigned(7 downto 0);
signal cv_cnt, cv_cnt_sys : u8_arr;
- signal powerup_ch : std_logic_vector(3 downto 0);
signal tx_ref_clk_i : std_logic;
- signal tx_rst_i : std_logic_vector(3 downto 0);
+ signal powerup_ch : std_logic_vector(3 downto 0);
+ signal link_rx_ready_i : std_logic_vector(3 downto 0);
+ signal link_rx_null_i : std_logic_vector(3 downto 0);
+ signal link_tx_null_i : std_logic_vector(3 downto 0);
+ signal word_sync_i : std_logic_vector(3 downto 0);
signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0);
signal rx_rst_i : std_logic_vector(3 downto 0);
signal rx_dlm_i : std_logic_vector(3 downto 0);
-
- signal global_reset_i : std_logic_vector(3 downto 0);
+ signal tx_rst_i : std_logic_vector(3 downto 0);
signal pll_lol_i : std_logic;
-
- signal link_rx_ready_i : std_logic_vector(3 downto 0);
- signal tx_clk_avail_sel : std_logic;
- signal word_sync_i : std_logic_vector(3 downto 0);
- signal word_sync_sel : std_logic;
-
- signal link_active_i : std_logic_vector(3 downto 0);
-
signal quad_mode : integer range 0 to 100;
begin
-------------------------------------------------
-- SFPs are disabled on unused SerDes channels
-------------------------------------------------
--- BUG: slave ports need also disable with link_tx_ready(i)
- SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) or (not SLAVE_ACTIVE_IN) --or RESET
- when IS_MODE(3) = c_IS_MASTER else
- not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE else
- '1' when IS_MODE(3) = c_IS_UNUSED else
- '0';
- SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) or (not SLAVE_ACTIVE_IN) --or RESET
- when IS_MODE(2) = c_IS_MASTER else
- not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE else
- '1' when IS_MODE(2) = c_IS_UNUSED else
- '0';
- SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) or (not SLAVE_ACTIVE_IN) --or RESET
- when IS_MODE(1) = c_IS_MASTER else
- not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE else
- '1' when IS_MODE(1) = c_IS_UNUSED else
- '0';
- SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) or (not SLAVE_ACTIVE_IN) --or RESET
- when IS_MODE(0) = c_IS_MASTER else
- not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE else
- '1' when IS_MODE(0) = c_IS_UNUSED else
- '0';
-
--------------------------------------------------
+ SD_TXDIS_OUT(3) <= '1' when (IS_MODE(3) = c_IS_UNUSED) else '0';
+ SD_TXDIS_OUT(2) <= '1' when (IS_MODE(2) = c_IS_UNUSED) else '0';
+ SD_TXDIS_OUT(1) <= '1' when (IS_MODE(1) = c_IS_UNUSED) else '0';
+ SD_TXDIS_OUT(0) <= '1' when (IS_MODE(0) = c_IS_UNUSED) else '0';
+
+-------------------------------------------------
-- TX ref clock
-- output only if a slave port is available in QUAD
--------------------------------------------------
+-------------------------------------------------
MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
'0';
--------------------------------------------------
--- global reset
--- output only if a slave port is available in QUAD
--------------------------------------------------
- GLOBAL_RESET_OUT <= global_reset_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
- global_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
- global_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
- global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+-------------------------------------------------
+-- K_NULL reset handling
+-------------------------------------------------
+ LINK_RX_NULL_OUT <= link_rx_null_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
+ link_rx_null_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
+ link_rx_null_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
+ link_rx_null_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
'0';
+ link_tx_null_i(3) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(3)) when (IS_MODE(3) = c_IS_MASTER) else '0';
+ link_tx_null_i(2) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(2)) when (IS_MODE(2) = c_IS_MASTER) else '0';
+ link_tx_null_i(1) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(1)) when (IS_MODE(1) = c_IS_MASTER) else '0';
+ link_tx_null_i(0) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(0)) when (IS_MODE(0) = c_IS_MASTER) else '0';
+
-------------------------------------------------
-- stable RX recovered clock available
-------------------------------------------------
- tx_clk_avail_sel <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
+ TX_CLK_AVAIL_OUT <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
link_rx_ready_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
link_rx_ready_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
'1';
-
- TX_CLK_AVAIL_OUT <= tx_clk_avail_sel;
-
--------------------------------------------------
---
--------------------------------------------------
- SLAVE_ACTIVE_OUT <= link_active_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
- link_active_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
- link_active_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
- link_active_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
- '0';
-------------------------------------------------
-- byte/word alignment
-------------------------------------------------
- word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
+ WORD_SYNC_OUT <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
word_sync_i(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else
'1';
- WORD_SYNC_OUT <= word_sync_sel;
-
-- if a SP is in the quad, we use the received WORD_SYNC.
-- in a MP only configuration, the TX WORD_SYNC is used as reference.
tx_sync_qd_c => SYNC_TX_PLL_IN
);
+ -- workaround for clock domain problem
clk_tx_full(0) <= MASTER_CLK_IN;
clk_tx_full(1) <= MASTER_CLK_IN;
clk_tx_full(2) <= MASTER_CLK_IN;
RX_LOS_IN => rx_los_low(i),
RX_CV_IN => rx_error(i),
RX_LSM_IN => lsm_status(i),
- TX_PLL_LOL_IN => TX_PLL_LOL_IN,
WA_POSITION_IN => wa_position_i(i*4+3 downto i*4),
WAP_REQUESTED_IN => wap_requested_i(i*4+3 downto i*4),
WAP_REQ_OUT => wap_req_i(i),
-- ports for synchronous operation
WORD_SYNC_IN => WORD_SYNC_IN,
WORD_SYNC_OUT => word_sync_i(i),
- GLOBAL_RESET_OUT => global_reset_i(i),
LINK_TX_READY_IN => LINK_TX_READY_IN,
LINK_RX_READY_OUT => link_rx_ready_i(i),
- LINK_ACTIVE_OUT => link_active_i(i),
+ LINK_RX_NULL_OUT => link_rx_null_i(i),
+ LINK_TX_NULL_IN => link_tx_null_i(i),
-- komma operation
TX_DLM_IN => TX_DLM_IN,
TX_DLM_WORD_IN => TX_DLM_WORD_IN,
rx_serdes_rst(i) <= '1'; -- keep in reset
rx_pcs_rst(i) <= '1'; -- keep in reset
wap_req_i(i) <= '0';
+ rx_dlm_i(i) <= '0';
MEDIA_MED2INT(i).dataready <= '0';
MEDIA_MED2INT(i).tx_read <= '1';
MEDIA_MED2INT(i).stat_op <= x"0007";
end generate;
+ RX_DLM_OUT <= rx_dlm_i;
+
wap_req_all <= wap_req_i(0) or wap_req_i(1) or wap_req_i(2) or wap_req_i(3);
-- SIGNAL_SYNC fails. TAKE CARE!
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