maxtot_timer <= maxtot_timer - 1;
else
edge_rising_valid <= '0';
- if edge_rising_valid = '1' then
- count_edges3 <= count_edges3 + 1;
- end if;
+ -- if edge_rising_valid = '1' then
+ -- count_edges3 <= count_edges3 + 1;
+ -- end if;
end if;
STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_edges1) when rising_edge(CLK_SYS);
STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_edges2) when rising_edge(CLK_SYS);
STATUS_OUT(71 downto 64) <= "00" & hit_buffer_level when rising_edge(CLK_SYS);
-STATUS_OUT(95 downto 72) <= x"00" & std_logic_vector(count_edges3(15 downto 0)) when rising_edge(CLK_SYS);
+-- STATUS_OUT(95 downto 72) <= x"00" & std_logic_vector(count_edges3(15 downto 0)) when rising_edge(CLK_SYS);
STATUS_OUT(127 downto 96) <= x"0000" & std_logic_vector(count_edges4(15 downto 0)) when rising_edge(CLK_SYS);
is_calib_sys <= '0';
timer <= TRIGGER_WINDOW;
elsif READOUT_RX.valid_notiming_trg = '1' then
- if READOUT_RX.trg_type = x"d" or READOUT_RX.trg_type = x"a" then
+ if READOUT_RX.trg_type = x"a" then
state_rdo <= CALIB;
is_calib_sys <= '1';
else
BUS_TX.data <= hitbuffer_status(addr)(31 downto 0);
elsif BUS_RX.addr(15 downto 5) = x"01" & "001" then
BUS_TX.data <= hitbuffer_status(addr)(63 downto 32);
- elsif BUS_RX.addr(15 downto 5) = x"01" & "010" then
- BUS_TX.data <= hitbuffer_status(addr)(95 downto 64);
+ -- elsif BUS_RX.addr(15 downto 5) = x"01" & "010" then
+ -- BUS_TX.data <= hitbuffer_status(addr)(95 downto 64);
elsif BUS_RX.addr(15 downto 5) = x"01" & "011" then
BUS_TX.data <= hitbuffer_status(addr)(127 downto 96);
else