Add adapted version of PWM for external threshold FPGA

diff --git a/code/pwm_machxo.vhd b/code/pwm_machxo.vhd
new file mode 100644 (file)
index 0000000..0298b89
--- /dev/null
+++ b/code/pwm_machxo.vhd
@@ -0,0 +1,82 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+
+entity pwm_generator is
+  generic(
+    CHANNELS : integer := 32
+    );
+  port(
+    CLK        : in std_logic;
+    
+    DATA_IN    : in  std_logic_vector(15 downto 0) := (others => '0');
+    DATA_OUT   : out std_logic_vector(15 downto 0);
+    WRITE_IN   : in  std_logic := '0';
+    COMP_IN    : in  signed(15 downto 0);
+    ADDR_IN    : in  std_logic_vector(4 downto 0) := (others => '0');
+    
+    
+    PWM        : out std_logic_vector(CHANNELS-1 downto 0)
+    
+    );
+end entity;
+
+
+
+architecture pwm_arch of pwm_generator is
+
+type ram_t is array(0 to CHANNELS-1) of unsigned(15 downto 0);
+signal set : ram_t := (others => x"87C1");
+signal set_tmp : ram_t;
+
+type cnt_t is array(0 to CHANNELS-1) of unsigned(16 downto 0);
+signal cnt : cnt_t := (others => (others => '0'));
+
+signal last_flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+signal flag      : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+signal pwm_i     : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+
+signal i         : integer range 0 to CHANNELS-1 := 0;
+signal clock_enable : std_logic_vector(15 downto 0) := x"0001";
+begin
+
+PROC_MEM : process begin
+  wait until rising_edge(CLK);
+  if WRITE_IN = '1' then
+    set(to_integer(unsigned(ADDR_IN))) <= unsigned(DATA_IN);
+  end if;
+  DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN))));
+end process;
+
+
+GEN_REAL_VALUES : process begin
+  wait until rising_edge(CLK);
+  set_tmp(i) <= unsigned(signed(set(i)) + COMP_IN);
+  i <= i + 1;
+end process;
+
+process begin
+  wait until rising_edge(CLK);
+  clock_enable <= clock_enable(14 downto 0) & clock_enable(15);
+end process;
+
+gen_channels : for i in 0 to CHANNELS-1 generate
+  flag(i)      <= cnt(i)(16);
+  
+  process begin
+    wait until rising_edge(CLK);
+    if clock_enable(i) = '1' then
+      last_flag(i) <= flag(i);
+      pwm_i(i)     <= (last_flag(i) xor flag(i));
+      cnt(i)       <= cnt(i) + resize(set_tmp(i),17);
+    end if;
+  end process;  
+end generate;
+
+
+
+PWM(CHANNELS-1 downto 0 ) <= pwm_i(CHANNELS-1 downto 0);
+
+end architecture;

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index d3897b3356196412660d845f2c6c7bd3b2d52bd9..5c90a7caba2ee2f23a86c0f07278f96888c477f1 100644 (file)
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -10,7 +10,7 @@ add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesi
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
 add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
-add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd"
+add_file -vhdl -lib work "../code/pwm_machxo.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index 33a5c596934a569f7a81b2e9a98e96ae21809cd0..4bac2993f3cdb1480842eb235246b37d36bde8b5 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -10,11 +10,10 @@ use work.trb_net_std.all;
 \r
 entity thresholds is\r
   port(\r
-    CLK    : in  std_logic;\r
-  \r
+    ID     : in  std_logic;\r
     OUTPUT : out std_logic_vector(15 downto 0);\r
-         TX_IN  : in  std_logic;\r
-         RX_OUT : out std_logic\r
+    TX_IN  : in  std_logic;\r
+    RX_OUT : out std_logic\r
 --     MISO_OUT : out std_logic;\r
 --     MOSI_IN  : in  std_logic;\r
 --     SCLK_IN  : in  std_logic;\r
@@ -59,6 +58,8 @@ architecture arch of thresholds is
   signal flash_busy    : std_logic;\r
   signal flash_err     : std_logic;\r
 \r
+  signal compensate_i  : signed(15 downto 0);\r
+  signal pwm_i         : std_logic_vector(15 downto 0);\r
 \r
   component OSCH\r
     generic (NOM_FREQ: string := "33.25");\r
@@ -135,6 +136,7 @@ PROC_REGS : process begin
   if bus_read = '1' then\r
     bus_ready <= '1';\r
     case uart_addr is\r
+      when x"10" => uart_tx_data <= std_logic_vector(compensate_i);\r
       when x"ee" => uart_tx_data <= sed_debug;\r
     end case;\r
   elsif bus_write = '1' then\r
@@ -145,6 +147,7 @@ PROC_REGS : process begin
     else\r
       case uart_addr is\r
 --         when x"10" => reg <= uart_rx_data;\r
+        when x"10" => compensate_i <= signed(uart_rx_data(15 downto 0);\r
         when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
       end case;\r
     end if;  \r
@@ -172,11 +175,14 @@ THE_PWM_GEN : entity work.pwm_generator
     CLK        => clk_i,\r
     DATA_IN    => pwm_data_i,\r
     DATA_OUT   => open,\r
-    COMP_IN    => (others => '0'),\r
+    COMP_IN    => compensate_i,\r
     WRITE_IN   => pwm_write_i,\r
     ADDR_IN    => pwm_addr_i,\r
-    PWM        => OUTPUT\r
+    PWM        => pwm_i\r
     );    \r
+\r
+--TODO connect to output according to ID\r
+OUTPUT <= pwm_i;\r
     \r
 ---------------------------------------------------------------------------\r
 -- Flash Controller\r
@@ -224,4 +230,4 @@ THE_FLASH : UFM_WB
 end architecture;\r
 \r
        \r
-       
\ No newline at end of file
+       \r