--- /dev/null
+library IEEE;
+-- use IEEE.STD_LOGIC_1164.ALL;
+-- use IEEE.STD_LOGIC_ARITH.ALL;
+ use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.all;
+
+-- -- use work.support.all;
+ library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-- use ieee.numeric_std.all;
+-- use ieee.std_logic_arith.all;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--library unisim;
+--use unisim.all;
+use work.all;
+-- -- Uncomment the following lines to use the declarations that are
+-- -- provided for instantiating Xilinx primitive components.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity dtu_interface is
+
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL1_ERROR_BUS : out std_logic;
+ LVL1_BUSY_BUS : out std_logic;
+ LVL1_TRIGGER : out std_logic;
+ LVL1_CODE : out std_logic_vector(3 downto 0);
+ LVL1_TAG : out std_logic_vector(7 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL2_ERROR_BUS : out std_logic;
+ LVL2_BUSY_BUS : out std_logic;
+ LVL2_TRIGGER : out std_logic;
+ LVL2_CODE : out std_logic_vector(3 downto 0);
+ LVL2_TAG : out std_logic_vector(7 downto 0);
+ LVL2_BUSY : in std_logic;
+ LVL2_TRB_ACK : in std_logic;
+ DTU_DEBUG_00 : out std_logic_vector( 31 downto 0)
+ );
+ end dtu_interface;
+architecture dtu_interface of dtu_interface is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component ram16x1D_virtex
+ port (
+ A : IN std_logic_VECTOR(3 downto 0);
+ CLK : IN std_logic;
+ D : IN std_logic_VECTOR(11 downto 0);
+ WE : IN std_logic;
+ DPRA : IN std_logic_VECTOR(3 downto 0);
+ DPO : OUT std_logic_VECTOR(11 downto 0);
+ SPO : OUT std_logic_VECTOR(11 downto 0));
+ end component;
+
+signal lvl1_code_i : std_logic_vector(3 downto 0);
+signal lvl1_tag_i : std_logic_vector(7 downto 0);
+signal lvl1_trigger_i : std_logic;
+signal lvl1_trigger_counter : std_logic_vector(1 downto 0);
+signal lvl1_triggers_counter : std_logic_vector(7 downto 0);
+signal lvl1_trb_trigg_enable : std_logic;
+signal lvl1_trigger_bus_pulse : std_logic;
+signal lvl1_trigger_data_bus_pulse : std_logic;
+signal lvl1_trigger_bus_pulse_synch : std_logic;
+signal lvl1_trigger_data_bus_pulse_synch : std_logic;
+
+signal lvl2_code_i : std_logic_vector(3 downto 0);
+signal lvl2_tag_i : std_logic_vector(7 downto 0);
+signal lvl2_trigger_i : std_logic;
+signal lvl2_trigger_counter : std_logic_vector(1 downto 0);
+signal lvl2_triggers_counter : std_logic_vector(7 downto 0);
+signal lvl2_trb_trigg_enable : std_logic;
+signal lvl2_trigger_bus_pulse : std_logic;
+signal lvl2_trigger_data_bus_pulse : std_logic;
+signal lvl2_trigger_bus_pulse_synch : std_logic;
+signal lvl2_trigger_data_bus_pulse_synch : std_logic;
+
+signal lvl2_fifo_address_in : std_logic_vector(3 downto 0):=x"0";
+signal lvl2_fifo_address_out : std_logic_vector(3 downto 0):=x"0";
+signal lvl2_fifo_full : std_logic;
+signal lvl2_fifo_not_empty : std_logic;
+signal lvl2_fifo_we : std_logic;
+signal lvl2_fifo_data_in : std_logic_vector(11 downto 0);
+signal lvl2_fifo_data_out : std_logic_vector(11 downto 0);
+signal lvl2_fifo_we_in : std_logic;
+signal fifo_counter: std_logic_vector(3 downto 0);
+
+type send_lvl2_trigger is (IDLE, SEND_TRIGGER, WAIT_FOR_ACK);
+signal current_state_send_lvl2_trigger, next_state_send_lvl2_trigger : send_lvl2_trigger;
+
+
+begin -- dtu_interface
+-------------------------------------------------------------------------------
+-- LVL1
+-------------------------------------------------------------------------------
+ LVL1_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGGER_BUS,
+ pulse => lvl1_trigger_bus_pulse);
+ LVL1_TRIGGER_DATA_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_DATA_TRIGGER_BUS,
+ pulse => lvl1_trigger_data_bus_pulse);
+
+ LVL1_SYNCH_TRIGGERS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_bus_pulse_synch <= '0';
+ lvl1_trigger_data_bus_pulse_synch <= '0';
+ else
+ lvl1_trigger_bus_pulse_synch <= lvl1_trigger_bus_pulse;
+ lvl1_trigger_data_bus_pulse_synch <= lvl1_trigger_data_bus_pulse;
+ end if;
+ end if;
+ end process LVL1_SYNCH_TRIGGERS;
+ LVL1_COUNTER_FOR_CODE_AND_TAG: process (CLK, RESET, lvl1_trigger_bus_pulse_synch, lvl1_trigger_data_bus_pulse_synch)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_counter <= "00";
+ elsif lvl1_trigger_bus_pulse_synch = '1' or lvl1_trigger_data_bus_pulse_synch = '1' then
+ lvl1_trigger_counter <= lvl1_trigger_counter + 1;
+ end if;
+ end if;
+ end process LVL1_COUNTER_FOR_CODE_AND_TAG;
+
+ LVL1_SAVE_CODE_AND_TAG: process (CLK, RESET,lvl1_trigger_bus_pulse_synch,lvl1_trigger_data_bus_pulse_synch,lvl1_trigger_counter)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_code_i <= x"0";
+ lvl1_tag_i <= x"00";
+ elsif (lvl1_trigger_bus_pulse_synch = '1') or (lvl1_trigger_data_bus_pulse_synch) = '1' then
+ case lvl1_trigger_counter is
+ when "00" => lvl1_code_i <= LVL1_DATA_BUS;
+ when "01" => lvl1_tag_i (3 downto 0) <= LVL1_DATA_BUS;
+ when "10" => lvl1_tag_i (7 downto 4) <= LVL1_DATA_BUS;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process LVL1_SAVE_CODE_AND_TAG;
+ LVL1_CODE <= lvl1_code_i;
+ LVL1_TAG <= lvl1_tag_i;
+ lvl1_trb_trigg_enable <= lvl1_trigger_counter(0) and lvl1_trigger_counter(1); --
+ --="11" last trigger
+ LVL1_TRB_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_trb_trigg_enable,
+ pulse => lvl1_trigger_i );
+
+ LVL1_TRIGGER <= lvl1_trigger_i;
+ LVL1_BUSY_BUS <= LVL1_BUSY;
+ LVL1_COUNT_TRIGGERS: process (CLK, RESET, lvl1_trigger_bus_pulse_synch)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_triggers_counter <= x"00";
+ elsif lvl1_trigger_bus_pulse_synch = '1' then
+ lvl1_triggers_counter <= lvl1_triggers_counter +1;
+ end if;
+ end if;
+ end process LVL1_COUNT_TRIGGERS;
+LVL1_CHECK_TAG: process (CLK, RESET, lvl1_trigger_i,lvl1_triggers_counter,lvl1_tag_i )
+begin
+ if RESET = '1' then
+ LVL1_ERROR_BUS <= '0';
+ if rising_edge(CLK) then
+ if lvl1_trigger_i = '1' then
+ if lvl1_triggers_counter /= lvl1_tag_i then
+ LVL1_ERROR_BUS <= '1';
+ end if;
+ end if;
+ end if;
+end if;
+end process LVL1_CHECK_TAG;
+
+
+-----------------------------------------------------------------------------
+-- LVL2
+-----------------------------------------------------------------------------
+
+ LVL2_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL2_TRIGGER_BUS,
+ pulse => lvl2_trigger_bus_pulse);
+ LVL2_TRIGGER_DATA_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL2_DATA_TRIGGER_BUS,
+ pulse => lvl2_trigger_data_bus_pulse);
+
+ LVL2_SYNCH_TRIGGERS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_trigger_bus_pulse_synch <= '0';
+ lvl2_trigger_data_bus_pulse_synch <= '0';
+ else
+ lvl2_trigger_bus_pulse_synch <= lvl2_trigger_bus_pulse;
+ lvl2_trigger_data_bus_pulse_synch <= lvl2_trigger_data_bus_pulse;
+ end if;
+ end if;
+ end process LVL2_SYNCH_TRIGGERS;
+ LVL2_COUNTER_FOR_CODE_AND_TAG: process (CLK, RESET,lvl2_trigger_bus_pulse_synch,lvl2_trigger_data_bus_pulse_synch)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_trigger_counter <= "00";
+ elsif lvl2_trigger_bus_pulse_synch = '1' or lvl2_trigger_data_bus_pulse_synch = '1' then
+ lvl2_trigger_counter <= lvl2_trigger_counter + 1;
+ end if;
+ end if;
+ end process LVL2_COUNTER_FOR_CODE_AND_TAG;
+
+ LVL2_SAVE_CODE_AND_TAG: process (CLK, RESET,lvl2_trigger_bus_pulse_synch,lvl2_trigger_data_bus_pulse_synch,lvl2_trigger_counter )
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_code_i <= x"0";
+ lvl2_tag_i <= x"00";
+ elsif lvl2_trigger_bus_pulse_synch = '1' or lvl2_trigger_data_bus_pulse_synch = '1' then
+ case lvl2_trigger_counter is
+ when "00" => lvl2_code_i <= LVL2_DATA_BUS;
+ when "01" => lvl2_tag_i (3 downto 0) <= LVL2_DATA_BUS;
+ when "10" => lvl2_tag_i (7 downto 4) <= LVL2_DATA_BUS;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end process LVL2_SAVE_CODE_AND_TAG;
+
+lvl2_fifo_data_in <= lvl2_code_i & lvl2_tag_i;
+LVL2_CODE <= lvl2_fifo_data_out(11 downto 8);
+LVL2_TAG <= lvl2_fifo_data_out(7 downto 0);
+lvl2_fifo_we_in <= lvl2_trigger_counter(0) and lvl2_trigger_counter(1);
+ LVL2_TRB_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_fifo_we_in,
+ pulse => lvl2_fifo_we );
+
+ ram16: ram16x1D_virtex
+ port map (
+ A => lvl2_fifo_address_in,
+ CLK => CLK,
+ D => lvl2_fifo_data_in,
+ WE => lvl2_fifo_we,
+ DPRA => lvl2_fifo_address_out,
+ DPO => lvl2_fifo_data_out,
+ SPO => open);
+ LVL2_FIFO_STATUS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_fifo_address_out <= x"0";
+ lvl2_fifo_address_in <= x"0";
+ fifo_counter <= x"0";
+ elsif lvl2_fifo_we = '1' and LVL2_TRB_ACK = '0' then
+ lvl2_fifo_address_in <= lvl2_fifo_address_in + 1;
+ lvl2_fifo_address_out <= lvl2_fifo_address_out;
+ fifo_counter <= fifo_counter + 1;
+ elsif lvl2_fifo_we = '0' and LVL2_TRB_ACK = '1' then
+ lvl2_fifo_address_in <= lvl2_fifo_address_in ;
+ lvl2_fifo_address_out <= lvl2_fifo_address_out + 1;
+ fifo_counter <= fifo_counter - 1;
+ elsif lvl2_fifo_we = '1' and LVL2_TRB_ACK = '1' then
+
+ lvl2_fifo_address_in <= lvl2_fifo_address_in + 1;
+ lvl2_fifo_address_out <= lvl2_fifo_address_out + 1;
+ fifo_counter <= fifo_counter;
+ else
+ lvl2_fifo_address_in <= lvl2_fifo_address_in;
+ lvl2_fifo_address_out <= lvl2_fifo_address_out;
+ fifo_counter <= fifo_counter;
+ end if;
+ end if;
+ end process LVL2_FIFO_STATUS;
+ lvl2_fifo_full <= '0' when fifo_counter < x"e" else '1';
+ lvl2_fifo_not_empty <= '1' when fifo_counter > x"0" else '0';
+-- LVL2_BUSY_BUS <= LVL2_BUSY or lvl2_fifo_full;
+ LVL2_BUSY_BUS <= lvl2_fifo_full;
+ SEND_LVL2_TRIGGER_FSM : process (CLK,RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state_send_lvl2_trigger <= IDLE;
+ else
+ current_state_send_lvl2_trigger <= next_state_send_lvl2_trigger;
+ end if;
+ end if;
+ end process SEND_LVL2_TRIGGER_FSM;
+
+ SEND_LVL2_TRIGGER_PROC: process (lvl2_fifo_not_empty,LVL2_TRB_ACK,CLK,LVL2_BUSY)
+ begin
+ case current_state_send_lvl2_trigger is
+ when IDLE =>
+ lvl2_trigger_i <= '0';
+ if lvl2_fifo_not_empty = '1' and LVL2_BUSY = '0' then
+ next_state_send_lvl2_trigger <= SEND_TRIGGER;
+ else
+ next_state_send_lvl2_trigger <= IDLE;
+ end if;
+ when SEND_TRIGGER =>
+ lvl2_trigger_i <= '1';
+ next_state_send_lvl2_trigger <= WAIT_FOR_ACK;
+ when WAIT_FOR_ACK =>
+ lvl2_trigger_i <= '0';
+ if LVL2_TRB_ACK ='1' then
+ next_state_send_lvl2_trigger <= IDLE;
+ else
+ next_state_send_lvl2_trigger <= WAIT_FOR_ACK;
+ end if;
+ when others =>
+ next_state_send_lvl2_trigger <= IDLE;
+ end case;
+ end process SEND_LVL2_TRIGGER_PROC;
+ LVL2_TRIGGER <= lvl2_trigger_i;
+end dtu_interface;
+
FPGA_REGISTER_29 : out std_logic_vector(31 downto 0);
FPGA_REGISTER_30 : out std_logic_vector(31 downto 0);
FPGA_REGISTER_31 : out std_logic_vector(31 downto 0);
- EXTERNAL_RESET : out std_logic
+ EXTERNAL_RESET : out std_logic;
+ LVL2_VALID : in std_logic
);
end etrax_interface;
architecture etrax_interface of etrax_interface is
signal etrax_data_pulse_2 : std_logic;
signal etrax_data_pulse_3: std_logic;
signal debug_reg_04 : std_logic_vector(15 downto 0);
+ signal etrax_is_ready_to_read_i : std_logic;
+ signal pulse_clock : std_logic;
+ signal lvl2_not_valid_pulse : std_logic;
+ signal counter_for_pulses : std_logic_vector(2 downto 0);
begin
ETRAX_TRIGG_PULSER : edge_to_pulse
ETRAX_READY_PULSE : edge_to_pulse
port map (
clock => CLK,
- en_clk => '1',
+ en_clk => DATA_VALID,--'1',
signal_in => ETRAX_DATA_BUS_C(17),
- pulse => ETRAX_IS_READY_TO_READ);
+ pulse => etrax_is_ready_to_read_i);
+ MAKE_PULSES: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_for_pulses <= "000";
+ -- pulse_clock <= '0';
+ else
+-- pulse_clock <= not pulse_clock;
+ counter_for_pulses <= counter_for_pulses + 1;
+ end if;
+ end if;
+ end process make_pulses;
+ LVL2_NOT_VALID_READY_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+-- signal_in => pulse_clock,
+ signal_in => counter_for_pulses(2),
+ pulse => lvl2_not_valid_pulse);
+-- ETRAX_READY_CLOCKED : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17))
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+-- ETRAX_RW_STATE_currentstate <= IDLE;
+-- else
+-- ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
+-- end if;
+-- end if;
+-- end process ETRAX_FPGA_COMUNICATION_CLOCK;
+
+ ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i or (DATA_VALID and lvl2_not_valid_pulse and LVL2_VALID);
RW_FINISHED_PULSER : edge_to_pulse
port map (
clock => CLK,
elsif DATA_VALID = '1' then
ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
-- ETRAX_DATA_BUS_B(17) <= CLK;
- ETRAX_DATA_BUS_B(16) <= '1';
+ ETRAX_DATA_BUS_B(16) <= '1' and not(LVL2_VALID);
else
- ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_07_i(15 downto 0);
+ ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_07_i(15 downto 0);
ETRAX_DATA_BUS_B(16) <= '0';
end if;
end if;
end process ETRAX_DATA_BUS_CHOOSE;
- ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0';
+ ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0';
TDC_JAM_SIGNALS : process (CLK, RESET, DATA_VALID, fpga_register_16_i(0))
begin
port (
CLK : in std_logic;
RESET : in std_logic;
- LVL1_BUSY : out std_logic;
- LVL2_BUSY : out std_logic;
+ LVL1_BUSY : out std_logic:='0';
+ LVL2_BUSY : out std_logic:='0';
TDC_LVL1_BUSY : in std_logic;
- TDC_LVL2_BUSY : in std_logic;
+ TDC_LVL2_BUSY : in std_logic:='0';
ETRAX_BUSY : in std_logic;
ETRAX_BUS_BUSY : in std_logic;
LVL1_TRIGG : in std_logic;
TRIGGER_CODE : in std_logic_vector(3 downto 0);
TDC_READOUT_COMPLETED : in std_logic;
TRIGGER_WITHOUT_HADES : in std_logic;
- BUSY_REGISTER_00 : out std_logic_vector(31 downto 0)
+ BUSY_REGISTER_00 : out std_logic_vector(31 downto 0);
+ BUSY_REGISTER_01 : out std_logic_vector(31 downto 0);
+ WRITE_LVL1_BUSY : out std_logic
);
end lvl1_and_lvl2_busy;
architecture lvl1_and_lvl2_busy of lvl1_and_lvl2_busy is
en_clk : in std_logic;
signal_in : in std_logic;
pulse : out std_logic);
+ end component;
+ component simpleupcounter_16bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
end component;
signal count_lvl1_lvl2_diff : std_logic_vector(15 downto 0);
signal lvl1_count_pulse : std_logic;
signal count_busy_lvl2 : std_logic;
signal write_busy_lvl1_pulse : std_logic;
signal tdc_lvl2_busy_pulse : std_logic;
+ signal lvl1_counter : std_logic_vector(15 downto 0);
+ signal lvl2_counter : std_logic_vector(15 downto 0);
begin
-------------------------------------------------------------------------------
-- LVL1 start pulse for count (up)
en_clk => '1',
signal_in => LVL2_TRIGG,
pulse => lvl2_count_pulse);
+-------------------------------------------------------------------------------
+-- LVL1 counter
+-------------------------------------------------------------------------------
+ LVL1_COUNT : simpleupcounter_16bit
+ port map (
+ QOUT => lvl1_counter,
+ UP => lvl1_count_pulse,
+ CLK => CLK,
+ CLR => RESET);
+-------------------------------------------------------------------------------
+-- LVL2 counter
+-------------------------------------------------------------------------------
+ LVL2_COUNT : simpleupcounter_16bit
+ port map (
+ QOUT => lvl2_counter,
+ UP => lvl2_count_pulse,
+ CLK => CLK,
+ CLR => RESET);
+
+ BUSY_REGISTER_01 <= lvl1_counter & lvl2_counter;
-----------------------------------------------------------------------------
--LVL1 UP PULSE
-----------------------------------------------------------------------------
end if;
end if;
end process BUSY_LVL1;
+ WRITE_LVL1_BUSY <= write_busy_lvl1;
LVL1_BUSY <= write_busy_lvl1 or TDC_LVL1_BUSY;
----------------------------------------------------------------------------
-- LEVEL 2 BUSY LOGIC
----------------------------------------------------------------------------
count_busy_lvl2 <= write_busy_lvl1 when count_lvl1_lvl2_diff = x"01" else '0';
- LVL2_BUSY <= TDC_LVL2_BUSY or count_busy_lvl2 or ETRAX_BUSY or ETRAX_BUS_BUSY;
+ LVL2_BUSY <= TDC_LVL2_BUSY or count_busy_lvl2;-- or ETRAX_BUSY or ETRAX_BUS_BUSY;
-- TDC_LVL2_BUSY - write busy
-- ETRAX_BUSY - etrax is not ready
-- ETRAX_BUS_BUSY - comunication between etrax and FPGA
CLR : in std_logic);
end simpleupcounter_16bit;
-architecture Behavioral of simpleupcounter_16bit is
+architecture simpleupcounter_16bit of simpleupcounter_16bit is
signal counter: std_logic_vector (15 downto 0);
QOUT <= counter;
-end Behavioral;
+end simpleupcounter_16bit;
TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
BUNCH_RESET : out std_logic;
EVENT_RESET : out std_logic;
- READ_ADRESS_END_UP : in std_logic
+ READ_ADRESS_END_UP : in std_logic;
+ MY_LVL1_COUNTER : in std_logic_vector(7 downto 0)
);
end tdc_interface;
architecture tdc_interface of tdc_interface is
signal word_count_up : std_logic:='0';
signal word_count_up_clk : std_logic := '0';
signal word_count_up_pulse : std_logic:='0';
- signal how_many_words_in_fifo : std_logic_vector(15 downto 0):=(others => '0');
+ signal how_many_words_in_fifo : std_logic_vector(9 downto 0):=(others => '0');
signal how_many_words_in_ram : std_logic_vector(9 downto 0):=(others => '0');
signal tdc_data_valid_i : std_logic:='0';
signal lvl2_trigger_pulse : std_logic;
signal word_count_down_clk: std_logic;
signal word_count_down_pulse: std_logic;
signal locked_i : std_logic;
- signal word_ram_counter_up : std_logic_vector(15 downto 0);
- signal word_ram_counter_down : std_logic_vector(15 downto 0);
+ signal word_ram_counter_up : std_logic_vector(9 downto 0);
+ signal word_ram_counter_down : std_logic_vector(9 downto 0);
+ signal lvl1_tag_minus_one : std_logic_vector(7 downto 0);
+ signal saved_beg_address : std_logic_vector( 14 downto 0) ;
+ signal lvl2_trigger_pulse_1delay : std_logic;
+ signal lvl2_trigger_pulse_2delay : std_logic;
+ signal lvl2_trigger_pulse_3delay : std_logic;
+ signal lvl2_trigger_pulse_4delay : std_logic;
+ signal lvl2_trigger_pulse_delay : std_logic;
begin
TDC_REGISTER : process (CLK, RESET)
begin
TDC_REGISTER_00(1) <= B_TDC_ERROR;
TDC_REGISTER_00(2) <= C_TDC_ERROR;
TDC_REGISTER_00(3) <= D_TDC_ERROR;
- TDC_REGISTER_00(19 downto 4) <= how_many_words_in_fifo;
+ TDC_REGISTER_00(19 downto 4) <= "000000"&how_many_words_in_fifo;
TDC_REGISTER_00(20) <= clkfx_bufg_i;
TDC_REGISTER_00(30 downto 21) <= (others => '0');
TDC_REGISTER_00(31) <= locked_i;
counter_l_i <= (others => '0');
counter_m_i <= (others => '0');
elsif START_TDC_READOUT = '1' then
- counter_a_i <= COUNTER_a;
- counter_b_i <= COUNTER_b;
+ counter_a_i <= x"00000" & "00" & how_many_words_in_fifo;--COUNTER_a;
+ counter_b_i <= x"000000" & MY_LVL1_COUNTER;--COUNTER_b;
counter_c_i <= COUNTER_c;
counter_d_i <= COUNTER_d;
counter_e_i <= COUNTER_e;
end if;
end if;
end process COUNT_WORDS_IN_EVENT;
- first_header <= x"0" & LVL1_CODE & LVL1_TAG & words_in_event;
+ lvl1_tag_minus_one <= LVL1_TAG - 1;
+ first_header <= x"a" & LVL1_CODE & LVL1_TAG & words_in_event;
+
second_header <= x"02" & x"00" & x"00" & HOW_MANY_ADD_DATA;
write_address <= write_address_tdc_data when add_data_pulse = '0' else saved_address;
-----------------------------------------------------------------------------
if rising_edge(CLK) then
if RESET = '1' then
how_many_words_in_event <= (others => '0');
- elsif lvl2_trigger_pulse = '1' then
+ elsif lvl2_trigger_pulse_delay = '1' then
how_many_words_in_event <= x"1" & doutb_i(15 downto 0);
- elsif lvl2_trigger_pulse = '0' and how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1'then
+ elsif lvl2_trigger_pulse_delay = '0' and how_many_words_in_event > x"0ffff" and (ETRAX_IS_READY_TO_READ = '1' or READ_ADRESS_END_UP='1')then
--this should be without and ETRAX_IS_READY_TO_READ - this is simple
--version of readout - in next whole event has to be written without
--waiting for etrax - ifthere is no LVL2 busy from etrax
tdc_data_valid_i <= '0';
read_data_address_up <= '0';
elsif how_many_words_in_event > x"10000" then
- tdc_data_valid_i <= lvl2_valid_saved;
+ tdc_data_valid_i <= '1';--lvl2_valid_saved;
read_data_address_up <= '1';
elsif how_many_words_in_event = x"10000" then
tdc_data_valid_i <= '0';--lvl2_valid_saved;
end process MAKE_LVL2_PULSE;
SYNCH_DATA_VALID: process (CLK, RESET)
begin
- if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
+ if falling_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
if RESET = '1' then
TDC_DATA_VALID <= '0';
else
end if;
end process SYNCH_DATA_VALID;
TDC_LVL2_BUSY <= tdc_data_valid_i;
+ DELAY_LVL2_TRIGGER: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_trigger_pulse_delay <= '0';
+
+ lvl2_trigger_pulse_1delay <= '0';
+ lvl2_trigger_pulse_2delay <= '0';
+ lvl2_trigger_pulse_3delay <= '0';
+ lvl2_trigger_pulse_4delay <= '0';
+
+ else
+ lvl2_trigger_pulse_1delay <= lvl2_trigger_pulse;
+ lvl2_trigger_pulse_2delay <= lvl2_trigger_pulse_1delay;
+ lvl2_trigger_pulse_3delay <= lvl2_trigger_pulse_2delay;
+ lvl2_trigger_pulse_4delay <= lvl2_trigger_pulse_3delay;
+ lvl2_trigger_pulse_delay <= lvl2_trigger_pulse_4delay;
+
+-- lvl2_trigger_pulse_delay <= lvl2_trigger_pulse;
+ end if;
+ end if;
+ end process DELAY_LVL2_TRIGGER;
READ_ADDRESS_CHANGE : process (CLK, RESET, read_data_address_up)
begin
if rising_edge(CLK) then
if RESET = '1' then
read_address <= (others => '0');
+-- saved_beg_address <= (others => '0');
+-- elsif lvl2_trigger_pulse_delay = '1' then
+-- -- saved_beg_address <= saved_beg_address + doutb_i(14 downto 0);
+-- read_address <= saved_beg_address + doutb_i(14 downto 0);
elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then
read_address <= read_address + 1;
else
read_address <= read_address;
+ saved_beg_address <= saved_beg_address;
end if;
end if;
end process READ_ADDRESS_CHANGE;
+-- SAVE_BEG_ADDRESS: process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then -- rising clock edge
+-- if RESET = '1' then
+-- saved_beg_address <= (others => '0');
+-- elsif lvl2_trigger_pulse = '1' then
+-- saved_beg_address <= saved_beg_address + doutb_i(14 downto 0);
+-- else
+-- saved_beg_address <= saved_beg_address;
+-- end if;
+-- end if;
+-- end process SAVE_BEG_ADDRESS;
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Mixed LVL1 and LVL2
if rising_edge(CLK) then
if RESET = '1' then
word_ram_counter_down <= (others => '0');
- elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then
+-- elsif (read_data_address_up = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1' then
+ elsif ((tdc_data_valid_i = '1' and ETRAX_IS_READY_TO_READ = '1') or READ_ADRESS_END_UP='1') and how_many_words_in_fifo /= "0000000000000000" then
word_ram_counter_down <= word_ram_counter_down + 1;
end if;
end if;
end process WORD_SEND_FROM_MEMORY;
- how_many_words_in_fifo <= word_ram_counter_up - word_ram_counter_down;
- TDC_LVL1_BUSY <= '1' when how_many_words_in_fifo > "0011111111111111" else '0';
+ REGISTER_DIFFERENCE: process (CLK, RESET)
+ begin
+ if CLK'event and CLK = '1' then -- rising clock edge
+ if RESET = '1' then -- asynchronous reset (active low)
+ how_many_words_in_fifo <= (others => '0');
+ else
+ how_many_words_in_fifo <= word_ram_counter_up - word_ram_counter_down;
+ end if;
+ end if;
+ end process REGISTER_DIFFERENCE;
+
+ TDC_LVL1_BUSY <= '1' when how_many_words_in_fifo > "011111111" else '0';
--set
--to
--max
-- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
-----------------------------------------------------------------------------
end tdc_interface;
+
+
+-- etrax czasem widzi za wczesnie header zamiast headera widzi dana z poprzedniego eventu ¿
+-- moze READ_ADRESS_END_UP gdzeis jest zgubione ?
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
+ library IEEE;
+-- use IEEE.STD_LOGIC_1164.ALL;
+-- use IEEE.STD_LOGIC_ARITH.ALL;
+ use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.all;
--- use work.support.all;
- library UNISIM;
- use UNISIM.VCOMPONENTS.all;
+-- -- use work.support.all;
+ library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-- use ieee.numeric_std.all;
+-- use ieee.std_logic_arith.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--library unisim;
+--use unisim.all;
+use work.all;
-- -- Uncomment the following lines to use the declarations that are
-- -- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- ADDON_TO_TRB_CLKINN : std_logic;
-- ADDON_TO_TRB_CLKINP : std_logic;
-- ADO_LV : std_logic_vector(61 downto 0);lvds signal
- ADO_TTL : out std_logic_vector(46 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
-------------------------------------------------------------------------------
--JTAG
-------------------------------------------------------------------------------
TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
BUNCH_RESET : out std_logic;
EVENT_RESET : out std_logic;
- READ_ADRESS_END_UP : in std_logic);
+ READ_ADRESS_END_UP : in std_logic;
+ MY_LVL1_COUNTER : in std_logic_vector(7 downto 0)
+ );
end component;
component lvl1_and_lvl2_busy
port (
TRIGGER_CODE : in std_logic_vector(3 downto 0);
TDC_READOUT_COMPLETED : in std_logic;
TRIGGER_WITHOUT_HADES : in std_logic;
- BUSY_REGISTER_00 : out std_logic_vector(31 downto 0)
+ BUSY_REGISTER_00 : out std_logic_vector(31 downto 0);
+ BUSY_REGISTER_01 : out std_logic_vector(31 downto 0);
+ WRITE_LVL1_BUSY : out std_logic
+
);
end component;
component trigger_logic
TDC_CODE : out std_logic_vector(3 downto 0);
TDC_TAG : out std_logic_vector(7 downto 0);
LVL2_TRIGGER : in std_logic_vector(1 downto 0);
+ LVL2_TRIGGER_CODE : in std_logic_vector(3 downto 0);
LVL1_TRIGGER : in std_logic;
LVL1_TDC_TRIGG : out std_logic;
LVL2_TDC_TRIGG : out std_logic_vector(1 downto 0);
TRB_ACK_LVL1 : out std_logic;
TRB_ACK_LVL2 : out std_logic;
TRIGGER_TO_TDC : out std_logic;
- TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0)
+ TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0);
+ LVL2_BUSY_ALL : in std_logic
);
end component;
component etrax_interface
FPGA_REGISTER_29 : out std_logic_vector(31 downto 0);
FPGA_REGISTER_30 : out std_logic_vector(31 downto 0);
FPGA_REGISTER_31 : out std_logic_vector(31 downto 0);
- EXTERNAL_RESET : out std_logic);
+ EXTERNAL_RESET : out std_logic;
+ LVL2_VALID : in std_logic);
end component;
- component tlk_interface
- port (
- VIRT_CLK : in std_logic;
- ENABLE : out std_logic;
- LCKREFN : out std_logic;
- LOOPEN : out std_logic;
- PRBSEN : out std_logic;
- RX_CLK : in std_logic;
- RX_DV : in std_logic;
- RX_ER : in std_logic;
- TLK_CLK : in std_logic;
- TLK_RXD : in std_logic_vector (15 downto 0);
- TLK_TXD : out std_logic_vector (15 downto 0);
- TX_EN : out std_logic;
- TX_ER : out std_logic;
- RESET_VIRT : in std_logic;
- TLK_REGISTER_00 : out std_logic_vector(31 downto 0);
- TLK_REGISTER_01 : out std_logic_vector(31 downto 0));
+-- component tlk_interface
+-- port (
+-- VIRT_CLK : in std_logic;
+-- ENABLE : out std_logic;
+-- LCKREFN : out std_logic;
+-- LOOPEN : out std_logic;
+-- PRBSEN : out std_logic;
+-- RX_CLK : in std_logic;
+-- RX_DV : in std_logic;
+-- RX_ER : in std_logic;
+-- TLK_CLK : in std_logic;
+-- TLK_RXD : in std_logic_vector (15 downto 0);
+-- TLK_TXD : out std_logic_vector (15 downto 0);
+-- TX_EN : out std_logic;
+-- TX_ER : out std_logic;
+-- RESET_VIRT : in std_logic;
+-- TLK_REGISTER_00 : out std_logic_vector(31 downto 0);
+-- TLK_REGISTER_01 : out std_logic_vector(31 downto 0));
+-- end component;
+-- component dsp_interface
+-- port (
+-- -- signal to/from dsp
+-- HBR_OUT : out std_logic; -- Host Bus Request to DSP
+-- HBG_IN : in std_logic; -- Host Bus Grant from DSP
+-- RD_OUT : out std_logic; -- read/write enable of DSP
+-- DSP_DATA_OUT : out std_logic_vector(31 downto 0);
+-- DSP_DATA_IN : in std_logic_vector(31 downto 0);
+-- ADDRESS_DSP : out std_logic_vector(31 downto 0);
+-- WRL : out std_logic; --when dsp slave is output
+-- WRH : out std_logic; --when dsp slave is output
+-- BM_IN : in std_logic; --Bus Master. For debug
+-- DSP_RESET : out std_logic;
+-- BRST : inout std_logic;
+-- ACK : in std_logic;
+-- --internal data and address bus
+-- CLK : in std_logic;
+-- RESET : in std_logic;
+-- R_W_ENABLE : in std_logic;
+-- TRIGGER : in std_logic;
+-- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0
+-- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0
+-- INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+-- VALID_DATA_SENT : out std_logic;
+-- ACKNOWLEDGE : in std_logic;
+-- DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+-- );
+-- end component;
+ component DTU
+ port (
+ T_CLK_40 : in std_logic;
+ T_RES : in std_logic;
+ T_TRIGBUS_TSTR_LVL1 : in std_logic;
+ T_TRIGBUS_DSTR_LVL1 : in std_logic;
+ T_TRIGBUS_DIN_LVL1 : in std_logic_vector(3 downto 0);
+ T_TRIGBUS_BUSY_LVL1 : out std_logic;
+ T_TRIGBUS_ERR_LVL1 : out std_logic;
+ T_TRIGBUS_TSTR_LVL2 : in std_logic;
+ T_TRIGBUS_DSTR_LVL2 : in std_logic;
+ T_TRIGBUS_DIN_LVL2 : in std_logic_vector(3 downto 0);
+ T_TRIGBUS_BUSY_LVL2 : out std_logic;
+ T_TRIGBUS_ERR_LVL2 : out std_logic;
+ TRIGGER_CODE_LVL1 : out unsigned(3 downto 0);
+ TRIGGER_TAG_LVL1 : out unsigned(7 downto 0);
+ TRIGGER_CODE_LVL2 : out unsigned(3 downto 0);
+ TRIGGER_TAG_LVL2 : out unsigned(7 downto 0);
+ LVL1_START : out std_logic;
+ LVL2_START : out std_logic;
+ TRB_BUSY_LVL1 : in std_logic;
+ TRB_ERR_LVL1 : in std_logic;
+ TRB_ACK_LVL1 : in std_logic;
+ TRB_BUSY_LVL2 : in std_logic;
+ TRB_ERR_LVL2 : in std_logic;
+ TRB_ACK_LVL2 : in std_logic;
+ TRIGGER_STATUS_LVL1 : out std_logic_vector(7 downto 0);
+ TRIGGER_COUNTER_LVL1 : out unsigned(7 downto 0);
+ TRIGGER_DEADTIME_LVL1 : in std_logic_vector(7 downto 0);
+ TRIGGER_STATUS_LVL2 : out std_logic_vector(7 downto 0);
+ TRIGGER_COUNTER_LVL2 : out unsigned(7 downto 0);
+ TRIGGER_DEADTIME_LVL2 : in std_logic_vector(7 downto 0);
+ DTU_DEBUG_11 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_12 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_13 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_14 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_21 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_22 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_23 : out std_logic_vector(7 downto 0);
+ DTU_DEBUG_24 : out std_logic_vector(7 downto 0);
+ TRB_DEBUG_07 : out std_logic_vector(15 downto 0);
+ TRB_DEBUG_08 : out std_logic_vector(15 downto 0);
+ TRB_DEBUG_09 : out std_logic_vector(15 downto 0);
+ TRB_DEBUG_10 : out std_logic_vector (15 downto 0);
+ TRB_DEBUG_11 : out std_logic_vector (15 downto 0);
+ TRB_DEBUG_12 : out std_logic_vector (15 downto 0)
+ );
end component;
- component dsp_interface
+
+ component dtu_interface
port (
--- signal to/from dsp
- HBR_OUT : out std_logic; -- Host Bus Request to DSP
- HBG_IN : in std_logic; -- Host Bus Grant from DSP
- RD_OUT : out std_logic; -- read/write enable of DSP
- DSP_DATA_OUT : out std_logic_vector(31 downto 0);
- DSP_DATA_IN : in std_logic_vector(31 downto 0);
- ADDRESS_DSP : out std_logic_vector(31 downto 0);
- WRL : out std_logic; --when dsp slave is output
- WRH : out std_logic; --when dsp slave is output
- BM_IN : in std_logic; --Bus Master. For debug
- DSP_RESET : out std_logic;
- BRST : inout std_logic;
- ACK : in std_logic;
---internal data and address bus
- CLK : in std_logic;
- RESET : in std_logic;
- R_W_ENABLE : in std_logic;
- TRIGGER : in std_logic;
- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0
- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0
- INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
- VALID_DATA_SENT : out std_logic;
- ACKNOWLEDGE : in std_logic;
- DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
- );
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_TRIGGER_BUS : in std_logic;
+ LVL1_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL1_ERROR_BUS : out std_logic;
+ LVL1_BUSY_BUS : out std_logic;
+ LVL1_TRIGGER : out std_logic;
+ LVL1_CODE : out std_logic_vector(3 downto 0);
+ LVL1_TAG : out std_logic_vector(7 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_TRIGGER_BUS : in std_logic;
+ LVL2_DATA_BUS : in std_logic_vector(3 downto 0);
+ LVL2_ERROR_BUS : out std_logic;
+ LVL2_BUSY_BUS : out std_logic;
+ LVL2_TRIGGER : out std_logic;
+ LVL2_CODE : out std_logic_vector(3 downto 0);
+ LVL2_TAG : out std_logic_vector(7 downto 0);
+ LVL2_BUSY : in std_logic;
+ LVL2_TRB_ACK : in std_logic;
+ DTU_DEBUG_00 : out std_logic_vector( 31 downto 0));
end component;
+
-----------------------------------------------------------------------------
-- SPI --component !!!
-----------------------------------------------------------------------------
signal test_en_tdc_clk : std_logic;
signal test_en : std_logic;
signal busy_register_00_i : std_logic_vector(31 downto 0);
+ signal busy_register_01_i : std_logic_vector(31 downto 0);
signal trigger_register_00_i : std_logic_vector(31 downto 0);
+ signal lvl2_trigger_code_i : std_logic_vector(3 downto 0);
+ signal trb_ack_lvl1_long_i : std_logic;
+ signal trb_ack_lvl2_long_i : std_logic;
+ signal lvl1_counter_ack : std_logic_vector(7 downto 0);
+ signal lvl2_counter_ack : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_delay : std_logic;
+ signal lvl2_delay_trigg_count : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_code_synch : std_logic;
+ signal write_lvl1_busy_i : std_logic;
+
begin
TDC_REGISTER_00 => tdc_register_00_i,
BUNCH_RESET => bunch_reset_i,
EVENT_RESET => event_reset_i,
- READ_ADRESS_END_UP => trb_ack_lvl2_i);
+ READ_ADRESS_END_UP => trb_ack_lvl2_i,
+ MY_LVL1_COUNTER => busy_register_01_i(15 downto 8));
-- -------------------------------------------------------------------------------
-- -- sim
-- -------------------------------------------------------------------------------
- how_many_add_data_i <= x"05"; --put this to etrax register !!!!
- lvl1_trigger_i <= A_TEMP;
- simulation_00 <= A_RESERVED & B_RESERVED & C_RESERVED & D_RESERVED;
- lvl2_trigger_i <= B_TEMP & C_TEMP;
- tdc_tag_i <= x"ab";
- tdc_code_i <= simulation_00;
+ how_many_add_data_i <= x"00"; --put this to etrax register !!!!
+-- lvl1_trigger_i <= A_TEMP;
+-- simulation_00 <= A_RESERVED & B_RESERVED & C_RESERVED & D_RESERVED;
+-- lvl2_trigger_i <= B_TEMP & C_TEMP;
+-- tdc_tag_i <= x"ab";
+-- tdc_code_i <= simulation_00;
-- -------------------------------------------------------------------------------
-- -- end sim
-- -------------------------------------------------------------------------------
TDC_LVL1_BUSY => tdc_lvl1_busy_i,
TDC_LVL2_BUSY => tdc_lvl2_busy_i,
ETRAX_BUS_BUSY => etrax_bus_busy_i,
- ETRAX_BUSY => FS_PC(16),
+ ETRAX_BUSY => '0',--FS_PC(16), --correct this !"!!!!!!!!!!!!!!!
LVL1_TRIGG => lvl1_trigger_i,
LVL2_TRIGG => lvl2_trigger_i(0),
TRIGGER_CODE => lvl1_trigger_code_i,
TDC_READOUT_COMPLETED => tdc_readout_completed_i,
TRIGGER_WITHOUT_HADES => trigg_without_hades_i,
- BUSY_REGISTER_00 => busy_register_00_i
+ BUSY_REGISTER_00 => busy_register_00_i,
+ BUSY_REGISTER_01 => busy_register_01_i,
+ WRITE_LVL1_BUSY => write_lvl1_busy_i
);
-- trigg_without_hades_i <= TDC_CLK;
SYNCH_EXT_TRIGG: process (CLK, external_reset_i)
TDC_CODE => tdc_code_i,
TDC_TAG => tdc_tag_i,
LVL2_TRIGGER => lvl2_trigger_i,
+ LVL2_TRIGGER_CODE => lvl2_trigger_code_i,
LVL1_TRIGGER => lvl1_trigger_i,
LVL1_TDC_TRIGG => lvl1_tdc_trigg_i,
LVL2_TDC_TRIGG => lvl2_tdc_trigg_i,
TRIGG_WITHOUT_HADES => trigg_without_hades_i,
TDC_CONTROL_REGISTER => tdc_control_register_i,
DELAY_TRIGGER => x"00", --delay_trigger_i,
- LVL1_BUSY => lvl1_busy_i,
- LVL2_BUSY => lvl2_busy_i,
+ LVL1_BUSY => write_lvl1_busy_i,--27.03lvl1_busy_i,
+ LVL2_BUSY => tdc_lvl2_busy_i, --27.03lvl2_busy_i
TRB_ACK_LVL1 => trb_ack_lvl1_i,
TRB_ACK_LVL2 => trb_ack_lvl2_i,
TRIGGER_TO_TDC => trigger_to_tdc_i,
- TRIGGER_REGISTER_00 => trigger_register_00_i
+ TRIGGER_REGISTER_00 => trigger_register_00_i,
+ LVL2_BUSY_ALL => lvl2_busy_i
);
a_trigg <= trigger_to_tdc_i;
FPGA_REGISTER_05 => trigger_register_00_i,
FPGA_REGISTER_06 => x"abbaab05",
FPGA_REGISTER_07 => fpga_register_07_i,
- FPGA_REGISTER_08 => x"abbaab07",
+ FPGA_REGISTER_08 => busy_register_01_i,
FPGA_REGISTER_09 => x"abbaab08",
FPGA_REGISTER_10 => x"abbaab09",
FPGA_REGISTER_11 => x"abbaab10",
FPGA_REGISTER_29 => open,
FPGA_REGISTER_30 => open,
FPGA_REGISTER_31 => open,
- EXTERNAL_RESET => external_reset_i);
+ EXTERNAL_RESET => external_reset_i,
+ LVL2_VALID => lvl2_trigger_code_synch --lvl2_trigger_code_i(3)
+ );
TLK_RX_CLK_BUFR: BUFR
port map(
CE => '1',
I => TLK_CLK,
O => tlk_clk_r
);
- tlk_interface_logic: tlk_interface
- port map (
- VIRT_CLK => CLK,
- ENABLE => TLK_ENABLE,
- LCKREFN => TLK_LCKREFN,
- LOOPEN => TLK_LOOPEN,
- PRBSEN => TLK_PRBSEN,
- RX_CLK => tlk_rx_clk_r,
- RX_DV => TLK_RX_DV,
- RX_ER => TLK_RX_ER,
- TLK_CLK => tlk_clk_r,
- TLK_RXD => TLK_RXD,
- TLK_TXD => TLK_TXD,
- TX_EN => TLK_TX_EN,
- TX_ER => TLK_TX_ER,
- RESET_VIRT => external_reset_i,
- TLK_REGISTER_00 => tlk_register_00_i,
- TLK_REGISTER_01 => tlk_register_01_i
- );
+-- tlk_interface_logic: tlk_interface
+-- port map (
+-- VIRT_CLK => CLK,
+-- ENABLE => TLK_ENABLE,
+-- LCKREFN => TLK_LCKREFN,
+-- LOOPEN => TLK_LOOPEN,
+-- PRBSEN => TLK_PRBSEN,
+-- RX_CLK => tlk_rx_clk_r,
+-- RX_DV => TLK_RX_DV,
+-- RX_ER => TLK_RX_ER,
+-- TLK_CLK => tlk_clk_r,
+-- TLK_RXD => TLK_RXD,
+-- TLK_TXD => TLK_TXD,
+-- TX_EN => TLK_TX_EN,
+-- TX_ER => TLK_TX_ER,
+-- RESET_VIRT => external_reset_i,
+-- TLK_REGISTER_00 => tlk_register_00_i,
+-- TLK_REGISTER_01 => tlk_register_01_i
+-- );
dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
- DSP_INTERFACE_LOGIC: dsp_interface
- port map (
- HBR_OUT => dsp_hbr_i,
- HBG_IN => DSP_HBG,
- RD_OUT => DSP_RD_i,
- DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP,
- DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA,
- ADDRESS_DSP => dspaddr_i,--DSPADDR,
- WRL => DSP_WRL_i,
- WRH => DSP_WRH,
- BM_IN => DSP_BM,
- DSP_RESET => open,
- BRST => DSP_BRST,
- ACK => DSP_ACK,
- CLK => CLK,
- RESET => external_reset_i,
- R_W_ENABLE => external_mode_i(15),
- TRIGGER => dsp_strobe_i,
- INTERNAL_DATA_IN => external_data_out_i,
- INTERNAL_DATA_OUT => external_data_in_i,
- INTERNAL_ADDRESS => external_address_i,
- VALID_DATA_SENT => dsp_external_valid_i,
- ACKNOWLEDGE => dsp_strobe_i,
- DEBUGSTATE_MACHINE => dsp_register_00_i);
-
+-- DSP_INTERFACE_LOGIC: dsp_interface
+-- port map (
+-- HBR_OUT => dsp_hbr_i,
+-- HBG_IN => DSP_HBG,
+-- RD_OUT => DSP_RD_i,
+-- DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP,
+-- DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA,
+-- ADDRESS_DSP => dspaddr_i,--DSPADDR,
+-- WRL => DSP_WRL_i,
+-- WRH => DSP_WRH,
+-- BM_IN => DSP_BM,
+-- DSP_RESET => open,
+-- BRST => DSP_BRST,
+-- ACK => DSP_ACK,
+-- CLK => CLK,
+-- RESET => external_reset_i,
+-- R_W_ENABLE => external_mode_i(15),
+-- TRIGGER => dsp_strobe_i,
+-- INTERNAL_DATA_IN => external_data_out_i,
+-- INTERNAL_DATA_OUT => external_data_in_i,
+-- INTERNAL_ADDRESS => external_address_i,
+-- VALID_DATA_SENT => dsp_external_valid_i,
+-- ACKNOWLEDGE => dsp_strobe_i,
+-- DEBUGSTATE_MACHINE => dsp_register_00_i);
+ -- ADO_TTL(18) <= '1';
+ ADO_TTL(15 downto 0) <= (others => 'Z');
+
+-- dtu_instance : DTU port map (
+-- T_CLK_40 => tdc_clk,
+-- T_RES => external_reset_i,
+-- T_TRIGBUS_TSTR_LVL1 => ADO_TTL(4), --ttl_connector
+-- T_TRIGBUS_DSTR_LVL1 => ADO_TTL(9),
+-- T_TRIGBUS_DIN_LVL1 => ADO_TTL(8 downto 5),
+-- T_TRIGBUS_BUSY_LVL1 => ADO_TTL(0),
+-- T_TRIGBUS_ERR_LVL1 => ADO_TTL(1),
+-- T_TRIGBUS_TSTR_LVL2 => ADO_TTL(10),
+-- T_TRIGBUS_DSTR_LVL2 => ADO_TTL(15),
+-- T_TRIGBUS_DIN_LVL2 => ADO_TTL(14 downto 11),
+-- T_TRIGBUS_BUSY_LVL2 => ADO_TTL(2),
+-- T_TRIGBUS_ERR_LVL2 => ADO_TTL(3),
+-- std_logic_vector(TRIGGER_CODE_LVL1) => lvl1_trigger_code_i,
+-- std_logic_vector(TRIGGER_TAG_LVL1) => lvl1_trigger_tag_i,
+-- std_logic_vector(TRIGGER_CODE_LVL2) => lvl2_trigger_code_i,
+-- TRIGGER_TAG_LVL2 => open,
+-- LVL1_START => lvl1_trigger_i,
+-- LVL2_START => lvl2_trigger_i(0),--lvl2_trigger_delay,
+-- TRB_BUSY_LVL1 => lvl1_busy_i,
+-- TRB_ERR_LVL1 => '0',
+-- TRB_ACK_LVL1 => trb_ack_lvl1_long_i,
+-- TRB_BUSY_LVL2 => lvl2_busy_i,
+-- TRB_ERR_LVL2 => '0',
+-- TRB_ACK_LVL2 => trb_ack_lvl2_long_i,
+-- TRIGGER_STATUS_LVL1 => open,
+-- TRIGGER_COUNTER_LVL1 => open,
+-- TRIGGER_DEADTIME_LVL1 => x"07",
+-- TRIGGER_STATUS_LVL2 => open,
+-- TRIGGER_COUNTER_LVL2 => open,
+-- TRIGGER_DEADTIME_LVL2 => x"07",
+-- DTU_DEBUG_11 => open,--DTU_DEBUG_11_i,
+-- DTU_DEBUG_12 => open,--DTU_DEBUG_12_i,
+-- DTU_DEBUG_13 => open,
+-- DTU_DEBUG_14 => open,
+-- DTU_DEBUG_21 => open,--DTU_DEBUG_21_i, --LVL2 states
+-- DTU_DEBUG_22 => open,--DTU_DEBUG_22_i,
+-- DTU_DEBUG_23 => open,
+-- DTU_DEBUG_24 => open,
+-- TRB_DEBUG_07 => open,--TRB_DEBUG_07_i,
+-- TRB_DEBUG_08 => open,--TRB_DEBUG_08_i,
+-- TRB_DEBUG_09 => open,--TRB_DEBUG_09_i,
+-- TRB_DEBUG_10 => open,--TRB_DEBUG_10_i,
+-- TRB_DEBUG_11 => open,--TRB_DEBUG_11_i,
+-- TRB_DEBUG_12 => open
+-- );
+ DTU_INT: dtu_interface
+ port map (
+ CLK => CLK,
+ RESET => external_reset_i,
+ LVL1_TRIGGER_BUS => ADO_TTL(4),
+ LVL1_DATA_TRIGGER_BUS => ADO_TTL(9),
+ LVL1_DATA_BUS => ADO_TTL(8 downto 5),
+ LVL1_ERROR_BUS => ADO_TTL(1),
+ LVL1_BUSY_BUS => ADO_TTL(0),
+ LVL1_TRIGGER => lvl1_trigger_i,
+ LVL1_CODE => lvl1_trigger_code_i,
+ LVL1_TAG => lvl1_trigger_tag_i,
+ LVL1_BUSY => lvl1_busy_i,
+ LVL2_TRIGGER_BUS => ADO_TTL(10),
+ LVL2_DATA_TRIGGER_BUS => ADO_TTL(15),
+ LVL2_DATA_BUS => ADO_TTL(14 downto 11),
+ LVL2_ERROR_BUS => ADO_TTL(3),
+ LVL2_BUSY_BUS => ADO_TTL(2),
+ LVL2_TRIGGER => lvl2_trigger_i(0),
+ LVL2_CODE => lvl2_trigger_code_i,
+ LVL2_TAG => open,
+ LVL2_BUSY => lvl2_busy_i,
+ LVL2_TRB_ACK => trb_ack_lvl2_i,
+ DTU_DEBUG_00 => open);
+
+
+
+
+-- MAKE_DELAYED_LVL2_TRIGGER: process (CLK, external_reset_i)
+-- begin -- process MAKE_LONG_ACK
+-- if rising_edge(CLK) then -- rising clock edge
+-- if external_reset_i = '1' then -- asynchronous reset (active low)
+-- lvl2_delay_trigg_count <= x"2f";
+-- elsif lvl2_trigger_delay ='1' then
+-- lvl2_delay_trigg_count <= x"00";
+-- elsif lvl2_delay_trigg_count < x"2f" then
+-- lvl2_delay_trigg_count <= lvl2_delay_trigg_count + 1;
+-- else
+-- lvl2_delay_trigg_count <= lvl2_delay_trigg_count;
+-- end if;
+-- end if;
+-- end process MAKE_DELAYED_LVL2_TRIGGER;
+-- lvl2_trigger_i(0) <= '1' when lvl2_delay_trigg_count = x"20" else '0';
+ MAKE_LONG_LVL1_ACK: process (CLK, external_reset_i)
+ begin -- process MAKE_LONG_ACK
+ if rising_edge(CLK) then -- rising clock edge
+ if external_reset_i = '1' then -- asynchronous reset (active low)
+ trb_ack_lvl1_long_i <= '0';
+ lvl1_counter_ack <= x"1f";
+ elsif trb_ack_lvl1_i ='1' then
+ lvl1_counter_ack <= x"00";
+ trb_ack_lvl1_long_i <= '1';
+ elsif lvl1_counter_ack < x"1f" then
+ lvl1_counter_ack <= lvl1_counter_ack + 1;
+ trb_ack_lvl1_long_i <= '1';
+ else
+ trb_ack_lvl1_long_i <= '0';
+ lvl1_counter_ack <= lvl1_counter_ack;
+ end if;
+ end if;
+ end process MAKE_LONG_LVL1_ACK;
+ MAKE_LONG_LVL2_ACK: process (CLK, external_reset_i)
+ begin -- process MAKE_LONG_ACK
+ if rising_edge(CLK) then -- rising clock edge
+ if external_reset_i = '1' then--or trb_ack_lvl2_i ='1' then -- asynchronous reset (active low)
+ -- trb_ack_lvl2_long_i <= '0';
+ lvl2_counter_ack <= x"1f";
+ -- elsif trb_ack_lvl2_i ='1' then
+ -- lvl2_counter_ack <= x"00";
+ -- trb_ack_lvl2_long_i <= '1';
+ elsif trb_ack_lvl2_i ='1' then
+ lvl2_counter_ack <= x"00";
+ elsif lvl2_counter_ack < x"1f" then
+ lvl2_counter_ack <= lvl2_counter_ack + 1;
+ -- trb_ack_lvl2_long_i <= '1';
+ else
+ -- trb_ack_lvl2_long_i <= '0';
+ lvl2_counter_ack <= lvl2_counter_ack;
+ end if;
+ end if;
+ end process MAKE_LONG_LVL2_ACK;
+ LVL2_CODE_SYNCH: process (CLK, external_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' then
+ lvl2_trigger_code_synch <= '0' ;
+ else
+ lvl2_trigger_code_synch <= lvl2_trigger_code_i(3);
+
+ end if;
+ end if;
+ end process LVL2_CODE_SYNCH;
+ trb_ack_lvl2_long_i <= '1' when lvl2_counter_ack < x"1f" else '0';
+
SFP_TX_DIS <= '0';
ETRAX_IRQ <= '1';
DBAD <= lvl1_busy_i;
-- ADO_TTL <= "000" & x"0000000" & DSP_WRL_i & DSP_RD_i & "0" &
-- dspdat_in_i(4 downto 0) & dspdat_out_i(4 downto 0)
-- & CLK & fpga_register_07_i(2 downto 1);
- ADO_TTL <= "000" & x"0000000" & trigg_without_hades_i & trb_ack_lvl1_i & busy_register_00_i(0) & tdc_data_valid_i & etrax_bus_busy_i & tdc_readout_completed_i&TOKEN_IN & A_DATA_READY & B_DATA_READY & C_DATA_READY & D_DATA_READY & etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i;
+ -- ADO_TTL(15 downto 0) <= trigg_without_hades_i & trb_ack_lvl1_i & busy_register_00_i(0) & tdc_data_valid_i & etrax_bus_busy_i & tdc_readout_completed_i&TOKEN_IN & A_DATA_READY & B_DATA_READY & C_DATA_READY & D_DATA_READY & etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i;
+ -- ADO_TTL(15 downto 0) <= x"00" & lvl2_busy_i & tdc_lvl2_busy_i & tdc_data_valid_i & etrax_is_ready_to_read_i & lvl2_trigger_code_i(3) & trb_ack_lvl2_i &trb_ack_lvl2_long_i & lvl1_busy_i;
-- trb_status_register_00 <= etrax_bus_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl2_busy_i & lvl1_busy_i;
-- clk & tdc_clk & event_reset_i no & bunch_reset_i no & trigger_to_tdc_i yes & TOKEN_
-- OUT '1' & lvl1_tdc_trigg_i yes & A_DATA_READY no & B_DATA_READY no & C_DATA_
#add_file options
+add_file -vhdl -lib work "simpleupcounter_16bit.vhd"
add_file -vhdl -lib work "etrax_interface.vhd"
#add_file -vhdl -lib work "lvl1_fifo.vhd"
add_file -vhdl -lib work "trigger_logic.vhd"
add_file -vhdl -lib work "trbnet/optical_link_to_64_bit.vhd"
add_file -vhdl -lib work "up_down_counter_10bit.vhd"
add_file -vhdl -lib work "simpleupcounter_10bit.vhd"
-add_file -vhdl -lib work "simpleupcounter_16bit.vhd"
+add_file -vhdl -lib work "dtu_interface.vhd"
add_file -vhdl -lib work "dsp_interface.vhd"
+add_file -vhdl -lib work "dtu/FIFO2MDC.vhd"
+add_file -vhdl -lib work "dtu/Fifo.vhd"
+add_file -vhdl -lib work "dtu/L12TrigBusInterface.vhd"
+add_file -vhdl -lib work "dtu/L1StateFull.vhd"
+add_file -vhdl -lib work "dtu/L2StateFull.vhd"
+add_file -vhdl -lib work "dtu/LEVEL_2_DTU_MDC.vhd"
+add_file -vhdl -lib work "dtu/LEVEL_1_DTU_MDC.vhd"
+add_file -vhdl -lib work "dtu/LVL1State.vhd"
+add_file -vhdl -lib work "dtu/LVL2State.vhd"
+add_file -vhdl -lib work "dtu/Triggercounter.vhd"
+add_file -vhdl -lib work "dtu/deadtime.vhd"
+add_file -vhdl -lib work "dtu/dtu.vhd"
+add_file -vhdl -lib work "dtu/ram16x12.vhd"
#add_file -vhdl -lib work "lvl1_memory.vhd"
#add_file -vhdl -lib work ""
#add_file -vhdl -lib work ""
DSP_BRST : inout std_logic;
DSP_ACK : in std_logic;
DSP_BM : in std_logic;
- ADO_TTL : out std_logic_vector(46 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
A_TDC_ERROR : in std_logic;
B_TDC_ERROR : in std_logic;
C_TDC_ERROR : in std_logic;
SIGNAL C_TRIGGERB : std_logic;
SIGNAL D_TRIGGER : std_logic;
SIGNAL D_TRIGGERB : std_logic;
+ signal dtu_clk : std_logic;
+ signal dtu_lvl1_tag : std_logic_vector(7 downto 0):=x"00";
+ signal dtu_lvl2_tag : std_logic_vector(7 downto 0):=x"00";
+ signal lvl1_trig : std_logic:='0';
+ signal lvl2_trig : std_logic:='0';
+ signal ADO_TTL : std_logic_vector(46 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
C_TRIGGER => C_TRIGGER ,
C_TRIGGERB => C_TRIGGERB ,
D_TRIGGER => D_TRIGGER ,
- D_TRIGGERB => D_TRIGGERB
+ D_TRIGGERB => D_TRIGGERB,
+ ADO_TTL => ADO_TTL
);
+-------------------------------------------------------------------------------
+-- etrax_int_test
+-------------------------------------------------------------------------------
+-- etrax_intf : PROCESS
+-- BEGIN
- etrax_intf : PROCESS
- BEGIN
-
- --reading DSP(dev number 1)
- wait for 10 ns;
- RESET_VIRT <= '0';
+-- --reading DSP(dev number 1)
+-- wait for 10 ns;
+-- RESET_VIRT <= '0';
- wait for 10 ns;
- FS_PC(16) <= '1';
- FS_PC(17) <= '1';
- RESET_VIRT <= '1';
- wait for 10 ns;
+-- wait for 10 ns;
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '1';
+-- RESET_VIRT <= '1';
+-- wait for 10 ns;
- wait for 30 ns;
--- FS_PC(16) <= '0';
--- FS_PC(17) <= '0';
--- wait for 10 ns;
- FS_PC(15 downto 0) <= x"0000";
- FS_PC(16) <= '0';
- FS_PC(17) <= '0';
- wait on VIRT_CLK until FS_PB(16) = '0';
- wait for 20 ns;
- FS_PC(16) <= '1';
- wait for 20 ns;
- FS_PC(15) <= '1'; --read mode
- FS_PC(14 downto 8) <= (others => '0');
- FS_PC(7 downto 0) <= x"00"; --device
- FS_PC(16) <= '0';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(15 downto 0) <= x"0000"; --address upper part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '1';
- FS_PC(15 downto 0) <= x"0025"; --adrees lower part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait on VIRT_CLK until FS_PB(16)= '1';
- FS_PC(16) <= '1';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait on VIRT_CLK until FS_PB(16) = '0';
- FS_PC(16) <= '1';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait on VIRT_CLK until FS_PB(16)= '1';
- FS_PC(16) <= '1';
- wait for 20 ns;
- FS_PC(16) <= '0';
- --writing DSP
- wait for 20 ns;
- FS_PC(16) <= '1';
- test_synch_00 <= '1';
- wait for 20 ns;
- FS_PC(15) <= '0'; --write mode
- FS_PC(14 downto 8) <= (others => '0');
- FS_PC(7 downto 0) <= x"00"; --device
- FS_PC(16) <= '0';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(15 downto 0) <= x"0000"; --address upper part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '1';
- FS_PC(15 downto 0) <= x"0021"; --adrees lower part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait for 20 ns;
- FS_PC(15 downto 0) <= x"0000"; --data upper part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait for 20 ns;
- FS_PC(15 downto 0) <= x"0001"; --data upper part
- FS_PC(16) <= '1';
- FS_PC(17) <= '0';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait for 20 ns;
- test_synch_00 <= '0';
- FS_PC(16) <= '1';
- wait for 20 ns;
- FS_PC(16) <= '0';
- wait on VIRT_CLK until FS_PB(16)= '1';
- loop
- wait on VIRT_CLK until FS_PB(17) = '1';
- FS_PC(17) <= '1';
- wait for 50 ns;
- FS_PC(17) <= '0';
- wait for 50 ns;
- end loop;
+-- wait for 30 ns;
+-- -- FS_PC(16) <= '0';
+-- -- FS_PC(17) <= '0';
+-- -- wait for 10 ns;
+-- FS_PC(15 downto 0) <= x"0000";
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait on VIRT_CLK until FS_PB(16) = '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '1';
+-- wait for 20 ns;
+-- FS_PC(15) <= '1'; --read mode
+-- FS_PC(14 downto 8) <= (others => '0');
+-- FS_PC(7 downto 0) <= x"00"; --device
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(15 downto 0) <= x"0000"; --address upper part
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '1';
+-- FS_PC(15 downto 0) <= x"0025"; --adrees lower part
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait on VIRT_CLK until FS_PB(16)= '1';
+-- FS_PC(16) <= '1';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait on VIRT_CLK until FS_PB(16) = '0';
+-- FS_PC(16) <= '1';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait on VIRT_CLK until FS_PB(16)= '1';
+-- FS_PC(16) <= '1';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- --writing DSP
+-- wait for 20 ns;
+-- FS_PC(16) <= '1';
+-- test_synch_00 <= '1';
+-- wait for 20 ns;
+-- FS_PC(15) <= '0'; --write mode
+-- FS_PC(14 downto 8) <= (others => '0');
+-- FS_PC(7 downto 0) <= x"00"; --device
+-- FS_PC(16) <= '0';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(15 downto 0) <= x"0000"; --address upper part
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '1';
+-- FS_PC(15 downto 0) <= x"0021"; --adrees lower part
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait for 20 ns;
+-- FS_PC(15 downto 0) <= x"0000"; --data upper part
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait for 20 ns;
+-- FS_PC(15 downto 0) <= x"0001"; --data upper part - 1 switch on
+-- --internal generation of trigger
+-- FS_PC(16) <= '1';
+-- FS_PC(17) <= '0';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait for 20 ns;
+-- test_synch_00 <= '0';
+-- FS_PC(16) <= '1';
+-- wait for 20 ns;
+-- FS_PC(16) <= '0';
+-- wait on VIRT_CLK until FS_PB(16)= '1';
+-- loop
+-- wait on VIRT_CLK until FS_PB(17) = '1';
+-- FS_PC(17) <= '1';
+-- wait for 50 ns;
+-- FS_PC(17) <= '0';
+-- wait for 50 ns;
+-- end loop;
- wait; -- will wait forever
- end process;
+-- wait; -- will wait forever
+-- end process;
+
+
+
clock_gclk : process
begin
VIRT_CLK <= '1';
wait for 5 ns;
end process;
+
+
dsp : process
begin
-----------------------------------------------------------------------
clock_tdcclk : process
begin
+ wait for 15 ns;
+ loop
REF_TDC_CLK <= '0';
REF_TDC_CLKB <= '1';
wait for 12.5 ns;
REF_TDC_CLK <= '1';
REF_TDC_CLKB <= '0';
wait for 12.5 ns;
+ end loop;
end process;
trigger_lvl1 : process
begin
-- C_TEMP <= '1';
-- wait for 30 ns;
-- end process;
+
+ -----------------------------------------------------------------------
+ -- DTU
+ -----------------------------------------------------------------------
+ clock_dtu : process
+ begin
+ wait for 34 ns;
+
+ loop
+ dtu_clk <= '0';
+ wait for 50 ns;
+ dtu_clk <= '1';
+ wait for 50 ns;
+ end loop;
+ end process;
+ ADO_TTL(4) <= lvl1_trig;
+ ADO_TTL(10) <= lvl2_trig;
+-- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig)
+-- begin
+-- if rising_edge(dtu_clk) then
+-- if RESET_VIRT = '0' then
+-- dtu_lvl1_tag <= x"00";
+-- elsif ADO_TTL(17) = '1' then
+-- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+-- end if;
+-- end if;
+-- end process LVL1_TAG_COUNTER;
+ LVL1_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl1_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ loop
+ wait on dtu_clk until ADO_TTL(0) = '1';
+ wait for 1000 ns;
+ dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ end loop;
+ end process LVL1_COUNT;
+ LVL2_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl2_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ loop
+ wait on dtu_clk until ADO_TTL(2) = '1';
+ wait for 1000 ns;
+ dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ end loop;
+ end process LVL2_COUNT;
+
+
+-- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig)
+-- begin
+-- if rising_edge(dtu_clk) then
+-- if RESET_VIRT = '0' then
+-- dtu_lvl2_tag <= x"00";
+-- elsif lvl2_trig = '1' then
+-- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+-- end if;
+-- end if;
+-- end process LVL2_TAG_COUNTER;
+-- ADO_TTL(20 downto 17) <= (others => 'Z');
+
+
+ ADO_TTL(4) <= lvl1_trig;
+ DTU_EMULATION_LVL1: process
+ begin
+ ADO_TTL(9) <= '0';
+ lvl1_trig <= '0';
+ wait for 200 ns;
+ wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
+ lvl1_trig <= '1';
+ ADO_TTL(8 downto 5) <= x"d";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
+ loop
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
+ wait for 300 ns;
+ lvl1_trig <= '1';
+ ADO_TTL(8 downto 5) <= x"1";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
+ end loop;
+ end process DTU_EMULATION_LVL1;
+
+ ADO_TTL(10) <= lvl2_trig;
+ DTU_EMULATION_LVL2:process
+ begin
+ ADO_TTL(15) <= '0';
+ lvl2_trig <= '0';
+ wait for 26000 ns;
+ loop
+ ADO_TTL(15) <= '0';
+ wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; --busylvl2
+-- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ wait for 300 ns;
+ lvl2_trig <= '1';
+ ADO_TTL(14 downto 11) <= x"1";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+
+ wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1';
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ wait for 100 ns;
+ lvl2_trig <= '1';
+ ADO_TTL(14 downto 11) <= x"9";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ wait for 100 ns;
+ ADO_TTL(15) <= '1';
+ wait for 100 ns;
+ ADO_TTL(15) <= '0';
+ end loop;
+ end process DTU_EMULATION_LVL2;
+
+ ETRAX_RESPONSE: process
+ begin
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 10 ns;
+ RESET_VIRT <= '0';
+
+ wait for 10 ns;
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '1';
+ RESET_VIRT <= '1';
+ wait for 10 ns;
+
+ wait for 30 ns;
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 10 ns;
+ loop
+ FS_PC(17) <= '0';
+ wait on TLK_CLK until FS_PB(16) ='1';
+ wait for 20 ns;
+ FS_PC(17) <= '1';
+ wait for 2000 ns;
+ end loop;
+ end process ETRAX_RESPONSE;
+
END;
TDC_CODE : out std_logic_vector(3 downto 0);
TDC_TAG : out std_logic_vector(7 downto 0);
LVL2_TRIGGER : in std_logic_vector(1 downto 0); --0 trigger, 1 value
+ LVL2_TRIGGER_CODE : in std_logic_vector(3 downto 0);
LVL1_TRIGGER : in std_logic;
LVL1_TDC_TRIGG : out std_logic;
LVL2_TDC_TRIGG : out std_logic_vector(1 downto 0);
TRB_ACK_LVL1 : out std_logic;
TRB_ACK_LVL2 : out std_logic;
TRIGGER_TO_TDC : out std_logic;
- TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0)
+ TRIGGER_REGISTER_00 : out std_logic_vector(31 downto 0);
+ LVL2_BUSY_ALL : in std_logic
);
end trigger_logic;
end if;
when SEND_LVL2_TRIGG_1 =>
trigger_register_00_i(9 downto 7) <= "001";
- LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
- LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2;
+ LVL2_TDC_TRIGG <= "00";
+ if LVL2_BUSY_ALL = '0' then
+ LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2;
+ else
+ LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_1;
+ end if;
+-- LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0))) & '1';
+-- LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2;
when SEND_LVL2_TRIGG_2 =>
trigger_register_00_i(9 downto 7) <= "010";
- LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
+ LVL2_TDC_TRIGG <= "00";
+-- LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0))) & '1';
LVL2_START_fsm_nextstate <= WAIT_FOR_ACK;
when WAIT_FOR_ACK =>
trigger_register_00_i(9 downto 7) <= "011";
- LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
+ LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0))) & '1';
if ACK_LVL2_STATE = ACK_LVL2_PULSE_1 then
LVL2_START_fsm_nextstate <= IDLE;
else
case (ACK_LVL2_STATE) is
when IDLE =>
trigger_register_00_i(11 downto 10) <= "00";
- if LVL2_BUSY = '1' and LVL2_START_fsm_currentstate /= IDLE then
+ --03.27 if LVL2_BUSY = '1' and LVL2_START_fsm_currentstate ???? /= IDLE then
+ if LVL2_BUSY = '1' then
ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
else
ACK_LVL2_STATE <= IDLE;
jspc29 / trbv2.git / commitdiff