entity med_ecp3_sfp_sync_all_RS is
generic(
- SIM_MODE : integer := 0;
IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED);
IS_WAP_ZERO : integer := 1
);
txiclk_ch0 => clk_tx_full(0), -- drives TX FIFO bridge
rx_full_clk_ch0 => clk_rx_full(0), -- recovered RX clock
rx_half_clk_ch0 => clk_rx_half(0),
- tx_full_clk_ch0 => clk_tx_full(0), -- TX clock from PLL
+ tx_full_clk_ch0 => open, --clk_tx_full(0), -- TX clock from PLL
tx_half_clk_ch0 => clk_tx_half(0),
fpga_rxrefclk_ch0 => CLK_REF_FULL, -- reference RX clock
txdata_ch0 => tx_data(0*8+7 downto 0*8),
txiclk_ch1 => clk_tx_full(1),
rx_full_clk_ch1 => clk_rx_full(1),
rx_half_clk_ch1 => clk_rx_half(1),
- tx_full_clk_ch1 => clk_tx_full(1),
+ tx_full_clk_ch1 => open, --clk_tx_full(1),
tx_half_clk_ch1 => clk_tx_half(1),
fpga_rxrefclk_ch1 => CLK_REF_FULL,
txdata_ch1 => tx_data(1*8+7 downto 1*8),
txiclk_ch2 => clk_tx_full(2),
rx_full_clk_ch2 => clk_rx_full(2),
rx_half_clk_ch2 => clk_rx_half(2),
- tx_full_clk_ch2 => clk_tx_full(2),
+ tx_full_clk_ch2 => open, --clk_tx_full(2),
tx_half_clk_ch2 => clk_tx_half(2),
fpga_rxrefclk_ch2 => CLK_REF_FULL,
txdata_ch2 => tx_data(2*8+7 downto 2*8),
txiclk_ch3 => clk_tx_full(3),
rx_full_clk_ch3 => clk_rx_full(3),
rx_half_clk_ch3 => clk_rx_half(3),
- tx_full_clk_ch3 => clk_tx_full(3),
+ tx_full_clk_ch3 => open, --clk_tx_full(3),
tx_half_clk_ch3 => clk_tx_half(3),
fpga_rxrefclk_ch3 => CLK_REF_FULL,
txdata_ch3 => tx_data(3*8+7 downto 3*8),
tx_sync_qd_c => SYNC_TX_PLL_IN
);
+ clk_tx_full(0) <= MASTER_CLK_IN;
+ clk_tx_full(1) <= MASTER_CLK_IN;
+ clk_tx_full(2) <= MASTER_CLK_IN;
+ clk_tx_full(3) <= MASTER_CLK_IN;
+
gen_control : for i in 0 to 3 generate
gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate
THE_MED_CONTROL : entity work.med_sync_control_RS
generic map(
- SIM_MODE => SIM_MODE,
IS_WAP_ZERO => IS_WAP_ZERO,
IS_MODE => IS_MODE(i)
)
USE IEEE.numeric_std.all;\r
\r
entity main_tx_reset_RS is\r
- generic(\r
- SIM_MODE : integer := 0\r
- );\r
port(\r
CLEAR : in std_logic; -- async reset, active high\r
CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! \r
\r
architecture main_tx_reset_RS_arch of main_tx_reset_RS is\r
\r
- -- We use two different timing for simulation and real world.\r
- -- Using SIM_MODE for implementation will most likely kill the link.\r
- constant count_index : integer := 15 - (SIM_MODE * 9); -- end of timer\r
+ constant count_index : integer := 15; -- end of timer\r
\r
type statetype is ( IDLE, WAIT_FOR_TIMER, SYNC_ALL, SYNC_DONE, NORMAL );\r
\r
entity med_sync_control_RS is
generic(
- SIM_MODE : integer := 0; -- 0 for simulation, 1 for implementation
IS_WAP_ZERO : integer := 1; -- should be 1 for synchronous operation
IS_MODE : integer := c_IS_UNUSED
);
signal led_rx, last_led_rx : std_logic;
signal led_tx, last_led_tx : std_logic;
signal timer : unsigned(20 downto 0);
- signal sd_los_q : std_logic;
signal reset_i : std_logic;
signal link_tx_ready_i : std_logic;
-------------------------------------------------
-- Reset signals
-------------------------------------------------
--- synchronize SFP LOS signal
- SYNC_SFP_SIGS : entity work.signal_sync
- generic map(
- WIDTH => 1,
- DEPTH => 3
- )
- port map(
- RESET => '0',
- CLK0 => CLK_REF,
- CLK1 => CLK_REF,
- D_IN(0) => SFP_LOS_IN,
- D_OUT(0) => sd_los_q
- );
-- we use uplink signal detection as global reset (slave port)
-- doesn't make sense to start while no link partner is available
- GLOBAL_RESET_OUT <= sd_los_q;
+ GLOBAL_RESET_OUT <= SFP_LOS_IN;
-- TX_CONTROL and RX_CONTROL reset
--- reset_i <= (RESET or sd_los_q) when (IS_MODE = c_IS_SLAVE)
--- else (RESET);
reset_i <= RESET;
-
- -- We provide GLOBAL_RESET_OUT (in case of SLAVE port) to clock_reset_handler,
- -- which turns it into global RESET signal.
-- for syncing later
- link_tx_ready_i <= LINK_TX_READY_IN;
+ link_tx_ready_i <= LINK_TX_READY_IN; -- usually CLK_REF based
-------------------------------------------------
-- Reset RX FSM
CV_IN => RX_CV_IN,
LSM_IN => RX_LSM_IN,
LOS_IN => RX_LOS_IN,
- SD_LOS_IN => SFP_LOS_IN, -- could be "sd_los_q" (already sync'ed)
+ SD_LOS_IN => SFP_LOS_IN,
WAP_ZERO_IN => is_wap_zero_i,
-- outputs
RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based
-------------------------------------------------
-- RX Data
-------------------------------------------------
- THE_RX_CONTROL : rx_control_RS
- generic map(
- SIM_MODE => SIM_MODE
- )
+ THE_RX_CONTROL: rx_control_RS
port map(
CLK_RXI => CLK_RXI,
CLK_SYS => CLK_SYS,
-------------------------------------------------
THE_TX_CONTROL: tx_control_RS
generic map(
- SIM_MODE => SIM_MODE,
IS_MODE => IS_MODE
)
port map(
-------------------------------------------------
led_ok <= link_full_done_i when rising_edge(CLK_SYS);
led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS);
- led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS);
+-- led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS);
+ led_tx <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN) and not timer(20) when rising_edge(CLK_SYS);
ROC_TIMER_PROC: process( CLK_SYS, RESET )
begin
end component;\r
\r
component main_tx_reset_RS is\r
- generic(\r
- SIM_MODE : integer := 0\r
- );\r
port(\r
CLEAR : in std_logic; -- async reset, active high\r
CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! \r
end component;\r
\r
component rx_control_RS is\r
- generic(\r
- SIM_MODE : integer := 0\r
- );\r
port(\r
CLK_RXI : in std_logic;\r
CLK_SYS : in std_logic;\r
\r
component tx_control_RS is\r
generic(\r
- SIM_MODE : integer := 0;\r
IS_MODE : integer := c_IS_UNUSED\r
);\r
port(\r
use work.med_sync_define_RS.all;\r
\r
entity rx_control_RS is\r
- generic(\r
- SIM_MODE : integer := 0\r
- );\r
port(\r
CLK_RXI : in std_logic;\r
CLK_SYS : in std_logic;\r
\r
end case;\r
\r
+ -- BUG: master ports don't reset correctly\r
-- if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then\r
if( (RESET = '1') ) then\r
rx_state <= SLEEP;\r
\r
entity tx_control_RS is\r
generic(\r
- SIM_MODE : integer := 0;\r
IS_MODE : integer := c_IS_UNUSED\r
);\r
port(\r
jspc29 / trbnet.git / commitdiff