debugging

diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd
index 35d17e7fb5017d856e1941c3490ecdbf0977e153..91f8e25ce7061f952fa0476bc740ce0aaf3c7fd8 100644 (file)
--- a/gbe_trb/base/gbe_logic_wrapper.vhd
+++ b/gbe_trb/base/gbe_logic_wrapper.vhd
@@ -30,7 +30,6 @@ entity gbe_logic_wrapper is
     MY_IP_OUT                : out std_logic_vector(31 downto 0);              
     MY_TRBNET_ADDRESS_IN     : in  std_logic_vector(15 downto 0);
     ISSUE_REBOOT_OUT         : out std_logic;
-
     -- connection to MAC
     MAC_READY_CONF_IN        : in  std_logic;
     MAC_RECONF_OUT           : out std_logic;
@@ -133,7 +132,8 @@ entity gbe_logic_wrapper is
     MONITOR_TX_PACKETS_OUT   : out std_logic_vector(31 downto 0);
     MONITOR_DROPPED_OUT      : out std_logic_vector(31 downto 0);
     MONITOR_GEN_DBG_OUT      : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
-    MAKE_RESET_OUT           : out std_logic
+    MAKE_RESET_OUT           : out std_logic;
+    DEBUG_OUT                : out std_logic_vector(31 downto 0)
   );
 end entity gbe_logic_wrapper;
 
@@ -574,6 +574,12 @@ begin
       MONITOR_DROPPED_OUT     => monitor_dropped
     );
 
+  DEBUG_OUT(0) <= fr_rd_en;
+  DEBUG_OUT(1) <= fr_frame_valid;
+  DEBUG_OUT(2) <= fr_get_frame;
+  DEBUG_OUT(3) <= monitor_dropped(0);
+  DEBUG_OUT(4) <= monitor_dropped(1);
+    
   MONITOR_RX_FRAMES_OUT  <= monitor_rx_frames;
   MONITOR_RX_BYTES_OUT   <= monitor_rx_bytes;
   MONITOR_TX_FRAMES_OUT  <= monitor_tx_frames;

diff --git a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd
index e6d7d3fd0af8ef1986fa3567cd95bccbf412c027..9d8b417686d40ae331472c3d14f67d1816df524e 100644 (file)
--- a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd
+++ b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd
@@ -651,7 +651,6 @@ begin
   end if;
 end process THE_ERROR_FRAMES_CTR_PROC;
 
--- not needed anymore?
 FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK);
 
 THE_RECEIVED_FRAMES_CTR: process( CLK )
@@ -676,10 +675,12 @@ begin
   end if;
 end process THE_DROPPED_FRAMES_CTR;
 
-MONITOR_DROPPED_OUT   <= std_logic_vector(dbg_drp_frames);
+--MONITOR_DROPPED_OUT   <= std_logic_vector(dbg_drp_frames);
 MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames);
 MONITOR_RX_BYTES_OUT  <= std_logic_vector(mon_rec_bytes);
 
+MONITOR_DROPPED_OUT(0) <= rec_fifo_empty;
+MONITOR_DROPPED_OUT(1) <= fifo_wr_en;
 
 THE_MON_REC_BYTES_PROC: process(CLK)
 begin

diff --git a/gbe_trb/base/trb_net16_gbe_receive_control.vhd b/gbe_trb/base/trb_net16_gbe_receive_control.vhd
index 4a7bc6f52d074312fa44535684b25dee31897c1c..42a3fcb7f8ca689b336003b5b0d157c5c7fe76f9 100644 (file)
--- a/gbe_trb/base/trb_net16_gbe_receive_control.vhd
+++ b/gbe_trb/base/trb_net16_gbe_receive_control.vhd
@@ -16,57 +16,49 @@ use work.trb_net_gbe_protocols.all;
 -- the message received from receiver, frame checking is already done
 -- 
 
-
 entity trb_net16_gbe_receive_control is
 port (
-       CLK                     : in    std_logic;  -- system clock
-       RESET                   : in    std_logic;
-
+  CLK                      : in  std_logic;  -- system clock
+  RESET                    : in  std_logic;
 -- signals to/from frame_receiver
-       RC_DATA_IN              : in    std_logic_vector(8 downto 0);
-       FR_RD_EN_OUT            : out   std_logic;
-       FR_FRAME_VALID_IN       : in    std_logic;
-       FR_GET_FRAME_OUT        : out   std_logic;
-       FR_FRAME_SIZE_IN        : in    std_logic_vector(15 downto 0);
-       FR_FRAME_PROTO_IN       : in    std_logic_vector(15 downto 0);
-       FR_IP_PROTOCOL_IN       : in    std_logic_vector(7 downto 0);
-       
-       FR_SRC_MAC_ADDRESS_IN   : in    std_logic_vector(47 downto 0);
-       FR_DEST_MAC_ADDRESS_IN  : in    std_logic_vector(47 downto 0);
-       FR_SRC_IP_ADDRESS_IN    : in    std_logic_vector(31 downto 0);
-       FR_DEST_IP_ADDRESS_IN   : in    std_logic_vector(31 downto 0);
-       FR_SRC_UDP_PORT_IN      : in    std_logic_vector(15 downto 0);
-       FR_DEST_UDP_PORT_IN     : in    std_logic_vector(15 downto 0);
-
-
--- signals to/from main controller
-       RC_RD_EN_IN             : in    std_logic;
-       RC_Q_OUT                : out   std_logic_vector(8 downto 0);
-       RC_FRAME_WAITING_OUT    : out   std_logic;
-       RC_LOADING_DONE_IN      : in    std_logic;
-       RC_FRAME_SIZE_OUT       : out   std_logic_vector(15 downto 0);
-       RC_FRAME_PROTO_OUT      : out   std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
-       RC_SRC_MAC_ADDRESS_OUT  : out   std_logic_vector(47 downto 0);
-       RC_DEST_MAC_ADDRESS_OUT : out   std_logic_vector(47 downto 0);
-       RC_SRC_IP_ADDRESS_OUT   : out   std_logic_vector(31 downto 0);
-       RC_DEST_IP_ADDRESS_OUT  : out   std_logic_vector(31 downto 0);
-       RC_SRC_UDP_PORT_OUT     : out   std_logic_vector(15 downto 0);
-       RC_DEST_UDP_PORT_OUT    : out   std_logic_vector(15 downto 0);
-
--- statistics
-       FRAMES_RECEIVED_OUT     : out   std_logic_vector(31 downto 0);
-       BYTES_RECEIVED_OUT      : out   std_logic_vector(31 downto 0);
-
-       DEBUG_OUT               : out   std_logic_vector(63 downto 0)
+  RC_DATA_IN               : in  std_logic_vector(8 downto 0);
+  FR_RD_EN_OUT             : out std_logic;
+  FR_FRAME_VALID_IN        : in  std_logic;
+  FR_GET_FRAME_OUT         : out std_logic;
+  FR_FRAME_SIZE_IN         : in  std_logic_vector(15 downto 0);
+  FR_FRAME_PROTO_IN        : in  std_logic_vector(15 downto 0);
+  FR_IP_PROTOCOL_IN        : in  std_logic_vector(7 downto 0);
+  
+  FR_SRC_MAC_ADDRESS_IN    : in  std_logic_vector(47 downto 0);
+  FR_DEST_MAC_ADDRESS_IN   : in  std_logic_vector(47 downto 0);
+  FR_SRC_IP_ADDRESS_IN     : in  std_logic_vector(31 downto 0);
+  FR_DEST_IP_ADDRESS_IN    : in  std_logic_vector(31 downto 0);
+  FR_SRC_UDP_PORT_IN       : in  std_logic_vector(15 downto 0);
+  FR_DEST_UDP_PORT_IN      : in  std_logic_vector(15 downto 0);
+  -- signals to/from main controller
+  RC_RD_EN_IN              : in  std_logic;
+  RC_Q_OUT                 : out std_logic_vector(8 downto 0);
+  RC_FRAME_WAITING_OUT     : out std_logic;
+  RC_LOADING_DONE_IN       : in  std_logic;
+  RC_FRAME_SIZE_OUT        : out std_logic_vector(15 downto 0);
+  RC_FRAME_PROTO_OUT       : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+  RC_SRC_MAC_ADDRESS_OUT   : out std_logic_vector(47 downto 0);
+  RC_DEST_MAC_ADDRESS_OUT  : out std_logic_vector(47 downto 0);
+  RC_SRC_IP_ADDRESS_OUT    : out std_logic_vector(31 downto 0);
+  RC_DEST_IP_ADDRESS_OUT   : out std_logic_vector(31 downto 0);
+  RC_SRC_UDP_PORT_OUT      : out std_logic_vector(15 downto 0);
+  RC_DEST_UDP_PORT_OUT     : out std_logic_vector(15 downto 0);
+  -- statistics
+  FRAMES_RECEIVED_OUT      : out std_logic_vector(31 downto 0);
+  BYTES_RECEIVED_OUT       : out std_logic_vector(31 downto 0);
+  --
+  DEBUG_OUT                : out std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_receive_control;
 
 
 architecture trb_net16_gbe_receive_control of trb_net16_gbe_receive_control is
 
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group";
 attribute syn_encoding : string;
 
 type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
@@ -97,16 +89,16 @@ RC_DEST_IP_ADDRESS_OUT  <= FR_DEST_IP_ADDRESS_IN;
 RC_SRC_UDP_PORT_OUT     <= FR_SRC_UDP_PORT_IN;
 RC_DEST_UDP_PORT_OUT    <= FR_DEST_UDP_PORT_IN;
 
-protocol_prioritizer : trb_net16_gbe_protocol_prioritizer
+protocol_prioritizer: trb_net16_gbe_protocol_prioritizer
 port map(
-       CLK                             => CLK,
-       RESET                       => reset_prioritizer,
-       
-       FRAME_TYPE_IN           => FR_FRAME_PROTO_IN,
-       PROTOCOL_CODE_IN        => FR_IP_PROTOCOL_IN,
-       UDP_PROTOCOL_IN         => FR_DEST_UDP_PORT_IN,
-       
-       CODE_OUT                    => proto_code
+  CLK              => CLK,
+  RESET            => reset_prioritizer,
+  --
+  FRAME_TYPE_IN    => FR_FRAME_PROTO_IN,
+  PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
+  UDP_PROTOCOL_IN  => FR_DEST_UDP_PORT_IN,
+  --
+  CODE_OUT         => proto_code
 );
 
 reset_prioritizer <= '1' when load_current_state = IDLE else '0';
@@ -114,35 +106,32 @@ reset_prioritizer <= '1' when load_current_state = IDLE else '0';
 --RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0');
 RC_FRAME_PROTO_OUT <= proto_code;  -- no more ones as the incorrect value, last slot for Trash
 
---DEBUG_OUT(3 downto 0)   <= state;
---DEBUG_OUT(11 downto 4)  <= frames_received_ctr(7 downto 0);
---DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
---DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
-
-LOAD_MACHINE_PROC : process(RESET, CLK)
+LOAD_MACHINE_PROC: process( CLK )
 begin
-       if RESET = '1' then
-               load_current_state <= IDLE;
-  elsif rising_edge(CLK) then
+  if( rising_edge(CLK) ) then
+    if( RESET = '1' ) then
+      load_current_state <= IDLE;
+    else
       load_current_state <= load_next_state;
+    end if;
   end if;
 end process LOAD_MACHINE_PROC;
 
-LOAD_MACHINE : process(load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN)
+LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN )
 begin
   case load_current_state is
 
     when IDLE =>
       state <= x"1";
-      if (frames_readout_ctr /= frames_received_ctr) then -- frame is still waiting in frame_receiver
-       load_next_state <= PREPARE;
+      if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver
+        load_next_state <= PREPARE;
       else
-       load_next_state <= IDLE;
+        load_next_state <= IDLE;
       end if;
 
     when PREPARE =>  -- prepare frame size
       state <= x"2";
-      load_next_state <= WAIT_ONE; --READY;
+      load_next_state <= WAIT_ONE;
       
     when WAIT_ONE =>
        load_next_state <= READY;
@@ -150,106 +139,85 @@ begin
     when READY => -- wait for reading out the whole frame
       state <= x"3";
       if (RC_LOADING_DONE_IN = '1') then
-       load_next_state <= IDLE;
+        load_next_state <= IDLE;
       else
-       load_next_state <= READY;
+        load_next_state <= READY;
       end if;
 
   end case;
 end process LOAD_MACHINE;
 
-process(CLK)
+process( CLK )
 begin
-       if rising_edge(CLK) then
-               if (load_current_state = PREPARE) then
-                       FR_GET_FRAME_OUT <= '1';
-               else
-                       FR_GET_FRAME_OUT <= '0';
-               end if;
-               
-               if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then
-                       RC_FRAME_WAITING_OUT <= '1';
-               else
-                       RC_FRAME_WAITING_OUT <= '0';
-               end if;
-               
-               --RC_FRAME_WAITING_OUT <= frame_waiting;
-       end if;
-end process;
-
---FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
---               else '0';
---
---RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
---                   else '0';
+  if( rising_edge(CLK) ) then
+    if( load_current_state = PREPARE ) then
+      FR_GET_FRAME_OUT <= '1';
+    else
+      FR_GET_FRAME_OUT <= '0';
+    end if;
 
---SYNC_PROC : process(CLK)
---begin
---  if rising_edge(CLK) then
---    FRAMES_RECEIVED_OUT              <= frames_received_ctr;
---    --BYTES_RECEIVED_OUT               <= bytes_rec_ctr;
---    BYTES_RECEIVED_OUT(15 downto 0)  <= bytes_rec_ctr(15 downto 0);
---    BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
---    BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
---  end if;
---end process SYNC_PROC;
+    if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then
+      RC_FRAME_WAITING_OUT <= '1';
+    else
+      RC_FRAME_WAITING_OUT <= '0';
+    end if;
+  end if;
+end process;
 
-FRAMES_REC_CTR_PROC : process(RESET, CLK)
+FRAMES_REC_CTR_PROC: process( CLK )
 begin
-  if (RESET = '1') then
+  if( rising_edge(CLK) ) then
+    if   ( RESET = '1' ) then
       frames_received_ctr <= (others => '0');
-  elsif rising_edge(CLK) then
-    if (FR_FRAME_VALID_IN = '1') then
-       frames_received_ctr <= frames_received_ctr + x"1";
+    elsif( FR_FRAME_VALID_IN = '1' ) then
+      frames_received_ctr <= frames_received_ctr + x"1";
     else
-       frames_received_ctr <= frames_received_ctr;
+      frames_received_ctr <= frames_received_ctr;
     end if;
   end if;
 end process FRAMES_REC_CTR_PROC;
 
-FRAMES_READOUT_CTR_PROC : process(RESET, CLK)
+FRAMES_READOUT_CTR_PROC: process( CLK )
 begin
-  if (RESET = '1') then
+  if( rising_edge(CLK) ) then
+    if   ( RESET = '1' ) then
       frames_readout_ctr <= (others => '0');
-  elsif rising_edge(CLK) then
-    if (RC_LOADING_DONE_IN = '1') then
-       frames_readout_ctr <= frames_readout_ctr + x"1";
+    elsif( RC_LOADING_DONE_IN = '1' ) then
+      frames_readout_ctr <= frames_readout_ctr + x"1";
     else
-       frames_readout_ctr <= frames_readout_ctr;
+      frames_readout_ctr <= frames_readout_ctr;
     end if;    
   end if;
 end process FRAMES_READOUT_CTR_PROC;
 
 -- debug only
-BYTES_REC_CTR_PROC : process(RESET, CLK)
+BYTES_REC_CTR_PROC : process( CLK )
 begin
-    if (RESET = '1') then
+  if( rising_edge(CLK) ) then
+    if   ( RESET = '1' ) then
       bytes_rec_ctr <= (others => '0');
-  elsif rising_edge(CLK) then
-    if (FR_FRAME_VALID_IN = '1') then
-       bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN;    
+    elsif( FR_FRAME_VALID_IN = '1' ) then
+      bytes_rec_ctr <= bytes_rec_ctr + FR_FRAME_SIZE_IN;    
     else
-       bytes_rec_ctr <= bytes_rec_ctr;
+      bytes_rec_ctr <= bytes_rec_ctr;
     end if;
   end if;
 end process BYTES_REC_CTR_PROC;
 
-SAVED_PROTO_PROC : process(CLK)
+SAVED_PROTO_PROC : process( CLK )
 begin
-       if rising_edge(CLK) then
-               if (load_current_state = READY) then
-                       if (and_all(proto_code) = '0') then
-                               saved_proto <= proto_code;
-                       else
-                               saved_proto <= (others => '0');
-                       end if;
-               else
-                       saved_proto <= saved_proto;
-               end if;
-       end if;
+  if( rising_edge(CLK) ) then
+    if (load_current_state = READY) then
+      if( and_all(proto_code) = '0' ) then
+        saved_proto <= proto_code;
+      else
+        saved_proto <= (others => '0');
+      end if;
+    else
+      saved_proto <= saved_proto;
+    end if;
+  end if;
 end process SAVED_PROTO_PROC;
--- end of debug
-
 
 end trb_net16_gbe_receive_control;
 

diff --git a/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
index c97deba9da0d24024e81f3c721fdbff27c0bf758..c292afedf6d4171c732dbc14860900801d555036 100644 (file)
--- a/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
+++ b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
@@ -96,7 +96,7 @@ entity gbe_wrapper_fifo is
     MAKE_RESET_OUT            : out std_logic;
     --                        
     STATUS_OUT                : out std_logic_vector(15 downto 0);
-    DEBUG_OUT                 : out std_logic_vector(127 downto 0)
+    DEBUG_OUT                 : out std_logic_vector(31 downto 0)
   );
 end entity gbe_wrapper_fifo;
 
@@ -262,7 +262,7 @@ begin
 
   -- debug(127 downto 64) are local
   -- debug(63 downto 0) are media interface
-  DEBUG_OUT <= debug;
+  --DEBUG_OUT <= debug;
 
   mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
 
@@ -391,7 +391,8 @@ begin
     MONITOR_TX_PACKETS_OUT   => monitor_tx_packets,
     MONITOR_DROPPED_OUT      => monitor_dropped,
     MONITOR_GEN_DBG_OUT      => monitor_gen_dbg,
-    MAKE_RESET_OUT           => make_reset0
+    MAKE_RESET_OUT           => make_reset0,
+    DEBUG_OUT                => DEBUG_OUT
   );
 
   BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_125_IN);