-
-#LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB";
+# locate the PCS blocks
LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
-LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
+# locate the media interfaces inside fabric
+REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB
+REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC
+LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT";
+
BLOCK PATH FROM CELL THE_TDC/calibration_o*;
BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*;
BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0];
-# REGION "MEDIA_GBE" "R89C2" 25 53;
-REGION "MEDIA_C" "R102C128" 13 40;
-REGION "MEDIA_B" "R102C55" 13 40;
-REGION "MEDIA_DOWN1" "R102C20D" 13 120;
-LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
-LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ;
-LOCATE UGROUP "gen_PCSB_ADDON.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
-
FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz;
bussci1_tx.data <= (others => '0');
bussci1_tx.ack <= '0';
bussci1_tx.nack <= '0';
- bussci1_tx.unknown <= '1';
-
+ bussci1_tx.unknown <= bussci1_rx.read or bussci1_rx.write when rising_edge(clk_sys);
+
---------------------------------------------------------------------------
-- PCSB Downlink without backplane is SFP
---------------------------------------------------------------------------
gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
-
THE_MEDIA_PCSB : entity med_ecp3_sfp_sync_all_RS
generic map(
IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER),
---------------------------------------------------------------------------
-- PCSC 4 downlinks
---------------------------------------------------------------------------
- bussci3_tx.data <= (others => '0');
- bussci3_tx.ack <= '0';
- bussci3_tx.nack <= '0';
- bussci3_tx.unknown <= '1';
---gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate
--- THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
--- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(2),
--- MEDIA_MED2INT(1) => med2int(3),
--- MEDIA_MED2INT(2) => med2int(0),
--- MEDIA_MED2INT(3) => med2int(1),
--- MEDIA_INT2MED(0) => int2med(2),
--- MEDIA_INT2MED(1) => int2med(3),
--- MEDIA_INT2MED(2) => int2med(0),
--- MEDIA_INT2MED(3) => int2med(1),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => HUB_MOD0(3),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(4),
--- SD_PRSNT_N_IN(2) => HUB_MOD0(1),
--- SD_PRSNT_N_IN(3) => HUB_MOD0(2),
--- SD_LOS_IN(0) => HUB_LOS(3),
--- SD_LOS_IN(1) => HUB_LOS(4),
--- SD_LOS_IN(2) => HUB_LOS(1),
--- SD_LOS_IN(3) => HUB_LOS(2),
--- SD_TXDIS_OUT(0) => HUB_TXDIS(3),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(4),
--- SD_TXDIS_OUT(2) => HUB_TXDIS(1),
--- SD_TXDIS_OUT(3) => HUB_TXDIS(2),
--- --Control Interface
--- BUS_RX => bussci3_rx,
--- BUS_TX => bussci3_tx,
--- -- Status and control port
--- STAT_DEBUG => open,
--- CTRL_DEBUG => open
--- );
---end generate;
-
---gen_PCSB_ADDON : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate
--- THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
--- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(4),
--- MEDIA_MED2INT(1) => med2int(5),
--- MEDIA_MED2INT(2) => med2int(6),
--- MEDIA_MED2INT(3) => med2int(7),
--- MEDIA_INT2MED(0) => int2med(4),
--- MEDIA_INT2MED(1) => int2med(5),
--- MEDIA_INT2MED(2) => int2med(6),
--- MEDIA_INT2MED(3) => int2med(7),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
---
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
--- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
--- SD_PRSNT_N_IN(3) => HUB_MOD0(8),
--- SD_LOS_IN(0) => HUB_LOS(5),
--- SD_LOS_IN(1) => HUB_LOS(6),
--- SD_LOS_IN(2) => HUB_LOS(7),
--- SD_LOS_IN(3) => HUB_LOS(8),
--- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
--- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
--- SD_TXDIS_OUT(3) => HUB_TXDIS(8),
--- --Control Interface
--- BUS_RX => bussci2_rx,
--- BUS_TX => bussci2_tx,
--- -- Status and control port
--- STAT_DEBUG => open,
--- CTRL_DEBUG => open
--- );
--- PCSSW <= "11100100"; --default 1:1
---end generate;
+ bussci3_tx.data <= (others => '0');
+ bussci3_tx.ack <= '0';
+ bussci3_tx.nack <= '0';
+ bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys);
---------------------------------------------------------------------------
-- GbE (PCSD)
------------------------------------------------------------------------------
--design options: backplane or front SFP, with or without GBE
- constant USE_BACKPLANE : integer := c_NO;
+ constant USE_BACKPLANE : integer := c_YES;
constant INCLUDE_GBE : integer := c_NO;
--We want an ECP3
-- port MII: SCTRL channel on uplink to CTS
-- port MII+1: SCTRL channel from GbE interface
+--With no GbE:
+-- for MII_NUMBER=5 (4 downlinks, 1 uplink):
+-- port 0,1,2,3: downlinks to other FPGA
+-- port 4: uplink
+-- port 5: internal endpoint on SCTRL
+
+
type hub_mii_t is array(0 to 3) of integer;
type hub_ct is array(0 to 16) of integer;
type hub_cfg_t is array(0 to 3) of hub_ct;
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.12',
synplify_path => '/opt/synplicity/R-2020.09-SP1',
-synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp",
+synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier",
nodelist_file => 'nodelist.txt',
#pinout_file => '',
par_options => '../par.p2t',
+#mapper_options => '-u -retime -split_node',
include_TDC => 0,
include_GBE => 0,
-LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ;
-LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ;
+# locate the PCS blocks
+LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST" SITE "PCSA";
+LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
+LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD";
LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
-#REGION "MEDIA_DOWN1" "R102C20D" 13 120;
-#LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ;
-
-REGION "MEDIA_LEFT" "R102C17D" 13 75;
-REGION "MEDIA_RIGHT" "R102C92D" 13 75;
-LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_RIGHT" ;
-LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT" ;
-LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT" ;
-LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_RIGHT" ;
-LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_LEFT" ;
+# locate the media interfaces inside fabric
+REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB
+REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC
+LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_RIGHT";
+LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT";
+LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT";
+LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_RIGHT";
+LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_LEFT";
+
+# primary nets
+USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]";
+USE PRIMARY NET "THE_MEDIA_4_PCSC/clk_rx_full[0]";
+USE PRIMARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[0]";
+
+# secondary nets
+USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[1]";
+USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[2]";
+USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[3]";
+USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[1]";
+USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[2]";
+USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[3]";
+USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]";
+
+################################
FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz;
FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz;
BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i";
-
MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns;
-
-
-
-# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ;
-# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ;
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
-# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
-- PCSA Uplink when backplane is used
---------------------------------------------------------------------------
gen_PCSA : if USE_BACKPLANE = c_YES generate
--- THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync
--- generic map(
--- SERDES_NUM => 0,
--- IS_SYNC_SLAVE => c_YES
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT => med2int(INTERFACE_NUM-1), --10 or 8
--- MEDIA_INT2MED => int2med(INTERFACE_NUM-1),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN => BACK_GPIO(1),
--- SD_LOS_IN => BACK_GPIO(1),
--- SD_TXDIS_OUT => BACK_GPIO(0),
--- --Control Interface
--- BUS_RX => bussci1_rx,
--- BUS_TX => bussci1_tx,
--- -- Status and control port
--- STAT_DEBUG => med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
+ THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS
+ generic map(
+ IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED),
+ IS_WAP_ZERO => 1
+ )
+ port map(
+ -- Clocks and reset
+ CLK_REF_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ -- Media Interface TX/RX
+ MEDIA_MED2INT(0) => med2int(INTERFACE_NUM-1),
+ MEDIA_MED2INT(1) => open,
+ MEDIA_MED2INT(2) => open,
+ MEDIA_MED2INT(3) => open,
+ MEDIA_INT2MED(0) => int2med(INTERFACE_NUM-1),
+ MEDIA_INT2MED(1) => open,
+ MEDIA_INT2MED(2) => open,
+ MEDIA_INT2MED(3) => open,
+ -- komma operation
+ RX_DLM_OUT(0) => rx_dlm_i,
+ RX_DLM_OUT(1) => open,
+ RX_DLM_OUT(2) => open,
+ RX_DLM_OUT(3) => open,
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => x"00",
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
+ -- sync operation
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => master_clk_i,
+ QUAD_RST_IN => global_reset_i,
+ GLOBAL_RESET_OUT => global_reset_i,
+ SLAVE_ACTIVE_OUT => slave_active_i,
+ SLAVE_ACTIVE_IN => slave_active_i,
+ TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0",
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => BACK_GPIO(1),
+ SD_PRSNT_N_IN(1) => '1',
+ SD_PRSNT_N_IN(2) => '1',
+ SD_PRSNT_N_IN(3) => '1',
+ SD_LOS_IN(0) => BACK_GPIO(1),
+ SD_LOS_IN(1) => '1',
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+ SD_TXDIS_OUT(0) => BACK_GPIO(0),
+ SD_TXDIS_OUT(1) => open,
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
+ --Control Interface
+ BUS_RX => bussci1_rx,
+ BUS_TX => bussci1_tx,
+ -- Status and control port
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
+ );
end generate;
---------------------------------------------------------------------------
-- PCSB Uplink without backplane and 3/4 downlinks
---------------------------------------------------------------------------
gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate
--- THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4
--- generic map(
--- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
--- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
--- )
--- port map(
--- CLK_REF_FULL => clk_full_osc,
--- CLK_INTERNAL_FULL => clk_full_osc,
--- SYSCLK => clk_sys,
--- RESET => reset_i,
--- CLEAR => clear_i,
--- --Internal Connection
--- MEDIA_MED2INT(0) => med2int(4),
--- MEDIA_MED2INT(1) => med2int(5),
--- MEDIA_MED2INT(2) => med2int(6),
--- MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
--- MEDIA_INT2MED(0) => int2med(4),
--- MEDIA_INT2MED(1) => int2med(5),
--- MEDIA_INT2MED(2) => int2med(6),
--- MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
--- --Sync operation
--- RX_DLM => open,
--- RX_DLM_WORD => open,
--- TX_DLM => open,
--- TX_DLM_WORD => open,
--- --SFP Connection
--- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
--- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
--- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
--- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
--- SD_LOS_IN(0) => HUB_LOS(5),
--- SD_LOS_IN(1) => HUB_LOS(6),
--- SD_LOS_IN(2) => HUB_LOS(7),
--- SD_LOS_IN(3) => SFP_LOS(1),
--- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
--- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
--- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
--- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--- --Control Interface
--- BUS_RX => bussci2_rx,
--- BUS_TX => bussci2_tx,
--- -- Status and control port
--- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
--- CTRL_DEBUG => open
--- );
+ THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS
+ generic map(
+ IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
+ IS_WAP_ZERO => 1
+ )
+ port map(
+ -- Clocks and reset
+ CLK_REF_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ -- Media Interface TX/RX
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(5),
+ MEDIA_MED2INT(2) => med2int(6),
+ MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(5),
+ MEDIA_INT2MED(2) => int2med(6),
+ MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
+ -- komma operation
+ RX_DLM_OUT(0) => open,
+ RX_DLM_OUT(1) => open,
+ RX_DLM_OUT(2) => open,
+ RX_DLM_OUT(3) => open,
+ RX_DLM_WORD_OUT => open,
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => x"00",
+ RX_RST_OUT => open,
+ RX_RST_WORD_OUT => open,
+ TX_RST_IN => '0',
+ TX_RST_WORD_IN => x"00",
+ -- sync operation
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => open,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => open,
+ QUAD_RST_IN => global_reset_i,
+ GLOBAL_RESET_OUT => open,
+ SLAVE_ACTIVE_OUT => open,
+ SLAVE_ACTIVE_IN => slave_active_i,
+ TX_PLL_LOL_IN => tx_pll_lol_all_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
+ TX_CLK_AVAIL_OUT => open,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => x"0",
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+ SD_PRSNT_N_IN(1) => HUB_MOD0(6),
+ SD_PRSNT_N_IN(2) => HUB_MOD0(7),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => HUB_LOS(6),
+ SD_LOS_IN(2) => HUB_LOS(7),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ --Control Interface
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
+ -- Status and control port
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => open
+ );
end generate;
gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate
TX_PLL_LOL_OUT => tx_pll_lol_all_i,
TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
- SYNC_TX_QUAD_OUT => open, --sync_tx_quad_i,
+ SYNC_TX_QUAD_OUT => sync_tx_quad_i,
LINK_TX_READY_OUT => link_tx_ready_i,
STATE_OUT => tx_reset_state
);
- sync_tx_quad_i <= '1';
+-- sync_tx_quad_i <= '1';
---------------------------------------------------------------------------
-- PCSC 4 downlinks
GSC_REPLY_READ_OUT => gsc_reply_read,
GSC_BUSY_IN => gsc_busy,
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
-
+ BUS_IP_RX => busgbeip_rx,
+ BUS_IP_TX => busgbeip_tx,
+ BUS_REG_RX => busgbereg_rx,
+ BUS_REG_TX => busgbereg_tx,
+
MAKE_RESET_OUT => reset_via_gbe,
DEBUG_OUT => open
-# MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full_osc" 1 X ;
-# MULTICYCLE FROM CLKNET "clk_full_osc" TO CLKNET "clk_sys" 2 X ;
+# locate the PCS blocks
+LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB";
+
+# locate the media interfaces inside fabric
+REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB
+REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_LEFT";
MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x;
jspc29 / trb3sc.git / commitdiff