updated fifo, Jan

diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd
index bda4d5f92e5c3becd483320cd8f53c8217451f96..582182cfd89e96a7cd7fa68c132046410a30dd95 100644 (file)
--- a/trb_net_fifo.vhd
+++ b/trb_net_fifo.vhd
@@ -13,12 +13,13 @@ USE ieee.std_logic_arith.ALL;
 entity trb_net_fifo is
   
   generic (WIDTH : integer := 18;      -- FIFO word width
-           DEPTH : integer := 3);     -- Depth of the FIFO, 2^(n+1)
+           DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
+           FORCE_LUT : integer range 0 to 1 := 0): --don't allow use of BlockRAM
 
   port (CLK    : in std_logic;                 
         RESET  : in std_logic;         
         CLK_EN : in std_logic;
-        
+
         DATA_IN         : in  std_logic_vector(WIDTH - 1 downto 0);  -- Input data
         WRITE_ENABLE_IN : in  std_logic;               
         DATA_OUT        : out std_logic_vector(WIDTH - 1 downto 0);  -- Output data

diff --git a/xilinx/trb_net_fifo_arch.vhd b/xilinx/trb_net_fifo_arch.vhd
index 6535ba8831439d3211348cf5bf786f3e31456885..47a9b6b19c756ef63105f2f9123e3bfebe04af55 100644 (file)
--- a/xilinx/trb_net_fifo_arch.vhd
+++ b/xilinx/trb_net_fifo_arch.vhd
@@ -50,7 +50,7 @@ architecture arch_trb_net_fifo of trb_net_fifo is
 
 begin
 
-  gen_shiftreg : if DEPTH /= 6 or WIDTH /= 18 generate
+  gen_shiftreg : if DEPTH /= 6 or WIDTH /= 18 or FORCE_LUT = 1 generate
   
     FULL_OUT  <= current_FULL;
     EMPTY_OUT <= current_EMPTY;
@@ -176,7 +176,7 @@ begin
 
 
 
-  gen_BRAM : if DEPTH = 6 and WIDTH = 18 generate
+  gen_BRAM : if (DEPTH = 6 and WIDTH = 18) and FORCE_LUT = 0 generate
    bram_fifo:trb_net16_bram_fifo
     port map (
       clock_in         => CLK,