<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 22:15:00.057" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_adc_clk" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 07 15:14:45.597" version="5.3" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_adc_clk.lpc" type="lpc" modified="2013 10 02 22:14:51.000"/>
- <File name="pll_adc_clk.vhd" type="top_level_vhdl" modified="2013 10 02 22:14:51.000"/>
- <File name="pll_adc_clk_tmpl.vhd" type="template_vhdl" modified="2013 10 02 22:14:51.000"/>
+ <File name="pll_adc_clk.lpc" type="lpc" modified="2014 04 07 15:14:44.000"/>
+ <File name="pll_adc_clk.vhd" type="top_level_vhdl" modified="2014 04 07 15:14:44.000"/>
+ <File name="pll_adc_clk_tmpl.vhd" type="template_vhdl" modified="2014 04 07 15:14:44.000"/>
</Package>
</DiamondModule>
ModuleName=pll_adc_clk
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=10/02/2013
-Time=22:14:51
+Date=04/07/2014
+Time=15:14:44
[Parameters]
Verilog=0
OK_Tol=0.0
KFrq=
ClkRst=0
-PCDR=0
+PCDR=1
FINDELA=0
VcoRate=
Bandwidth=1.826303
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 187.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 187.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e
--- Wed Oct 2 22:14:51 2013
+-- Mon Apr 7 15:14:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
entity pll_adc_clk is
port (
CLK: in std_logic;
+ RESET: in std_logic;
CLKOP: out std_logic;
LOCK: out std_logic);
attribute dont_touch : boolean;
PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 15, CLKI_DIV=> 16,
FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo,
+ WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo,
+ DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo,
+ DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo,
+ FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo,
+ FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
+ CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
CLKOP <= CLKOP_t;
end Structure;
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 20 03:05:03.937" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 07 15:14:26.931" version="5.3" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 10 20 03:05:02.000"/>
- <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 10 20 03:05:02.000"/>
- <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 10 20 03:05:02.000"/>
+ <File name="pll_nx_clk250.lpc" type="lpc" modified="2014 04 07 15:14:25.000"/>
+ <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2014 04 07 15:14:25.000"/>
+ <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2014 04 07 15:14:25.000"/>
</Package>
</DiamondModule>
ModuleName=pll_nx_clk250
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=10/20/2013
-Time=03:05:02
+Date=04/07/2014
+Time=15:14:25
[Parameters]
Verilog=0
OK_Tol=0.0
KFrq=125.000000
ClkRst=0
-PCDR=0
+PCDR=1
FINDELA=0
VcoRate=
Bandwidth=1.753251
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw -e
--- Sun Oct 20 03:05:02 2013
+-- Mon Apr 7 15:14:25 2014
library IEEE;
use IEEE.std_logic_1164.all;
entity pll_nx_clk250 is
port (
CLK: in std_logic;
+ RESET: in std_logic;
CLKOP: out std_logic;
CLKOK: out std_logic;
LOCK: out std_logic);
PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 4,
FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo,
+ WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo,
+ DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo,
+ DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo,
+ FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo,
+ FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>CLKOK,
+ CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open);
CLKOP <= CLKOP_t;
end Structure;
signal adc0_frame_notlocked : std_logic;
signal adc0_frame_notlocked_p : std_logic;
signal adc0_notlock_ctr : unsigned(7 downto 0);
- signal adc0_bit_shift : unsigned(1 downto 0);
- signal adc0_bit_shift_last : unsigned(1 downto 0);
- signal adc0_bit_shift_change : std_logic;
signal adc1_frame_notlocked : std_logic;
signal adc1_frame_notlocked_p : std_logic;
signal adc1_notlock_ctr : unsigned(7 downto 0);
- signal adc1_bit_shift : unsigned(1 downto 0);
- signal adc1_bit_shift_last : unsigned(1 downto 0);
- signal adc1_bit_shift_change : std_logic;
-- Merge Data
type q_map_t is array(0 to 4) of std_logic_vector(3 downto 0);
signal adc0_data_buf : adc_data_buf_t;
signal adc0_frame_ctr : unsigned(2 downto 0);
+ signal adc0_frame_ctr_last : unsigned(2 downto 0);
+ signal adc0_bit_shift : unsigned(1 downto 0);
+ signal adc0_bit_shift_last : unsigned(1 downto 0);
+ signal adc0_ctr_error : std_logic;
+ signal adc0_shift_error : std_logic;
+ signal adc0_error_status : std_logic_vector(15 downto 0);
signal adc0_frame_locked : std_logic;
-
+
signal adc0_new_data_t : std_logic;
signal adc0_data_t : adc_data_t;
signal adc1_data_buf : adc_data_buf_t;
signal adc1_frame_ctr : unsigned(2 downto 0);
+ signal adc1_frame_ctr_last : unsigned(2 downto 0);
+ signal adc1_bit_shift : unsigned(1 downto 0);
+ signal adc1_bit_shift_last : unsigned(1 downto 0);
+ signal adc1_ctr_error : std_logic;
+ signal adc1_shift_error : std_logic;
+ signal adc1_error_status : std_logic_vector(15 downto 0);
signal adc1_frame_locked : std_logic;
signal adc1_new_data_t : std_logic;
-- DEBUG
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= DDR_DATA_CLK;
- DEBUG_OUT(2) <= adc0_bit_shift_change;
- DEBUG_OUT(3) <= adc0_write_enable;
- DEBUG_OUT(4) <= adc0_fifo_full;
- DEBUG_OUT(5) <= adc0_fifo_empty;
- DEBUG_OUT(6) <= adc0_frame_locked;
- DEBUG_OUT(7) <= adc0_new_data_t;
- DEBUG_OUT(8) <= adc0_read_enable;
- DEBUG_OUT(9) <= adc0_read_enable_t;
- DEBUG_OUT(10) <= adc0_read_enable_tt;
- DEBUG_OUT(11) <= adc0_data_valid_o;
- DEBUG_OUT(15 downto 12) <= (others => '0');
-
+ DEBUG_OUT(2) <= adc0_write_enable;
+ DEBUG_OUT(3) <= adc0_fifo_full;
+ DEBUG_OUT(4) <= adc0_fifo_empty;
+ DEBUG_OUT(5) <= adc0_new_data_t;
+ DEBUG_OUT(6) <= adc0_read_enable;
+ DEBUG_OUT(7) <= adc0_read_enable_t;
+ DEBUG_OUT(8) <= adc0_read_enable_tt;
+ DEBUG_OUT(9) <= adc0_data_valid_o;
+ DEBUG_OUT(10) <= adc0_ctr_error;
+ DEBUG_OUT(11) <= adc0_shift_error;
+ DEBUG_OUT(12) <= adc0_frame_locked;
+ DEBUG_OUT(13) <= adc0_frame_notlocked;
+ DEBUG_OUT(14) <= adc0_frame_notlocked_p;
+ DEBUG_OUT(15) <= error_adc0_o;
+
when x"1" =>
DEBUG_OUT <= adc0_data_buf(0);
when x"5" =>
DEBUG_OUT <= adc0_data_buf(4);
- --when x"e" =>
- -- DEBUG_OUT <= q_0(15 downto 0);
-
- --when x"f" =>
- -- DEBUG_OUT <= q_1(15 downto 0);
-
when others =>
DEBUG_OUT <= (others => '0');
+
end case;
end process PROC_DEBUG;
-----------------------------------------------------------------------------
PROC_MERGE_DATA0: process(DDR_DATA_CLK)
- variable q_0_map : q_map_t;
+ variable q_0_map : q_map_t;
begin
if (rising_edge(DDR_DATA_CLK)) then
- -- Remap DDR Output q_value
- for I in 0 to 4 loop
- q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15);
- end loop;
-
- for I in 0 to 4 loop
- adc0_data_buf(I)(3 downto 0) <= q_0_map(I);
- adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0);
- end loop;
-
if (RESET_DDR_DATA_CLK = '1') then
adc0_new_data_t <= '0';
adc0_frame_ctr <= (others => '0');
- adc0_frame_locked <= '0';
+ adc0_frame_ctr_last <= (others => '0');
adc0_bit_shift <= "00";
adc0_bit_shift_last <= "00";
- adc0_bit_shift_change <= '0';
+ adc0_ctr_error <= '0';
+ adc0_shift_error <= '0';
+ adc0_error_status <= (others => '0');
+ adc0_frame_locked <= '0';
+
+ for I in 0 to 3 loop
+ adc0_data_t(I) <= (others => '0');
+ end loop;
+
else
+ adc0_shift_error <= '0';
+ adc0_frame_locked <= '0';
+
+ -- Remap DDR Output q_value
+ for I in 0 to 4 loop
+ q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15);
+ end loop;
+
+ -- Buffer new incoming Data
+ for I in 0 to 4 loop
+ adc0_data_buf(I)(3 downto 0) <= q_0_map(I);
+ adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0);
+ end loop;
+
-- Test Frame Clock Pattern
- adc0_new_data_t <= '0';
- case adc0_data_buf(4) is -- adc0_data_buf(4) is frame clock
+ case adc0_data_buf(4) is -- q_0_map(4) is THE Frame Clock
when "0000111111000000" =>
for I in 0 to 3 loop
adc0_data_t(I) <= adc0_data_buf(I)(11 downto 0);
end loop;
adc0_new_data_t <= '1';
adc0_bit_shift <= "00";
+ adc0_frame_ctr <= (others => '0');
when "0001111110000001" =>
for I in 0 to 3 loop
end loop;
adc0_new_data_t <= '1';
adc0_bit_shift <= "01";
-
+ adc0_frame_ctr <= (others => '0');
+
when "0011111100000011" =>
for I in 0 to 3 loop
adc0_data_t(I) <= adc0_data_buf(I)(13 downto 2);
end loop;
adc0_new_data_t <= '1';
adc0_bit_shift <= "10";
-
+ adc0_frame_ctr <= (others => '0');
+
when "0111111000000111" =>
for I in 0 to 3 loop
adc0_data_t(I) <= adc0_data_buf(I)(14 downto 3);
end loop;
adc0_new_data_t <= '1';
adc0_bit_shift <= "11";
-
- when others => null;
+ adc0_frame_ctr <= (others => '0');
+ when others =>
+ for I in 0 to 3 loop
+ adc0_data_t(I) <= (others => '0');
+ end loop;
+ adc0_new_data_t <= '0';
+ adc0_frame_ctr <= adc0_frame_ctr + 1;
end case;
- -- ADC Lock Status
+ -- Monitor ADC Lock Status
+ adc0_frame_ctr_last <= adc0_frame_ctr;
if (adc0_new_data_t = '1') then
- adc0_frame_ctr <= (others => '0');
- adc0_frame_locked <= '1';
- elsif (adc0_frame_ctr < x"4") then
- adc0_frame_ctr <= adc0_frame_ctr + 1;
- else
- adc0_frame_locked <= '0';
+ if (adc0_frame_ctr_last /= x"2") then
+ adc0_ctr_error <= '1';
+ else
+ adc0_ctr_error <= '0';
+ end if;
end if;
- adc0_bit_shift_last <= adc0_bit_shift;
+ adc0_bit_shift_last <= adc0_bit_shift;
if (adc0_bit_shift /= adc0_bit_shift_last) then
- adc0_bit_shift_change <= '1';
+ adc0_shift_error <= '1';
+ else
+ adc0_shift_error <= '0';
+ end if;
+
+ -- Error Status
+ adc0_error_status(0) <= adc0_ctr_error or adc0_shift_error;
+ for X in 0 to 14 loop
+ adc0_error_status(X + 1) <= adc0_error_status(X);
+ end loop;
+
+ if (adc0_error_status = x"0000") then
+ adc0_frame_locked <= '1';
else
- adc0_bit_shift_change <= '0';
+ adc0_frame_locked <= '0';
end if;
end if;
variable q_1_map : q_map_t;
begin
if (rising_edge(DDR_DATA_CLK)) then
- -- Remap DDR Output q_value
- for I in 0 to 4 loop
- q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15);
- end loop;
-
- for I in 0 to 4 loop
- adc1_data_buf(I)(3 downto 0) <= q_1_map(I);
- adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0);
- end loop;
-
if (RESET_DDR_DATA_CLK = '1') then
adc1_new_data_t <= '0';
adc1_frame_ctr <= (others => '0');
- adc1_frame_locked <= '0';
+ adc1_frame_ctr_last <= (others => '0');
adc1_bit_shift <= "00";
adc1_bit_shift_last <= "00";
- adc1_bit_shift_change <= '0';
+ adc1_ctr_error <= '0';
+ adc1_shift_error <= '0';
+ adc1_error_status <= (others => '0');
+ adc1_frame_locked <= '0';
+
+ for I in 0 to 3 loop
+ adc1_data_t(I) <= (others => '0');
+ end loop;
else
+ adc1_ctr_error <= '0';
+ adc1_shift_error <= '0';
+
+ -- Remap DDR Output q_value
+ for I in 0 to 4 loop
+ q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15);
+ end loop;
+
+ -- Buffer new incoming Data
+ for I in 0 to 4 loop
+ adc1_data_buf(I)(3 downto 0) <= q_1_map(I);
+ adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0);
+ end loop;
+
-- Test Frame Clock Pattern
- adc1_new_data_t <= '0';
case adc1_data_buf(4) is -- adc1_data_buf(4) is frame clock
when "0000111111000000" =>
for I in 0 to 3 loop
end loop;
adc1_new_data_t <= '1';
adc1_bit_shift <= "00";
+ adc1_frame_ctr <= (others => '0');
when "0001111110000001" =>
for I in 0 to 3 loop
end loop;
adc1_new_data_t <= '1';
adc1_bit_shift <= "01";
+ adc1_frame_ctr <= (others => '0');
when "0011111100000011" =>
for I in 0 to 3 loop
end loop;
adc1_new_data_t <= '1';
adc1_bit_shift <= "10";
+ adc1_frame_ctr <= (others => '0');
when "0111111000000111" =>
for I in 0 to 3 loop
end loop;
adc1_new_data_t <= '1';
adc1_bit_shift <= "11";
+ adc1_frame_ctr <= (others => '0');
+
+ when others =>
+ for I in 0 to 3 loop
+ adc1_data_t(I) <= (others => '0');
+ end loop;
+ adc1_new_data_t <= '0';
+ adc1_frame_ctr <= adc1_frame_ctr + 1;
- when others => null;
-
end case;
- -- ADC Lock Status
+ -- Monitor ADC Lock Status
+ adc1_frame_ctr_last <= adc1_frame_ctr;
if (adc1_new_data_t = '1') then
- adc1_frame_ctr <= (others => '0');
- adc1_frame_locked <= '1';
- elsif (adc1_frame_ctr < x"4") then
- adc1_frame_ctr <= adc1_frame_ctr + 1;
- else
- adc1_frame_locked <= '0';
+ if (adc1_frame_ctr_last /= x"2") then
+ adc1_ctr_error <= '1';
+ else
+ adc1_ctr_error <= '0';
+ end if;
end if;
- adc1_bit_shift_last <= adc1_bit_shift;
+ adc1_bit_shift_last <= adc1_bit_shift;
if (adc1_bit_shift /= adc1_bit_shift_last) then
- adc1_bit_shift_change <= '1';
+ adc1_shift_error <= '1';
+ else
+ adc1_shift_error <= '0';
+ end if;
+
+ -- Error Status
+ adc1_error_status(0) <= adc1_ctr_error or adc1_shift_error;
+ for X in 0 to 14 loop
+ adc1_error_status(X + 1) <= adc1_error_status(X);
+ end loop;
+
+ if (adc1_error_status = x"0000") then
+ adc1_frame_locked <= '1';
else
- adc1_bit_shift_change <= '0';
+ adc1_frame_locked <= '0';
end if;
end if;
-----------------------------------------------------------------------------
-- Lock Monitor
-----------------------------------------------------------------------------
+ signal_async_trans_1: signal_async_trans
+ port map (
+ CLK_IN => CLK_IN,
+ SIGNAL_A_IN => not adc0_frame_locked,
+ SIGNAL_OUT => adc0_frame_notlocked
+ );
+ signal_async_trans_2: signal_async_trans
+ port map (
+ CLK_IN => CLK_IN,
+ SIGNAL_A_IN => not adc1_frame_locked,
+ SIGNAL_OUT => adc1_frame_notlocked
+ );
+
level_to_pulse_1: level_to_pulse
port map (
- CLK_IN => DDR_DATA_CLK,
- RESET_IN => RESET_DDR_DATA_CLK,
- LEVEL_IN => not adc0_frame_locked,
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ LEVEL_IN => adc0_frame_notlocked,
PULSE_OUT => adc0_frame_notlocked_p
);
level_to_pulse_2: level_to_pulse
port map (
- CLK_IN => DDR_DATA_CLK,
- RESET_IN => RESET_DDR_DATA_CLK,
- LEVEL_IN => not adc1_frame_locked,
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ LEVEL_IN => adc1_frame_notlocked,
PULSE_OUT => adc1_frame_notlocked_p
);
- pulse_dtrans_1: pulse_dtrans
- generic map (
- CLK_RATIO => 2
- )
- port map (
- CLK_A_IN => DDR_DATA_CLK,
- RESET_A_IN => RESET_DDR_DATA_CLK,
- PULSE_A_IN => adc0_frame_notlocked_p,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => adc0_frame_notlocked
- );
-
- pulse_dtrans_2: pulse_dtrans
- generic map (
- CLK_RATIO => 2
- )
- port map (
- CLK_A_IN => DDR_DATA_CLK,
- RESET_A_IN => RESET_DDR_DATA_CLK,
- PULSE_A_IN => adc1_frame_notlocked_p,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => adc1_frame_notlocked
- );
-
PROC_NOTLOCK_COUNTER: process(CLK_IN)
begin
if (rising_edge(CLK_IN)) then
adc0_notlock_ctr <= (others => '0');
adc1_notlock_ctr <= (others => '0');
else
- if (adc0_frame_notlocked = '1') then
+ if (adc0_frame_notlocked_p = '1') then
adc0_notlock_ctr <= adc0_notlock_ctr + 1;
end if;
- if (adc1_frame_notlocked = '1') then
+ if (adc1_frame_notlocked_p = '1') then
adc1_notlock_ctr <= adc1_notlock_ctr + 1;
end if;
end if;
error_adc0_o <= '0';
error_adc1_o <= '0';
- if (adc0_frame_notlocked = '1' or
- adc0_bit_shift_change = '1') then
+ if (adc0_frame_notlocked = '1') then
error_adc0_o <= '1';
end if;
- if (adc1_frame_notlocked = '1' or
- adc1_bit_shift_change = '1') then
+ if (adc1_frame_notlocked = '1') then
error_adc1_o <= '1';
end if;
end if;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity Gray_Decoder is
+entity gray_decoder is
generic (
WIDTH : integer range 2 to 32 := 12 -- Register Width
end entity;
-architecture Behavioral of Gray_Decoder is
+architecture Behavioral of gray_decoder is
signal binary_o : std_logic_vector(WIDTH - 1 downto 0);
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity Gray_Encoder is
+entity gray_encoder is
generic (
WIDTH : integer range 2 to 32 := 12 -- Register Width
);
end entity;
-architecture Behavioral of Gray_Encoder is
+architecture Behavioral of gray_encoder is
signal gray_o : std_logic_vector(WIDTH - 1 downto 0);
DEBUG_OUT(6) <= fifo_read_enable;
DEBUG_OUT(7) <= fifo_read_enable_t;
DEBUG_OUT(8) <= fifo_read_enable_tt;
- DEBUG_OUT(9) <= new_data_o;
- DEBUG_OUT(12 downto 10) <= NX_FRAME_IN(11 downto 9);
- DEBUG_OUT(15 downto 13) <= nx_frame_o(11 downto 9);
- --DEBUG_OUT(15 downto 13) <= fifo_data_out(11 downto 9);
+ DEBUG_OUT(15 downto 9) <= NX_FRAME_OUT(14 downto 8);
else
DEBUG_OUT <= debug_fifo;
end if;
entity nx_data_receiver is
port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- NX_DATA_CLK_TEST_IN : in std_logic;
- TRIGGER_IN : in std_logic;
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NX_DATA_CLK_TEST_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+
+ -- nXyter Ports
+ NX_TIMESTAMP_CLK_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_TIMESTAMP_RESET_OUT : out std_logic;
- -- nXyter Ports
- NX_TIMESTAMP_CLK_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
-
-- ADC Ports
- ADC_CLK_DAT_IN : in std_logic;
- ADC_FCLK_IN : in std_logic_vector(1 downto 0);
- ADC_DCLK_IN : in std_logic_vector(1 downto 0);
- ADC_SAMPLE_CLK_OUT : out std_logic;
- ADC_A_IN : in std_logic_vector(1 downto 0);
- ADC_B_IN : in std_logic_vector(1 downto 0);
- ADC_NX_IN : in std_logic_vector(1 downto 0);
- ADC_D_IN : in std_logic_vector(1 downto 0);
- ADC_SCLK_LOCK_OUT : out std_logic;
-
- -- Outputs
- NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
- ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- NEW_DATA_OUT : out std_logic;
-
- TIMESTAMP_CURRENT_IN : in unsigned(11 downto 0);
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- ERROR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ ADC_CLK_DAT_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SAMPLE_CLK_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
+ ADC_SCLK_LOCK_OUT : out std_logic;
+
+ -- Outputs
+ NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
+ ADC_DATA_OUT : out std_logic_vector(11 downto 0);
+ NEW_DATA_OUT : out std_logic;
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ ERROR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end entity;
signal rs_sync_set : std_logic;
signal rs_sync_reset : std_logic;
- -- Parity Check
- signal parity_error : std_logic;
-
-- NX Clock Active
signal nx_clk_active_ff_0 : std_logic;
signal nx_clk_active_ff_1 : std_logic;
signal rs_timeout_timer_start : std_logic;
signal rs_timeout_timer_done : std_logic;
signal rs_timeout_timer_reset : std_logic;
+ signal nx_timestamp_reset_o : std_logic;
type R_STATES is (R_IDLE,
R_SET_ALL_RESETS,
signal nx_fifo_read_enable : std_logic;
signal nx_fifo_empty : std_logic;
signal nx_read_enable : std_logic;
+ signal nx_fifo_data_valid_tt : std_logic;
signal nx_fifo_data_valid_t : std_logic;
signal nx_fifo_data_valid : std_logic;
-
+
+ signal nx_fifo_data : std_logic_vector(31 downto 0);
+
-- NX FIFO READ
type delay_array_t is array(0 to 15) of std_logic_vector(31 downto 0);
signal nx_timestamp_d : delay_array_t;
signal nx_timestamp_t : std_logic_vector(31 downto 0);
signal nx_new_timestamp : std_logic;
signal nx_new_timestamp_ctr : unsigned(3 downto 0);
- signal nx_fifo_data : std_logic_vector(31 downto 0);
+ signal nx_fifo_data_f : std_logic_vector(31 downto 0);
-- Resync Counter Process
signal resync_counter : unsigned(11 downto 0);
signal nx_clk_active : std_logic;
-- Parity Error Counter Process
+ signal parity_error : std_logic;
signal parity_error_counter : unsigned(11 downto 0);
- signal parity_error_ctr_inc : std_logic;
signal reg_nx_frame_synced : std_logic;
signal adc_debug_type : std_logic_vector(3 downto 0);
-- Data Output Handler
- type STATES is (IDLE,
- WAIT_ADC,
+ type STATES is (WAIT_ADC,
WAIT_TIMESTAMP
);
signal STATE : STATES;
- signal STATE_d : std_logic_vector(1 downto 0);
-
+ signal STATE_d : std_logic;
+
signal nx_timestamp_o : std_logic_vector(31 downto 0);
signal adc_data_o : std_logic_vector(11 downto 0);
signal new_data_o : std_logic;
-
+ signal merge_timeout_ctr : unsigned(3 downto 0);
+ signal merge_timeout_error : std_logic;
+ signal merge_error_ctr : unsigned(11 downto 0);
+
-- Check Nxyter Data Clock via Johnson Counter
signal nx_data_clock_test_0 : std_logic;
signal nx_data_clock_test_1 : std_logic;
signal adc_frame_rate : unsigned(27 downto 0);
signal frame_rate_ctr : unsigned(27 downto 0);
signal frame_rate : unsigned(27 downto 0);
- signal parity_rate_ctr : unsigned(27 downto 0);
- signal parity_rate : unsigned(27 downto 0);
+ signal parity_err_rate_ctr : unsigned(27 downto 0);
+ signal parity_err_rate : unsigned(27 downto 0);
signal rate_timer_ctr : unsigned(27 downto 0);
-
+
-- Error
signal error_adc0 : std_logic;
signal error_adc1 : std_logic;
signal frame_rate_error : std_logic;
signal parity_rate_error : std_logic;
signal reset_for_offline : std_logic;
-
+
+ -- Data Stream DeltaT Error Counters
+ signal new_adc_delta_t_ctr : unsigned(3 downto 0);
+ signal new_timestamp_delta_t_ctr : unsigned(3 downto 0);
+ signal new_adc_dt_error_ctr : unsigned(11 downto 0);
+ signal new_timestamp_dt_error_ctr : unsigned(11 downto 0);
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
DEBUG_OUT(2) <= nx_fifo_full;
DEBUG_OUT(3) <= nx_fifo_write_enable;
DEBUG_OUT(4) <= nx_fifo_empty;
- DEBUG_OUT(5) <= nx_fifo_empty;
+ DEBUG_OUT(5) <= merge_timeout_error; --STATE_d;
DEBUG_OUT(6) <= nx_fifo_read_enable;
DEBUG_OUT(7) <= nx_fifo_data_valid;
DEBUG_OUT(8) <= adc_data_valid;
DEBUG_OUT(9) <= nx_new_timestamp;
DEBUG_OUT(10) <= adc_new_data;
DEBUG_OUT(11) <= nx_fifo_reset;
- DEBUG_OUT(12) <= '0';
+ DEBUG_OUT(12) <= parity_error;
DEBUG_OUT(13) <= nx_new_frame;
DEBUG_OUT(14) <= new_data_o;
DEBUG_OUT(15) <= nx_frame_synced;
when "10" =>
-- AD9228 Handler Debug output
DEBUG_OUT <= ADC_DEBUG;
-
+
when "11" =>
-- Test Channel
DEBUG_OUT(0) <= CLK_IN;
timer_static_RESET_TIMEOUT: timer_static
generic map (
- CTR_WIDTH => 26,
- CTR_END => 10000000 -- 1s
+ CTR_WIDTH => 30,
+ CTR_END => 1000000000 -- 10s
)
port map (
CLK_IN => CLK_IN,
reset_handler_busy <= '0';
reset_timeout_flag <= '0';
startup_reset <= '1';
+ nx_timestamp_reset_o <= '0';
R_STATE <= R_IDLE;
else
frame_rates_reset <= '0';
rs_timeout_timer_start <= '0';
rs_timeout_timer_reset <= '0';
reset_handler_busy <= '1';
-
+ nx_timestamp_reset_o <= '0';
+
debug_state <= x"0";
if (reset_handler_counter_clear = '1') then
- reset_handler_counter <= (others => '0');
+ reset_handler_counter <= (others => '0');
end if;
if (rs_timeout_timer_done = '1') then
-- Reset Timeout
- reset_timeout_flag <= '1';
+ reset_timeout_flag <= '1';
+ R_STATE <= R_IDLE;
+ else
+
+ case R_STATE is
+ when R_IDLE =>
+ if (reset_for_offline = '1' or
+ pll_adc_not_lock = '1' or
+ adc_reset_sync = '1' or
+ reset_handler_start_r = '1' or
+ startup_reset = '1'
+ ) then
+ if (reset_handler_counter_clear = '0') then
+ reset_handler_counter <= reset_handler_counter + 1;
+ end if;
+ R_STATE <= R_SET_ALL_RESETS;
+ else
+ reset_handler_busy <= '0';
+ R_STATE <= R_IDLE;
+ end if;
+
+ when R_SET_ALL_RESETS =>
+ frame_rates_reset <= '1';
+ nx_fifo_reset <= '1';
+ sampling_clk_reset <= '1';
+ adc_reset_p <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+
+ nx_timestamp_reset_o <= '1';
+
+ rs_wait_timer_start <= '1'; -- wait 1mue to settle
+ R_STATE <= R_WAIT_1;
+ debug_state <= x"1";
+
+ when R_WAIT_1 =>
+ if (rs_wait_timer_done = '0') then
+ nx_fifo_reset <= '1';
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_1;
+ else
+ -- Release NX Fifo Reset + Start Timeout Handler
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ rs_timeout_timer_start <= '1';
+ R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
+ end if;
+ debug_state <= x"2";
+
+ when R_WAIT_NX_FRAME_RATE_OK =>
+ if (nx_frame_rate_offline = '0' and
+ nx_frame_rate_error = '0') then
+ -- Release PLL Reset
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_PLL_WAIT_LOCK;
+ else
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
+ end if;
+ debug_state <= x"3";
+
+ when R_PLL_WAIT_LOCK =>
+ if (pll_adc_not_lock = '1') then
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_PLL_WAIT_LOCK;
+ else
+ -- Release ADC Reset
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_ADC_OK;
+ end if;
+ debug_state <= x"4";
+
+ when R_WAIT_ADC_OK =>
+ if (error_adc0 = '0' and
+ adc_frame_rate_error = '0') then
+ -- Release Output Handler Reset
+ R_STATE <= R_WAIT_DATA_HANDLER_OK;
+ else
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_ADC_OK;
+ end if;
+ debug_state <= x"5";
+
+ when R_WAIT_DATA_HANDLER_OK =>
+ if (frame_rate_error = '0') then
+ startup_reset <= '0';
+ reset_timeout_flag <= '0';
+ rs_timeout_timer_reset <= '1';
+ R_STATE <= R_IDLE;
+ else
+ R_STATE <= R_WAIT_DATA_HANDLER_OK;
+ end if;
+ debug_state <= x"6";
+
+ end case;
end if;
-
- case R_STATE is
- when R_IDLE =>
- if (reset_for_offline = '1' or
- --pll_adc_not_lock = '1' or
- --adc_reset_sync = '1' or
- reset_handler_start_r = '1' or
- startup_reset = '1'
- ) then
- if (reset_handler_counter_clear = '0') then
- reset_handler_counter <= reset_handler_counter + 1;
- end if;
- R_STATE <= R_SET_ALL_RESETS;
- else
- reset_handler_busy <= '0';
- R_STATE <= R_IDLE;
- end if;
-
- when R_SET_ALL_RESETS =>
- frame_rates_reset <= '1';
- nx_fifo_reset <= '1';
- sampling_clk_reset <= '1';
- adc_reset_p <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
-
- rs_wait_timer_start <= '1'; -- wait 1mue to settle
- R_STATE <= R_WAIT_1;
- debug_state <= x"1";
-
- when R_WAIT_1 =>
- if (rs_wait_timer_done = '0') then
- nx_fifo_reset <= '1';
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_1;
- else
- -- Release NX Fifo Reset + Start Timeout HAndler
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- reset_timeout_flag <= '0';
- rs_timeout_timer_start <= '1';
- R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
- end if;
- debug_state <= x"2";
-
- when R_WAIT_NX_FRAME_RATE_OK =>
- if (nx_frame_rate_offline = '0' and
- nx_frame_rate_error = '0') then
- -- Release PLL Reset
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_PLL_WAIT_LOCK;
- else
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
- end if;
- debug_state <= x"3";
-
- when R_PLL_WAIT_LOCK =>
- if (pll_adc_not_lock = '1') then
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_PLL_WAIT_LOCK;
- else
- -- Release ADC Reset
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_ADC_OK;
- end if;
- debug_state <= x"4";
-
- when R_WAIT_ADC_OK =>
- if (error_adc0 = '0' and
- adc_frame_rate_error = '0') then
- -- Release Output Handler Reset
- R_STATE <= R_WAIT_DATA_HANDLER_OK;
- else
- R_STATE <= R_WAIT_ADC_OK;
- end if;
- debug_state <= x"5";
-
- when R_WAIT_DATA_HANDLER_OK =>
- if (frame_rate_error = '0') then
- startup_reset <= '0';
- R_STATE <= R_IDLE;
- else
- R_STATE <= R_WAIT_DATA_HANDLER_OK;
- end if;
- debug_state <= x"6";
-
- end case;
end if;
end if;
end process PROC_RESET_HANDLER;
end if;
end process PROC_RS_FRAME_SYNCED;
- -- Check Parity
- PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN)
- variable parity_bits : std_logic_vector(22 downto 0);
- variable parity : std_logic;
- begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
- parity_error <= '0';
- else
- parity_error <= '0';
- if (nx_new_frame = '1' and nx_frame_synced = '1') then
- -- Timestamp Bit #6 is excluded (funny nxyter-bug)
- parity_bits := nx_frame_word(31) &
- nx_frame_word(30 downto 24) &
- nx_frame_word(21 downto 16) &
- nx_frame_word(14 downto 8) &
- nx_frame_word( 2 downto 1);
- parity := xor_all(parity_bits);
-
- if (parity /= nx_frame_word(0)) then
- parity_error <= '1';
- end if;
- end if;
- end if;
- end if;
- end process PROC_PARITY_CHECK;
-
fifo_ts_32to32_dc_1: fifo_ts_32to32_dc
port map (
- Data => nx_frame_word,
- WrClock => NX_TIMESTAMP_CLK_IN,
- RdClock => CLK_IN,
- WrEn => nx_fifo_write_enable,
- RdEn => nx_fifo_read_enable,
- Reset => nx_fifo_reset,
- RPReset => nx_fifo_reset,
- Q => nx_fifo_data,
- Empty => nx_fifo_empty,
- Full => nx_fifo_full
+ Data => nx_frame_word,
+ WrClock => NX_TIMESTAMP_CLK_IN,
+ RdClock => CLK_IN,
+ WrEn => nx_fifo_write_enable,
+ RdEn => nx_fifo_read_enable,
+ Reset => nx_fifo_reset,
+ RPReset => nx_fifo_reset,
+ Q => nx_fifo_data_f,
+ Empty => nx_fifo_empty,
+ Full => nx_fifo_full
);
nx_fifo_write_enable <= nx_new_frame and not nx_fifo_full;
-- NX CLK_IN Domain
-----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- Gray Decode Timestamp Frame (Timestamp and Channel Id)
+ -----------------------------------------------------------------------------
+
+ gray_decoder_TIMESTAMP: gray_decoder -- Decode nx_timestamp
+ generic map (
+ WIDTH => 14
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ GRAY_IN(13 downto 7) => not nx_fifo_data_f(30 downto 24),
+ GRAY_IN( 6 downto 0) => not nx_fifo_data_f(22 downto 16),
+ BINARY_OUT(13 downto 7) => nx_fifo_data(30 downto 24),
+ BINARY_OUT(6 downto 0) => nx_fifo_data(22 downto 16)
+ );
+
+ gray_decoder_CHANNEL_ID: gray_decoder -- Decode Channel_ID
+ generic map (
+ WIDTH => 7
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ GRAY_IN => nx_fifo_data_f(14 downto 8),
+ BINARY_OUT => nx_fifo_data(14 downto 8)
+ );
+
+ -- Leave other bits untouched
+ PROC_GRAY_DECODE: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
+ nx_fifo_data(31) <= nx_fifo_data_f(31);
+ nx_fifo_data(23) <= nx_fifo_data_f(23);
+ nx_fifo_data(15) <= nx_fifo_data_f(15);
+ nx_fifo_data(7 downto 1) <= nx_fifo_data_f(7 downto 1);
+ end if;
+ end process PROC_GRAY_DECODE;
+
+ -- Replace Parity Bit by Parity Error Bit
+ PROC_PARITY_CHECKER: process(CLK_IN)
+ variable parity_bits : std_logic_vector(22 downto 0);
+ variable parity : std_logic;
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ nx_fifo_data(0) <= '0';
+ else
+ -- Timestamp Bit #6 is excluded (funny nxyter-bug)
+ parity_bits := nx_fifo_data_f(31) &
+ nx_fifo_data_f(30 downto 24) &
+ nx_fifo_data_f(21 downto 16) &
+ nx_fifo_data_f(14 downto 8) &
+ nx_fifo_data_f( 2 downto 1);
+ parity := xor_all(parity_bits);
+ if (parity /= nx_fifo_data_f(0)) then
+ nx_fifo_data(0) <= '1';
+ else
+ nx_fifo_data(0) <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_PARITY_CHECKER;
+
+ -----------------------------------------------------------------------------
-- FIFO Read Handler
+ -----------------------------------------------------------------------------
+
nx_fifo_read_enable <= not nx_fifo_empty;
PROC_NX_FIFO_READ_ENABLE: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
- nx_fifo_data_valid_t <= nx_fifo_read_enable;
+ nx_fifo_data_valid_tt <= nx_fifo_read_enable;
if(RESET_IN = '1') then
+ nx_fifo_data_valid_t <= '0';
nx_fifo_data_valid <= '0';
else
- -- Delay read signal by one CLK
+ -- Delay read signal by two Clock Cycles
+ nx_fifo_data_valid_t <= nx_fifo_data_valid_tt;
nx_fifo_data_valid <= nx_fifo_data_valid_t;
end if;
end if;
for I in 1 to 15 loop
nx_timestamp_d(I) <= (others => '0');
end loop;
+ parity_error <= '0';
else
if (nx_fifo_data_valid = '1') then
-- Delay Data relative to ADC by 8 steps
nx_timestamp_t <= nx_timestamp_d(to_integer(nx_fifo_delay));
nx_new_timestamp <= '1';
nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1;
+ parity_error <= nx_timestamp_d(to_integer(nx_fifo_delay))(0);
else
nx_timestamp_t <= x"deadbeef";
nx_new_timestamp <= '0';
+ parity_error <= '0';
end if;
end if;
end if;
PULSE_B_OUT => resync_ctr_inc
);
- pulse_dtrans_3: pulse_dtrans
- generic map (
- CLK_RATIO => 3
- )
- port map (
- CLK_A_IN => NX_TIMESTAMP_CLK_IN,
- RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
- PULSE_A_IN => parity_error,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => parity_error_ctr_inc
- );
-
-- nx_frame_synced --> CLK_IN Domain
signal_async_trans_1: signal_async_trans
port map (
if (RESET_IN = '1' or reset_parity_error_ctr = '1') then
parity_error_counter <= (others => '0');
else
- if (parity_error_ctr_inc = '1') then
+ if (parity_error = '1') then
parity_error_counter <= parity_error_counter + 1;
end if;
end if;
-----------------------------------------------------------------------------
-- Output handler
-----------------------------------------------------------------------------
- PROC_OUTPUT_HANDLER: process(CLK_IN)
+
+ PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ new_adc_delta_t_ctr <= (others => '0');
+ new_timestamp_delta_t_ctr <= (others => '0');
+ new_adc_dt_error_ctr <= (others => '0');
+ new_timestamp_dt_error_ctr <= (others => '0');
+ else
+ -- ADC
+ if (adc_new_data = '1') then
+ if (new_adc_delta_t_ctr < x"2" or
+ new_adc_delta_t_ctr > x"3") then
+ new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1;
+ end if;
+ new_adc_delta_t_ctr <= (others => '0');
+ else
+ new_adc_delta_t_ctr <= new_adc_delta_t_ctr + 1;
+ end if;
+
+ -- TimeStamp
+ if (nx_new_timestamp = '1') then
+ if (new_timestamp_delta_t_ctr < x"2" or
+ new_timestamp_delta_t_ctr > x"3") then
+ new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1;
+ end if;
+ new_timestamp_delta_t_ctr <= (others => '0');
+ else
+ new_timestamp_delta_t_ctr <= new_timestamp_delta_t_ctr + 1;
+ end if;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
+
+ PROC_OUTPUT_MERGE_HANDLER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
if (RESET_IN = '1' or output_handler_reset = '1') then
- nx_timestamp_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- STATE <= IDLE;
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ new_data_o <= '0';
+ merge_timeout_ctr <= (others => '0');
+ merge_timeout_error <= '0';
+ merge_error_ctr <= (others => '0');
+ STATE <= WAIT_ADC;
else
case STATE is
- when IDLE =>
- STATE_d <= "00";
- if (nx_new_timestamp = '1' and adc_new_data = '1') then
- nx_timestamp_o <= nx_timestamp_t;
- adc_data_o <= adc_data_t;
- new_data_o <= '1';
- STATE <= IDLE;
- elsif (nx_new_timestamp = '1') then
- nx_timestamp_o <= nx_timestamp_t;
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- STATE <= WAIT_ADC;
- elsif (adc_new_data = '1') then
- adc_data_o <= adc_data_t;
- nx_timestamp_o <= (others => '0');
- new_data_o <= '0';
- STATE <= WAIT_TIMESTAMP;
- else
- nx_timestamp_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- STATE <= IDLE;
- end if;
-
when WAIT_ADC =>
- STATE_d <= "01";
- if (adc_new_data = '1') then
- adc_data_o <= adc_data_t;
- new_data_o <= '1';
- STATE <= IDLE;
- else
- new_data_o <= '0';
- STATE <= WAIT_ADC;
+ STATE_d <= '0';
+ if (adc_new_data = '1' and nx_new_timestamp = '1') then
+ nx_timestamp_o <= nx_timestamp_t;
+ adc_data_o <= adc_data_t;
+ new_data_o <= '1';
+ merge_timeout_ctr <= (others => '0');
+ STATE <= WAIT_ADC;
+ elsif (adc_new_data = '1') then
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= adc_data_t;
+ new_data_o <= '0';
+ STATE <= WAIT_TIMESTAMP;
+ else
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ new_data_o <= '0';
+ merge_timeout_ctr <= merge_timeout_ctr + 1;
+ STATE <= WAIT_ADC;
end if;
when WAIT_TIMESTAMP =>
- STATE_d <= "10";
- if (nx_new_timestamp = '1') then
- nx_timestamp_o <= nx_timestamp_t;
- new_data_o <= '1';
- STATE <= IDLE;
+ STATE_d <= '1';
+ if (merge_timeout_error = '1') then
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ new_data_o <= '0';
+ merge_timeout_ctr <= (others => '0');
+ STATE <= WAIT_ADC;
else
- new_data_o <= '0';
- STATE <= WAIT_TIMESTAMP;
- end if;
-
+ if (nx_new_timestamp = '1') then
+ nx_timestamp_o <= nx_timestamp_t;
+ new_data_o <= '1';
+ merge_timeout_ctr <= (others => '0');
+ STATE <= WAIT_ADC;
+ else
+ nx_timestamp_o <= (others => '0');
+ new_data_o <= '0';
+ merge_timeout_ctr <= merge_timeout_ctr + 1;
+ STATE <= WAIT_TIMESTAMP;
+ end if;
+ end if;
+
end case;
+
+ -- Timeout?
+ if (merge_timeout_ctr > x"3") then
+ merge_timeout_error <= '1';
+ merge_error_ctr <= merge_error_ctr + 1;
+ else
+ merge_timeout_error <= '0';
+ end if;
end if;
end if;
- end process PROC_OUTPUT_HANDLER;
+ end process PROC_OUTPUT_MERGE_HANDLER;
-----------------------------------------------------------------------------
-- Rate Counters + Rate Error Check
adc_frame_rate <= (others => '0');
frame_rate_ctr <= (others => '0');
frame_rate <= (others => '0');
- parity_rate_ctr <= (others => '0');
- parity_rate <= (others => '0');
+ parity_err_rate_ctr <= (others => '0');
+ parity_err_rate <= (others => '0');
rate_timer_ctr <= (others => '0');
else
if (rate_timer_ctr < x"5f5e100") then
- rate_timer_ctr <= rate_timer_ctr + 1;
+ rate_timer_ctr <= rate_timer_ctr + 1;
if (nx_fifo_data_valid = '1') then
- nx_frame_rate_ctr <= nx_frame_rate_ctr + 1;
- end if;
-
- if (adc_data_valid = '1') then
- adc_frame_rate_ctr <= adc_frame_rate_ctr + 1;
- end if;
-
- if (new_data_o = '1') then
- frame_rate_ctr <= frame_rate_ctr + 1;
- end if;
-
- if (parity_error_ctr_inc = '1') then
- parity_rate_ctr <= parity_rate_ctr + 1;
- end if;
- else
- rate_timer_ctr <= (others => '0');
- nx_frame_rate <= nx_frame_rate_ctr;
- adc_frame_rate <= adc_frame_rate_ctr;
- frame_rate <= frame_rate_ctr;
- parity_rate <= parity_rate_ctr;
-
- nx_frame_rate_ctr(27 downto 1) <= (others => '0');
- nx_frame_rate_ctr(0) <= nx_fifo_data_valid;
-
- adc_frame_rate_ctr(27 downto 1) <= (others => '0');
- adc_frame_rate_ctr(0) <= adc_data_valid;
-
- frame_rate_ctr(27 downto 1) <= (others => '0');
- frame_rate_ctr(0) <= new_data_o;
-
- parity_rate_ctr(27 downto 1) <= (others => '0');
- parity_rate_ctr(0) <= parity_error_ctr_inc;
+ nx_frame_rate_ctr <= nx_frame_rate_ctr + 1;
+ end if;
+
+ if (adc_data_valid = '1') then
+ adc_frame_rate_ctr <= adc_frame_rate_ctr + 1;
+ end if;
+
+ if (new_data_o = '1') then
+ frame_rate_ctr <= frame_rate_ctr + 1;
+ end if;
+
+ if (parity_error = '1') then
+ parity_err_rate_ctr <= parity_err_rate_ctr + 1;
+ end if;
+ else
+ rate_timer_ctr <= (others => '0');
+ nx_frame_rate <= nx_frame_rate_ctr;
+ adc_frame_rate <= adc_frame_rate_ctr;
+ frame_rate <= frame_rate_ctr;
+ parity_err_rate <= parity_err_rate_ctr;
+
+ nx_frame_rate_ctr(27 downto 1) <= (others => '0');
+ nx_frame_rate_ctr(0) <= nx_fifo_data_valid;
+
+ adc_frame_rate_ctr(27 downto 1) <= (others => '0');
+ adc_frame_rate_ctr(0) <= adc_data_valid;
+
+ frame_rate_ctr(27 downto 1) <= (others => '0');
+ frame_rate_ctr(0) <= new_data_o;
+
+ parity_err_rate_ctr(27 downto 1) <= (others => '0');
+ parity_err_rate_ctr(0) <= parity_error;
end if;
end if;
end if;
frame_rate_error <= '0';
end if;
- if (parity_rate > 0) then
- parity_rate_error <= '1';
+ if (parity_err_rate > 0) then
+ parity_rate_error <= '1';
else
- parity_rate_error <= '0';
+ parity_rate_error <= '0';
end if;
-- Reset Request to Reset Handler
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o <= nx_timestamp_t;
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0) <= error_status_bits;
+ slv_data_out_o(31 downto 8) <= (others => '0');
+ slv_ack_o <= '1';
when x"0001" =>
- slv_data_out_o(0) <= nx_fifo_full;
- slv_data_out_o(1) <= nx_fifo_empty;
- slv_data_out_o(2) <= '0';
- slv_data_out_o(3) <= '0';
- slv_data_out_o(4) <= nx_fifo_data_valid;
- slv_data_out_o(5) <= adc_new_data;
- slv_data_out_o(29 downto 5) <= (others => '0');
- slv_data_out_o(30) <= '0';
- slv_data_out_o(31) <= reg_nx_frame_synced;
- slv_ack_o <= '1';
-
+ slv_data_out_o(0) <= reset_handler_busy;
+ slv_data_out_o(1) <= reset_timeout_flag;
+ slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"0002" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(resync_counter);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0) <= std_logic_vector(frame_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"0003" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(parity_error_counter);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_data_out_o(27 downto 0) <= std_logic_vector(nx_frame_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"0004" =>
- slv_data_out_o(11 downto 0) <=
- std_logic_vector(pll_adc_not_lock_ctr);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"0005" =>
- slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
- slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_data_out_o(27 downto 0) <= parity_err_rate;
+ slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0006" =>
- slv_data_out_o(3 downto 0) <=
- std_logic_vector(pll_adc_sample_clk_dphase_r);
- slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_data_out_o(15 downto 0) <= reset_handler_counter;
+ slv_data_out_o(31 downto 6) <= (others => '0');
slv_ack_o <= '1';
when x"0007" =>
- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb;
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0008" =>
- slv_data_out_o(11 downto 0) <= adc_data_t;
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
+
+ when x"0008" =>
+ slv_data_out_o(7 downto 0) <=
+ std_logic_vector(adc_notlock_ctr);
+ slv_data_out_o(31 downto 8) <= (others => '0');
+ slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr);
+ slv_data_out_o(11 downto 0) <= merge_error_ctr;
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000a" =>
- slv_data_out_o(31 downto 0) <= (others => '0');
- slv_ack_o <= '1';
+ when x"000a" =>
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(resync_counter);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"000b" =>
- slv_data_out_o(0) <= reset_handler_busy;
- slv_data_out_o(31 downto 1) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(parity_error_counter);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"000c" =>
- slv_data_out_o(15 downto 0) <= reset_handler_counter;
- slv_data_out_o(31 downto 6) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_data_out_o(11 downto 0) <=
+ std_logic_vector(pll_adc_not_lock_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"000d" =>
- slv_data_out_o(3 downto 0) <= std_logic_vector(nx_fifo_delay);
+ slv_data_out_o(3 downto 0) <=
+ std_logic_vector(pll_adc_sample_clk_dphase_r);
slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
when x"000e" =>
- slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift);
+ slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb;
slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_ack_o <= '1';
+
when x"000f" =>
- slv_data_out_o(7 downto 0) <=
- std_logic_vector(adc_notlock_ctr);
- slv_data_out_o(31 downto 8) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
+ slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_ack_o <= '1';
when x"0010" =>
- slv_data_out_o(27 downto 0) <= std_logic_vector(nx_frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(3 downto 0) <= std_logic_vector(nx_fifo_delay);
+ slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_ack_o <= '1';
when x"0011" =>
- slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(0) <= nx_fifo_full;
+ slv_data_out_o(1) <= nx_fifo_empty;
+ slv_data_out_o(2) <= '0';
+ slv_data_out_o(3) <= '0';
+ slv_data_out_o(4) <= nx_fifo_data_valid;
+ slv_data_out_o(5) <= adc_new_data;
+ slv_data_out_o(29 downto 5) <= (others => '0');
+ slv_data_out_o(30) <= '0';
+ slv_data_out_o(31) <= reg_nx_frame_synced;
+ slv_ack_o <= '1';
when x"0012" =>
- slv_data_out_o(11 downto 0) <= test_adc_data;
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift);
+ slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0013" =>
- slv_data_out_o(27 downto 0) <= std_logic_vector(frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o <= nx_timestamp_t;
+ slv_ack_o <= '1';
when x"0014" =>
- slv_data_out_o(11 downto 0) <= error_status_bits;
- slv_data_out_o(31 downto 8) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"0015" =>
- slv_data_out_o(27 downto 0) <= parity_rate;
- slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"001c" =>
+ slv_data_out_o(11 downto 0) <= adc_data_t;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"001d" =>
+ slv_data_out_o(11 downto 0) <= test_adc_data;
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"001e" =>
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
- when x"0002" =>
+ when x"0001" =>
+ reset_handler_start_r <= '1';
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ reset_handler_counter_clear <= '1';
+ slv_ack_o <= '1';
+
+ when x"000a" =>
reset_resync_ctr <= '1';
slv_ack_o <= '1';
- when x"0003" =>
+ when x"000b" =>
reset_parity_error_ctr <= '1';
slv_ack_o <= '1';
-
- when x"0004" =>
+
+ when x"000c" =>
pll_adc_not_lock_ctr_clear <= '1';
slv_ack_o <= '1';
-
- when x"0005" =>
- johnson_counter_sync_r <= SLV_DATA_IN(1 downto 0);
- reset_handler_start_r <= '1';
- slv_ack_o <= '1';
- when x"0006" =>
+ when x"000d" =>
pll_adc_sample_clk_dphase_r <=
unsigned(SLV_DATA_IN(3 downto 0));
reset_handler_start_r <= '1';
slv_ack_o <= '1';
-
- when x"0007" =>
+
+ when x"000e" =>
pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0);
reset_handler_start_r <= '1';
slv_ack_o <= '1';
- when x"000b" =>
+ when x"000f" =>
+ johnson_counter_sync_r <= SLV_DATA_IN(1 downto 0);
reset_handler_start_r <= '1';
- slv_ack_o <= '1';
-
- when x"000c" =>
- reset_handler_counter_clear <= '1';
- slv_ack_o <= '1';
-
- when x"000d" =>
+ slv_ack_o <= '1';
+
+ when x"0010" =>
nx_fifo_delay <=
unsigned(SLV_DATA_IN(3 downto 0));
slv_ack_o <= '1';
- when x"000e" =>
+ when x"0012" =>
adc_bit_shift <=
unsigned(SLV_DATA_IN(3 downto 0));
slv_ack_o <= '1';
-
+
when x"001e" =>
debug_adc <= SLV_DATA_IN(1 downto 0);
slv_ack_o <= '1';
nx_frame_rate_offline = '1' or
nx_frame_rate_error = '1' or
adc_clk_ok = '0' or
- parity_error_ctr_inc = '1' or
+ parity_error = '1' or
reg_nx_frame_synced = '0' or
adc_frame_rate_error = '1' or
parity_rate_error = '1'
end process PROC_ERROR;
-- Output Signals
-
- NX_TIMESTAMP_OUT <= nx_timestamp_o
- when new_data_o = '1' else x"0000_0000";
- ADC_DATA_OUT <= adc_data_o when new_data_o = '1' else x"000";
- NEW_DATA_OUT <= new_data_o;
- ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock;
- ERROR_OUT <= error_o;
-
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
+ NX_TIMESTAMP_RESET_OUT <= nx_timestamp_reset_o;
+ NX_TIMESTAMP_OUT <= nx_timestamp_o;
+ ADC_DATA_OUT <= adc_data_o;
+ NEW_DATA_OUT <= new_data_o;
+ ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock;
+ ERROR_OUT <= error_o;
+
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
end Behavioral;
-- Inputs
NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0);
ADC_DATA_IN : in std_logic_vector(11 downto 0);
- NEW_DATA_IN : in std_logic;
+ DATA_CLK_IN : in std_logic;
-- Outputs
TIMESTAMP_OUT : out std_logic_vector(13 downto 0);
CHANNEL_OUT : out std_logic_vector(6 downto 0);
TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- DATA_VALID_OUT : out std_logic;
- SELF_TRIGGER_OUT : out std_logic;
+ DATA_CLK_OUT : out std_logic;
NX_TOKEN_RETURN_OUT : out std_logic;
NX_NOMORE_DATA_OUT : out std_logic;
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
+
+ ERROR_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
signal new_timestamp : std_logic;
signal valid_frame_bits : std_logic_vector(3 downto 0);
signal status_bits : std_logic_vector(1 downto 0);
- signal parity_bit : std_logic;
- signal parity : std_logic;
+ signal parity_error : std_logic;
signal adc_data : std_logic_vector(11 downto 0);
-- Validate Timestamp
signal channel_o : std_logic_vector(6 downto 0);
signal timestamp_status_o : std_logic_vector(2 downto 0);
signal adc_data_o : std_logic_vector(11 downto 0);
- signal data_valid_o : std_logic;
+ signal data_clk_o : std_logic;
signal nx_token_return_o : std_logic;
signal nx_nomore_data_o : std_logic;
signal invalid_frame_ctr : unsigned(15 downto 0);
signal overflow_ctr : unsigned(15 downto 0);
signal pileup_ctr : unsigned(15 downto 0);
- signal parity_error_ctr : unsigned(15 downto 0);
signal trigger_rate_inc : std_logic;
signal frame_rate_inc : std_logic;
signal nx_frame_ctr_t : unsigned(27 downto 0);
signal nx_pileup_ctr_t : unsigned(27 downto 0);
signal nx_overflow_ctr_t : unsigned(27 downto 0);
+ signal adc_tr_error_ctr_t : unsigned(27 downto 0);
+
signal nx_rate_timer : unsigned(27 downto 0);
-- ADC Averages
signal adc_average_divisor : unsigned(3 downto 0);
- signal adc_average_ctr : unsigned(8 downto 0);
- signal adc_average_sum : unsigned(24 downto 0);
+ signal adc_average_ctr : unsigned(15 downto 0);
+ signal adc_average_sum : unsigned(31 downto 0);
signal adc_average : unsigned(11 downto 0);
signal adc_data_last : std_logic_vector(11 downto 0);
- signal adc_av : std_logic;
+
+ -- Token Return Average
+ signal adc_tr_data_p : std_logic_vector(11 downto 0);
+ signal adc_tr_data_c : std_logic_vector(11 downto 0);
+ signal adc_tr_data_clk : std_logic;
+ signal adc_tr_average_divisor : unsigned(7 downto 0);
+ signal adc_tr_average_ctr : unsigned(15 downto 0);
+ signal adc_tr_average_sum : unsigned(31 downto 0);
+ signal adc_tr_average : unsigned(11 downto 0);
+ signal adc_tr_mean : unsigned(11 downto 0);
+ signal adc_tr_limit : unsigned(11 downto 0);
+ signal adc_tr_error_ctr : unsigned(11 downto 0);
+ signal adc_tr_error : std_logic;
+ signal adc_tr_error_status : std_logic_vector(1 downto 0);
+ signal adc_tr_debug_mode : std_logic;
-- Config
signal readout_type : std_logic_vector(1 downto 0);
+ -- Error Status
+ signal error_o : std_logic;
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal nx_frame_rate : unsigned(27 downto 0);
signal nx_pileup_rate : unsigned(27 downto 0);
signal nx_overflow_rate : unsigned(27 downto 0);
- signal invalid_adc : std_logic;
+ signal adc_tr_error_rate : unsigned(27 downto 0);
+ signal invalid_adc : std_logic;
begin
-- Debug Line
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= nx_token_return_o;
- DEBUG_OUT(2) <= nx_nomore_data_o;
- DEBUG_OUT(3) <= data_valid_o;
- DEBUG_OUT(4) <= new_timestamp;
- DEBUG_OUT(5) <= self_trigger_o;
- DEBUG_OUT(8 downto 6) <= (others => '0');
- DEBUG_OUT(15 downto 9) <= channel_o;
- --DEBUG_OUT(6 downto 4) <= timestamp_status_o;
- --DEBUG_OUT(7) <= nx_token_return_o;
- --DEBUG_OUT(8) <= invalid_adc;--nx_nomore_data_o;
-
- --DEBUG_OUT(15 downto 9) <= channel_o;
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= data_clk_o; --DATA_CLK_IN;
+ DEBUG_OUT(2) <= nx_token_return_o;
+ DEBUG_OUT(3) <= nx_nomore_data_o;
+
+ DEBUG_OUT(15 downto 4) <= adc_data;
+
+ --DEBUG_OUT(4) <= data_clk_o;
+ --DEBUG_OUT(5) <= new_timestamp;
+ --DEBUG_OUT(6) <= self_trigger_o;
+ --DEBUG_OUT(7) <= invalid_adc;
+ --DEBUG_OUT(8) <= adc_tr_data_clk;
+ --DEBUG_OUT(9) <= adc_tr_error;
+ --DEBUG_OUT(15 downto 10) <= channel_o(5 downto 0);
-----------------------------------------------------------------------------
- -- Gray Decoder for Timestamp and Channel Id
+ -- Data Separation
-----------------------------------------------------------------------------
-
- Gray_Decoder_1: Gray_Decoder -- Decode nx_timestamp
- generic map (
- WIDTH => 14
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- GRAY_IN(13 downto 7) => not NX_TIMESTAMP_IN(30 downto 24),
- GRAY_IN( 6 downto 0) => not NX_TIMESTAMP_IN(22 downto 16),
- BINARY_OUT => nx_timestamp
- );
-
- Gray_Decoder_2: Gray_Decoder -- Decode Channel_ID
- generic map (
- WIDTH => 7
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- GRAY_IN => NX_TIMESTAMP_IN(14 downto 8),
- BINARY_OUT => nx_channel_id
- );
-
- -- Separate Status-, Parity- and Frame-bits, calculate parity
+
+ -- Separate Timestamp-, Status-, Parity- and Frame-bits
PROC_TIMESTAMP_BITS: process (CLK_IN)
- variable parity_bits : std_logic_vector(22 downto 0);
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
valid_frame_bits <= (others => '0');
+ nx_timestamp <= (others => '0');
+ nx_channel_id <= (others => '0');
status_bits <= (others => '0');
- parity_bit <= '0';
- parity <= '0';
+ parity_error <= '0';
new_timestamp <= '0';
adc_data <= (others => '0');
else
- -- Timestamp Bit #6 is excluded (funny nxyter-bug)
- parity_bits := NX_TIMESTAMP_IN(31 downto 24) &
- NX_TIMESTAMP_IN(21 downto 16) &
- NX_TIMESTAMP_IN(14 downto 8) &
- NX_TIMESTAMP_IN( 2 downto 1);
- valid_frame_bits <= (others => '0');
- status_bits <= (others => '0');
- parity_bit <= '0';
- parity <= '0';
- new_timestamp <= '0';
- adc_data <= (others => '0');
-
- if (NEW_DATA_IN = '1') then
- valid_frame_bits(3) <= NX_TIMESTAMP_IN(31);
- valid_frame_bits(2) <= NX_TIMESTAMP_IN(23);
- valid_frame_bits(1) <= NX_TIMESTAMP_IN(15);
- valid_frame_bits(0) <= NX_TIMESTAMP_IN(7);
- status_bits <= NX_TIMESTAMP_IN(2 downto 1);
- parity_bit <= NX_TIMESTAMP_IN(0);
- parity <= xor_all(parity_bits);
- adc_data <= ADC_DATA_IN;
- new_timestamp <= '1';
+ if (DATA_CLK_IN = '1') then
+ valid_frame_bits(3) <= NX_TIMESTAMP_IN(31);
+ valid_frame_bits(2) <= NX_TIMESTAMP_IN(23);
+ valid_frame_bits(1) <= NX_TIMESTAMP_IN(15);
+ valid_frame_bits(0) <= NX_TIMESTAMP_IN(7);
+ nx_timestamp(13 downto 7) <= NX_TIMESTAMP_IN(30 downto 24);
+ nx_timestamp(6 downto 0) <= NX_TIMESTAMP_IN(22 downto 16);
+ nx_channel_id <= NX_TIMESTAMP_IN(14 downto 8);
+ status_bits <= NX_TIMESTAMP_IN(2 downto 1);
+ parity_error <= NX_TIMESTAMP_IN(0);
+ adc_data <= ADC_DATA_IN;
+ new_timestamp <= '1';
+ else
+ valid_frame_bits <= (others => '0');
+ nx_timestamp <= (others => '0');
+ nx_channel_id <= (others => '0');
+ status_bits <= (others => '0');
+ parity_error <= '0';
+ adc_data <= (others => '0');
+ new_timestamp <= '0';
end if;
end if;
end if;
channel_o <= (others => '0');
timestamp_status_o <= (others => '0');
adc_data_o <= (others => '0');
- data_valid_o <= '0';
+ data_clk_o <= '0';
nx_token_return_o <= '0';
nx_nomore_data_o <= '0';
trigger_rate_inc <= '0';
frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
-
invalid_frame_ctr <= (others => '0');
overflow_ctr <= (others => '0');
pileup_ctr <= (others => '0');
- parity_error_ctr <= (others => '0');
+ invalid_adc <= '0';
+ adc_tr_data_p <= (others => '0');
+ adc_tr_data_c <= (others => '0');
+ adc_tr_data_clk <= '0';
+ adc_data_last <= (others => '0');
else
timestamp_o <= (others => '0');
channel_o <= (others => '0');
timestamp_status_o <= (others => '0');
adc_data_o <= (others => '0');
- data_valid_o <= '0';
+ data_clk_o <= '0';
trigger_rate_inc <= '0';
frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
invalid_adc <= '0';
-
+ adc_tr_data_clk <= '0';
+
if (new_timestamp = '1') then
+ adc_data_last <= adc_data;
+
case valid_frame_bits is
-- Data Frame
overflow_rate_inc <= '1';
end if;
- ---- Check Parity
- if ((parity_bit /= parity) and (clear_counters = '0')) then
- timestamp_status_o(2) <= '1';
- parity_error_ctr <= parity_error_ctr + 1;
- else
- timestamp_status_o(2) <= '0';
- end if;
-
-- Check PileUp
if ((status_bits(1) = '1') and (clear_counters = '0')) then
pileup_ctr <= pileup_ctr + 1;
-- Take Timestamp
timestamp_o <= nx_timestamp;
channel_o <= nx_channel_id;
+ timestamp_status_o(2) <= parity_error;
timestamp_status_o(1 downto 0) <= status_bits;
- adc_data_o <= adc_data;
- data_valid_o <= '1';
+ if (adc_tr_debug_mode = '0') then
+ adc_data_o <= adc_data;
+ else
+ adc_data_o <= adc_tr_data_p;
+ end if;
+ data_clk_o <= '1';
if (adc_data = x"aff") then
invalid_adc <= '1';
nx_token_return_o <= '0';
nx_nomore_data_o <= '0';
trigger_rate_inc <= '1';
-
+
+ if (nx_token_return_o = '1') then
+ -- First Data Word after empty Frame
+ adc_tr_data_p <= adc_data_last;
+ adc_tr_data_c <= adc_data;
+ adc_tr_data_clk <= '1';
+ end if;
+
-- Token return and nomore_data
when "0000" =>
nx_token_return_o <= '1';
invalid_frame_ctr <= (others => '0');
overflow_ctr <= (others => '0');
pileup_ctr <= (others => '0');
- parity_error_ctr <= (others => '0');
end if;
end if;
end if;
nx_rate_timer <= (others => '0');
nx_hit_rate <= (others => '0');
nx_frame_rate <= (others => '0');
+ adc_tr_error_rate <= (others => '0');
else
if (nx_rate_timer < x"5f5e100") then
if (trigger_rate_inc = '1') then
- nx_trigger_ctr_t <= nx_trigger_ctr_t + 1;
+ nx_trigger_ctr_t <= nx_trigger_ctr_t + 1;
end if;
if (frame_rate_inc = '1') then
- nx_frame_ctr_t <= nx_frame_ctr_t + 1;
+ nx_frame_ctr_t <= nx_frame_ctr_t + 1;
end if;
if (pileup_rate_inc = '1') then
- nx_pileup_ctr_t <= nx_pileup_ctr_t + 1;
+ nx_pileup_ctr_t <= nx_pileup_ctr_t + 1;
end if;
if (overflow_rate_inc = '1') then
- nx_overflow_ctr_t <= nx_overflow_ctr_t + 1;
- end if;
- nx_rate_timer <= nx_rate_timer + 1;
- else
- nx_hit_rate <= nx_trigger_ctr_t;
- nx_frame_rate <= nx_frame_ctr_t;
- nx_pileup_rate <= nx_pileup_ctr_t;
- nx_overflow_rate <= nx_overflow_ctr_t;
-
- nx_trigger_ctr_t(27 downto 1) <= (others => '0');
- nx_trigger_ctr_t(0) <= trigger_rate_inc;
-
- nx_frame_ctr_t(27 downto 1) <= (others => '0');
- nx_frame_ctr_t(0) <= frame_rate_inc;
-
- nx_pileup_ctr_t(27 downto 1) <= (others => '0');
- nx_pileup_ctr_t(0) <= pileup_rate_inc;
-
- nx_overflow_ctr_t(27 downto 1) <= (others => '0');
- nx_overflow_ctr_t(0) <= overflow_rate_inc;
+ nx_overflow_ctr_t <= nx_overflow_ctr_t + 1;
+ end if;
+ if (adc_tr_error = '1') then
+ adc_tr_error_ctr_t <= adc_tr_error_ctr_t + 1;
+ end if;
+ nx_rate_timer <= nx_rate_timer + 1;
+ else
+ nx_hit_rate <= nx_trigger_ctr_t;
+ nx_frame_rate <= nx_frame_ctr_t;
+ nx_pileup_rate <= nx_pileup_ctr_t;
+ nx_overflow_rate <= nx_overflow_ctr_t;
+ adc_tr_error_rate <= adc_tr_error_ctr_t;
+
+ nx_trigger_ctr_t(27 downto 1) <= (others => '0');
+ nx_trigger_ctr_t(0) <= trigger_rate_inc;
+
+ nx_frame_ctr_t(27 downto 1) <= (others => '0');
+ nx_frame_ctr_t(0) <= frame_rate_inc;
+
+ nx_pileup_ctr_t(27 downto 1) <= (others => '0');
+ nx_pileup_ctr_t(0) <= pileup_rate_inc;
+
+ nx_overflow_ctr_t(27 downto 1) <= (others => '0');
+ nx_overflow_ctr_t(0) <= overflow_rate_inc;
+
+ adc_tr_error_ctr_t(27 downto 0) <= (others => '0');
+ adc_tr_error_ctr_t(0) <= adc_tr_error;
- nx_rate_timer <= (others => '0');
+ nx_rate_timer <= (others => '0');
end if;
end if;
end if;
adc_average_ctr <= (others => '0');
adc_average_sum <= (others => '0');
adc_average <= (others => '0');
- adc_data_last <= (others => '0');
- adc_av <= '0';
else
- adc_av <= '0';
if ((adc_average_ctr srl to_integer(adc_average_divisor)) > 0) then
- adc_average <= (adc_average_sum srl
+ adc_average <= (adc_average_sum srl
to_integer(adc_average_divisor))(11 downto 0);
- adc_average_sum <= (others => '0');
- adc_average_ctr <= (others => '0');
- adc_av <= '1';
- elsif (data_valid_o = '1') then
- adc_average_sum <= adc_average_sum + unsigned(adc_data_o);
- adc_average_ctr <= adc_average_ctr + 1;
+ if (data_clk_o = '1') then
+ adc_average_sum(11 downto 0) <= unsigned(adc_data_o);
+ adc_average_sum(31 downto 13) <= (others => '0');
+ adc_average_ctr <= x"0001";
+ else
+ adc_average_sum <= (others => '0');
+ adc_average_ctr <= (others => '0');
+ end if;
+ elsif (data_clk_o = '1') then
+ adc_average_sum <= adc_average_sum + unsigned(adc_data_o);
+ adc_average_ctr <= adc_average_ctr + 1;
end if;
- if (data_valid_o = '1') then
- adc_data_last <= adc_data_o;
- end if;
end if;
end if;
end process PROC_ADC_AVERAGE;
- -----------------------------------------------------------------------------
- -- Self Trigger Out
- -----------------------------------------------------------------------------
- pulse_to_level_SELF_TRIGGER: pulse_to_level
- generic map (
- NUM_CYCLES => 2
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- PULSE_IN => data_valid_o,
- LEVEL_OUT => self_trigger_o
- );
-
+ PROC_ADC_TOKEN_RETURN: process(CLK_IN)
+ variable lower_limit : unsigned(11 downto 0);
+ variable upper_limit : unsigned(11 downto 0);
+
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ adc_tr_average_ctr <= (others => '0');
+ adc_tr_average_sum <= (others => '0');
+ adc_tr_average <= (others => '0');
+
+ adc_tr_error_ctr <= (others => '0');
+ adc_tr_error <= '0';
+ else
+ upper_limit := adc_tr_mean + adc_tr_limit;
+ lower_limit := adc_tr_mean - adc_tr_limit;
+ adc_tr_error <= '0';
+
+ if (adc_tr_data_clk = '1') then
+ if (unsigned(adc_tr_data_p) <= upper_limit and
+ unsigned(adc_tr_data_p) >= lower_limit) then
+ -- Empty token value is O.K., check next one
+ if (unsigned(adc_tr_data_c) > lower_limit) then
+ -- Following Value is not low enough, increase bit shift by one
+ adc_tr_error_ctr <= adc_tr_error_ctr + 1;
+ adc_tr_error_status <= "10";
+ adc_tr_error <= '1';
+ else
+ adc_tr_error_status <= "00";
+ end if;
+ else
+ -- Empty token value is not low enough, decrease bit shift by one
+ adc_tr_error_ctr <= adc_tr_error_ctr + 1;
+ adc_tr_error_status <= "01";
+ adc_tr_error <= '1';
+ end if;
+ end if;
+
+ if (adc_tr_average_ctr srl to_integer(adc_average_divisor) > 0) then
+ adc_tr_average <=
+ (adc_tr_average_sum srl
+ to_integer(adc_average_divisor))(11 downto 0);
+ if (adc_tr_data_clk = '1') then
+ adc_tr_average_sum(11 downto 0) <= unsigned(adc_tr_data_p);
+ adc_tr_average_sum(31 downto 12) <= (others => '0');
+ adc_tr_average_ctr <= x"0001";
+ else
+ adc_tr_average_sum <= (others => '0');
+ adc_tr_average_ctr <= (others => '0');
+ end if;
+ elsif (adc_tr_data_clk = '1') then
+ adc_tr_average_sum <=
+ adc_tr_average_sum + unsigned(adc_tr_data_p);
+ adc_tr_average_ctr <= adc_tr_average_ctr + 1;
+ end if;
+
+ end if;
+ end if;
+ end process PROC_ADC_TOKEN_RETURN;
+
+ PROC_ADC_TOKEN_RETURN_ERROR: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ error_o <= '0';
+ else
+ if (adc_tr_error_rate > x"0000020") then
+ error_o <= '1';
+ else
+ error_o <= '0';
+ end if;
+ end if;
+
+ end if;
+ end process PROC_ADC_TOKEN_RETURN_ERROR;
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
slv_no_more_data_o <= '0';
clear_counters <= '0';
adc_average_divisor <= x"3";
+
+ adc_tr_average_divisor <= x"00";
+ adc_tr_mean <= x"8f2"; -- 2290
+ adc_tr_limit <= x"014"; -- 20
+ adc_tr_debug_mode <= '0';
else
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
-
+
when x"0000" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(invalid_frame_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_hit_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"0001" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(overflow_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_frame_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"0002" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(pileup_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_pileup_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"0003" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(parity_error_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0) <=
+ std_logic_vector(nx_overflow_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"0004" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_hit_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(3 downto 0) <=
+ std_logic_vector(adc_average_divisor);
+ slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_ack_o <= '1';
when x"0005" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0006" =>
- slv_data_out_o(11 downto 0) <= adc_data_last;
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
+
+ when x"0006" =>
+ slv_data_out_o(1 downto 0) <= adc_tr_error_status;
+ slv_data_out_o(31 downto 8) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"0007" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(27 downto 0)
+ <= std_logic_vector(adc_tr_error_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"0008" =>
- slv_data_out_o(3 downto 0) <=
- std_logic_vector(adc_average_divisor);
- slv_data_out_o(31 downto 4) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_average);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_pileup_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_mean);
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"000a" =>
- slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_overflow_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_limit);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000b" =>
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_error_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000c" =>
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(pileup_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000d" =>
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(overflow_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000e" =>
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(invalid_frame_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000f" =>
+ slv_data_out_o(0) <= adc_tr_debug_mode;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end case;
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- clear_counters <= '1';
- slv_ack_o <= '1';
-
- when x"0008" =>
+ clear_counters <= '1';
+ slv_ack_o <= '1';
+
+ when x"0005" =>
adc_average_divisor <= SLV_DATA_IN(3 downto 0);
slv_ack_o <= '1';
-
+
+ when x"0009" =>
+ adc_tr_mean
+ <= unsigned(SLV_DATA_IN(11 downto 0));
+ slv_ack_o <= '1';
+
+ when x"000a" =>
+ adc_tr_limit
+ <= unsigned(SLV_DATA_IN(11 downto 0));
+ slv_ack_o <= '1';
+
+ when x"000f" =>
+ adc_tr_debug_mode <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end case;
else
- slv_ack_o <= '0';
+ slv_ack_o <= '0';
end if;
end if;
end if;
CHANNEL_OUT <= channel_o;
TIMESTAMP_STATUS_OUT <= timestamp_status_o;
ADC_DATA_OUT <= adc_data_o;
- DATA_VALID_OUT <= data_valid_o;
+ DATA_CLK_OUT <= data_clk_o;
NX_TOKEN_RETURN_OUT <= nx_token_return_o;
NX_NOMORE_DATA_OUT <= nx_nomore_data_o;
- SELF_TRIGGER_OUT <= self_trigger_o;
+
+ ERROR_OUT <= error_o;
-- Slave
SLV_DATA_OUT <= slv_data_out_o;
RESET_IN : in std_logic;
NX_MAIN_CLK_IN : in std_logic;
- TIMESTAMP_SYNC_IN : in std_logic;
+ TIMESTAMP_RESET_IN : in std_logic;
+ TIMESTAMP_RESET_OUT : out std_logic;
TRIGGER_IN : in std_logic; -- must be in NX_MAIN_CLK_DOMAIN
TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0);
- TIMESTAMP_SYNCED_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
-- Slave bus
end entity;
architecture Behavioral of nx_fpga_timestamp is
-
- signal timestamp_ctr : unsigned(11 downto 0);
- signal timestamp_current_o : unsigned(11 downto 0);
- signal timestamp_hold_o : std_logic_vector(11 downto 0);
- signal timestamp_trigger_o : std_logic;
- signal timestamp_sync : std_logic;
- signal timestamp_synced : std_logic;
- signal timestamp_synced_o : std_logic;
+ signal timestamp_reset : std_logic;
+ signal timestamp_ctr : unsigned(11 downto 0);
- signal fifo_full : std_logic;
- signal fifo_write_enable : std_logic;
+ signal timestamp_current_o : unsigned(11 downto 0);
+ signal timestamp_hold_o : std_logic_vector(11 downto 0);
+ signal timestamp_trigger_o : std_logic;
+ signal timestamp_reset_o : std_logic;
-- Reset
signal RESET_NX_MAIN_CLK_IN : std_logic;
begin
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= TIMESTAMP_SYNC_IN;
- DEBUG_OUT(2) <= timestamp_synced_o;
+ DEBUG_OUT(1) <= TIMESTAMP_RESET_IN;
+ DEBUG_OUT(2) <= TIMESTAMP_RESET_OUT;
DEBUG_OUT(3) <= TRIGGER_IN;
DEBUG_OUT(15 downto 4) <= timestamp_hold_o(11 downto 0);
port map (
CLK_IN => NX_MAIN_CLK_IN,
RESET_IN => RESET_NX_MAIN_CLK_IN,
- PULSE_A_IN => TIMESTAMP_SYNC_IN,
- PULSE_OUT => timestamp_sync
+ PULSE_A_IN => TIMESTAMP_RESET_IN,
+ PULSE_OUT => timestamp_reset
);
-- Timestamp Process + Trigger
PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN)
begin
- if( rising_edge(NX_MAIN_CLK_IN) ) then
- if( RESET_NX_MAIN_CLK_IN = '1' ) then
+ if (rising_edge(NX_MAIN_CLK_IN)) then
+ if (RESET_NX_MAIN_CLK_IN = '1') then
timestamp_ctr <= (others => '0');
timestamp_hold_o <= (others => '0');
- timestamp_synced <= '0';
+ timestamp_reset_o <= '0';
else
timestamp_trigger_o <= '1';
- timestamp_synced <= '0';
+ timestamp_reset_o <= '0';
- if (timestamp_sync = '1') then
+ if (timestamp_reset = '1') then
timestamp_ctr <= (others => '0');
- timestamp_synced <= '1';
+ timestamp_reset_o <= '1';
else
if (TRIGGER_IN = '1') then
timestamp_hold_o <= std_logic_vector(timestamp_ctr);
-- Output Signals
-----------------------------------------------------------------------------
- pulse_dtrans_1: pulse_dtrans
- generic map (
- CLK_RATIO => 4
- )
- port map (
- CLK_A_IN => NX_MAIN_CLK_IN,
- RESET_A_IN => RESET_NX_MAIN_CLK_IN,
- PULSE_A_IN => timestamp_synced,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => timestamp_synced_o
- );
-
+ TIMESTAMP_RESET_OUT <= timestamp_reset_o;
TIMESTAMP_CURRENT_OUT <= timestamp_current_o;
TIMESTAMP_HOLD_OUT <= timestamp_hold_o;
- TIMESTAMP_SYNCED_OUT <= timestamp_synced_o;
TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o;
end Behavioral;
I2C_DATA_OUT : out std_logic_vector(31 downto 0);
I2C_DATA_BYTES_OUT : out std_logic_vector(31 downto 0);
I2C_LOCK_IN : in std_logic;
-
+
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
DEBUG_OUT(11) <= i2c_busy;
DEBUG_OUT(12) <= sda_o;
DEBUG_OUT(13) <= scl_o;
- DEBUG_OUT(14) <= sda;
- DEBUG_OUT(15) <= scl;
+ DEBUG_OUT(14) <= sda_i;
+ DEBUG_OUT(15) <= scl_i;
--DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28);
-- Start / Stop Sequence
end if;
end if;
end process PROC_I2C_LINES_SYNC;
-
+
PROC_I2C_MASTER_TRANSFER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
when S_IDLE =>
if (i2c_start = '1') then
i2c_data_x <= x"8000_0000"; -- Set Running, clear all
- -- other bits
+ -- other bits
NEXT_STATE <= S_START;
else
i2c_busy_x <= '0';
COMMAND_BUSY_OUT <= command_busy_o;
I2C_DATA_OUT <= i2c_data_internal_o;
I2C_DATA_BYTES_OUT <= i2c_data_internal_bytes_o;
-
+
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
use work.trb_net_components.all;
use work.nxyter_components.all;
-entity nx_setup is
+entity nx_register_setup is
port(
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ I2C_ONLINE_IN : in std_logic;
I2C_COMMAND_OUT : out std_logic_vector(31 downto 0);
I2C_COMMAND_BUSY_IN : in std_logic;
I2C_DATA_IN : in std_logic_vector(31 downto 0);
I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0);
I2C_LOCK_OUT : out std_logic;
- I2C_ONLINE_OUT : out std_logic;
I2C_REG_RESET_IN : in std_logic;
SPI_COMMAND_OUT : out std_logic_vector(31 downto 0);
);
end entity;
-architecture Behavioral of nx_setup is
+architecture Behavioral of nx_register_setup is
-- I2C Command Multiplexer
signal i2c_lock_0 : std_logic;
signal i2c_lock_1 : std_logic;
signal i2c_lock_2 : std_logic;
signal i2c_lock_3 : std_logic;
- signal i2c_lock_4 : std_logic;
signal i2c_command : std_logic_vector(31 downto 0);
-- Send I2C Command
signal adc_token_ctr : unsigned(1 downto 0);
signal adc_read_token_clear : std_logic_vector(3 downto 0);
signal next_token_adc : std_logic;
- signal i2c_lock_4_clear : std_logic;
+ signal i2c_lock_3_clear : std_logic;
-- I2C Online Check
type R_STATES is (R_TIMER_RESTART,
signal wait_timer_start : std_logic;
signal wait_timer_done : std_logic;
- signal i2c_online_command : std_logic_vector(31 downto 0);
- signal i2c_lock_3_clear : std_logic;
- signal i2c_online_o : std_logic;
-- I2C Status
signal i2c_online_t : std_logic_vector(7 downto 0);
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= I2C_COMMAND_BUSY_IN;
DEBUG_OUT(2) <= i2c_command_busy_o;
- DEBUG_OUT(3) <= i2c_error;
+ DEBUG_OUT(3) <= i2c_disable_memory; --i2c_error;
DEBUG_OUT(4) <= i2c_command_done;
DEBUG_OUT(5) <= next_token_dac_r or
next_token_dac_w;
- DEBUG_OUT(6) <= i2c_update_memory;
+ DEBUG_OUT(6) <= i2c_update_memory_r;
DEBUG_OUT(7) <= i2c_lock_0_clear;
DEBUG_OUT(8) <= i2c_lock_1_clear;
DEBUG_OUT(9) <= i2c_lock_2_clear;
- DEBUG_OUT(10) <= i2c_lock_4_clear;
- DEBUG_OUT(11) <= i2c_online_o;
+ DEBUG_OUT(10) <= i2c_lock_3_clear;
+ DEBUG_OUT(11) <= i2c_command(31);
DEBUG_OUT(12) <= i2c_lock_0;
DEBUG_OUT(13) <= i2c_lock_1;
DEBUG_OUT(14) <= i2c_lock_2;
- DEBUG_OUT(15) <= i2c_lock_4;
+ DEBUG_OUT(15) <= i2c_lock_3;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
PROC_I2C_COMMAND_MULTIPLEXER: process(CLK_IN)
- variable locks : std_logic_vector(4 downto 0) := (others => '0');
+ variable locks : std_logic_vector(3 downto 0) := (others => '0');
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
i2c_lock_1 <= '0';
i2c_lock_2 <= '0';
i2c_lock_3 <= '0';
- i2c_lock_4 <= '0';
i2c_command <= (others => '0');
else
i2c_command <= (others => '0');
- locks := i2c_lock_4 & i2c_lock_3 &
- i2c_lock_2 & i2c_lock_1 &
- i2c_lock_0;
+ locks := i2c_lock_3 & i2c_lock_2 &
+ i2c_lock_1 & i2c_lock_0;
-- Clear Locks
if (i2c_lock_0_clear = '1') then
if (i2c_lock_3_clear = '1') then
i2c_lock_3 <= '0';
end if;
- if (i2c_lock_4_clear = '1') then
- i2c_lock_4 <= '0';
- end if;
if (i2c_command_busy_o = '0') then
- if (nx_i2c_command(31) = '1' and
- ((locks and "11110") = "00000") and
+ if (nx_i2c_command(31) = '1' and
+ ((locks and "1110") = "0000") and
i2c_lock_0_clear = '0') then
i2c_command <= nx_i2c_command;
i2c_lock_0 <= '1';
- elsif (dac_write_i2c_command(31) = '1' and
- ((locks and "11011") = "00000") and
+ elsif (dac_write_i2c_command(31) = '1' and
+ ((locks and "1011") = "0000") and
i2c_lock_2_clear = '0') then
i2c_command <= dac_write_i2c_command;
i2c_lock_2 <= '1';
- elsif (dac_read_i2c_command(31) = '1' and
- ((locks and "11101") = "00000") and
+ elsif (dac_read_i2c_command(31) = '1' and
+ ((locks and "1101") = "0000") and
i2c_lock_1_clear = '0') then
i2c_command <= dac_read_i2c_command;
i2c_lock_1 <= '1';
- elsif (i2c_online_command(31) = '1' and
- ((locks and "10111") = "00000") and
- i2c_lock_3_clear = '0') then
- i2c_command <= i2c_online_command;
- i2c_lock_3 <= '1';
- elsif (adc_i2c_command(31) = '1' and
- ((locks and "01111") = "00000") and
- i2c_lock_4_clear = '0') then
+ elsif (adc_i2c_command(31) = '1' and
+ ((locks and "0111") = "0000") and
+ i2c_lock_3_clear = '0') then
i2c_command <= adc_i2c_command;
- i2c_lock_4 <= '1';
+ i2c_lock_3 <= '1';
end if;
end if;
end if;
adc_token_ctr <= (others => '0');
next_token_adc <= '0';
adc_read_token_clear <= (others => '0');
- i2c_lock_4_clear <= '0';
+ i2c_lock_3_clear <= '0';
ADC_STATE <= ADC_IDLE_TOKEN;
else
index := to_integer(unsigned(adc_token_ctr));
adc_i2c_command <= (others => '0');
next_token_adc <= '0';
adc_read_token_clear <= (others => '0');
- i2c_lock_4_clear <= '0';
+ i2c_lock_3_clear <= '0';
case ADC_STATE is
when "11" => adc_i2c_command(15 downto 8) <= x"80";
end case;
adc_i2c_command(7 downto 0) <= (others => '0');
- if (i2c_lock_4 = '0') then
+ if (i2c_lock_3 = '0') then
ADC_STATE <= ADC_READ_I2C_REGISTER;
else
adc_read_token_clear(index) <= '1';
else
adc_ram(index) <= (others => '1');
end if;
- i2c_lock_4_clear <= '1';
+ i2c_lock_3_clear <= '1';
ADC_STATE <= ADC_NEXT_TOKEN;
-- Next Token
TIMER_DONE_OUT => wait_timer_done
);
- PROC_I2C_ONLINE: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- i2c_online_command <= (others => '0');
- i2c_online_o <= '0';
- i2c_lock_3_clear <= '0';
- wait_timer_start <= '0';
- R_STATE <= R_TIMER_RESTART;
- else
- i2c_online_command <= (others => '0');
- i2c_lock_3_clear <= '0';
- wait_timer_start <= '0';
-
- case R_STATE is
-
- when R_TIMER_RESTART =>
- wait_timer_start <= '1';
- R_STATE <= R_IDLE;
-
- when R_IDLE =>
- if (wait_timer_done = '1') then
- R_STATE <= R_READ_DUMMY;
- else
- R_STATE <= R_IDLE;
- end if;
-
- when R_READ_DUMMY =>
- i2c_online_command(31 downto 16) <= x"c108";
- i2c_online_command(15 downto 8) <= x"1f"; -- Dummy register
- i2c_online_command(7 downto 0) <= (others => '0');
- if (i2c_lock_3 = '0') then
- R_STATE <= R_READ_DUMMY;
- else
- R_STATE <= R_WAIT_DONE;
- end if;
-
- when R_WAIT_DONE =>
- if (i2c_command_done = '0') then
- R_STATE <= R_WAIT_DONE;
- else
- i2c_online_o <= not i2c_error;
- i2c_lock_3_clear <= '1';
- R_STATE <= R_TIMER_RESTART;
- end if;
-
- end case;
-
- end if;
- end if;
- end process PROC_I2C_ONLINE;
-
PROC_I2C_STATUS: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
i2c_reg_reset_clear <= '0';
-- Shift Online
- i2c_online_t(0) <= i2c_online_o;
+ i2c_online_t(0) <= I2C_ONLINE_IN;
for I in 1 to 7 loop
i2c_online_t(I) <= i2c_online_t(I - 1);
end loop;
when x"0056" =>
-- I2C Online
- int_data_o(0) <= i2c_online_o;
+ int_data_o(0) <= I2C_ONLINE_IN;
int_data_o(31 downto 2) <= (others => '0');
int_ack_o <= '1';
dac_ram_write_0 <= '0';
dac_read_token_r <= (others => '0');
adc_read_token_r <= (others => '0');
- i2c_update_memory_r <= '0';
+ i2c_update_memory_r <= '0';
nxyter_clock <= (others => '0');
nxyter_polarity <= (others => '0');
nxyter_testtrigger <= (others => '0');
when x"0056" =>
-- I2C Online
- slv_data_out_o(0) <= i2c_online_o;
+ slv_data_out_o(0) <= I2C_ONLINE_IN;
slv_data_out_o(31 downto 2) <= (others => '0');
slv_ack_o <= '1';
I2C_COMMAND_OUT <= i2c_command_o;
I2C_LOCK_OUT <= i2c_command_busy_o;
- I2C_ONLINE_OUT <= i2c_online_o;
SPI_COMMAND_OUT <= (others => '0');
SPI_LOCK_OUT <= '0';
library work;
use work.nxyter_components.all;
-entity nx_control is
+entity nx_status is
port(
CLK_IN : in std_logic;
RESET_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
PLL_ADC_SCLK_LOCK_IN : in std_logic;
-
+ PLL_RESET_OUT : out std_logic;
+
-- Signals
- I2C_SM_RESET_OUT : out std_logic;
+ I2C_SM_RESET_OUT : inout std_logic;
I2C_REG_RESET_OUT : out std_logic;
NX_TS_RESET_OUT : out std_logic;
- I2C_ONLINE_IN : in std_logic;
- OFFLINE_OUT : out std_logic;
+ NX_ONLINE_OUT : out std_logic;
-- Error
ERROR_ALL_IN : in std_logic_vector(7 downto 0);
);
end entity;
-architecture Behavioral of nx_control is
+architecture Behavioral of nx_status is
-- Offline Handler
- signal offline_force_internal : std_logic;
+
+ signal i2c_sm_reset_i_x : std_logic;
+ signal i2c_sm_reset_i : std_logic;
+ signal i2c_sm_online : std_logic;
+ signal i2c_sm_online_ctr : unsigned(8 downto 0);
+
signal offline_force : std_logic;
- signal offline_o : std_logic;
- signal offline_on : std_logic;
- signal online_on : std_logic;
- signal offline_last : std_logic;
-
+ signal online_o : std_logic;
+ signal online_trigger : std_logic;
+ signal online_last : std_logic;
+
-- I2C Reset
signal i2c_sm_reset_start : std_logic;
signal i2c_reg_reset_start : std_logic;
signal i2c_sm_reset_o : std_logic;
signal i2c_reg_reset_o : std_logic;
signal nx_ts_reset_o : std_logic;
-
+
type STATES is (S_IDLE,
S_I2C_SM_RESET,
signal pll_adc_sclk_notlock_ctr : unsigned(15 downto 0);
signal clear_notlock_counters : std_logic;
+ signal pll_reset_o : std_logic;
-- Nxyter Data Clock
signal nx_data_clk_dphase_o : std_logic_vector(3 downto 0);
DEBUG_OUT(9) <= pll_adc_sclk_lock;
- DEBUG_OUT(10) <= I2C_ONLINE_IN;
+ DEBUG_OUT(10) <= i2c_sm_online;
DEBUG_OUT(11) <= offline_force;
- DEBUG_OUT(12) <= offline_force_internal;
- DEBUG_OUT(13) <= offline_o;
- DEBUG_OUT(14) <= online_on;
- DEBUG_OUT(15) <= '0';
+ DEBUG_OUT(12) <= online_o;
+ DEBUG_OUT(13) <= i2c_sm_reset_i;
+ DEBUG_OUT(14) <= pll_reset_o;
+ DEBUG_OUT(15) <= online_trigger;
timer_1: timer
generic map (
-- Offline Handler
-----------------------------------------------------------------------------
- offline_force_internal <= '0';
+ signal_async_trans_i2c_sm_reset_i: signal_async_trans
+ port map (
+ CLK_IN => CLK_IN,
+ SIGNAL_A_IN => i2c_sm_reset_i_x,
+ SIGNAL_OUT => i2c_sm_reset_i
+ );
+
+ PROC_I2C_OFFLINE_SCHMITT_TRIGGER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ i2c_sm_online <= '0';
+ i2c_sm_online_ctr <= (others => '0');
+ else
+ if (i2c_sm_reset_i = '1') then
+ if (i2c_sm_online_ctr < x"1ff") then
+ i2c_sm_online_ctr <= i2c_sm_online_ctr + 1;
+ end if;
+ else
+ if (i2c_sm_online_ctr > x"000") then
+ i2c_sm_online_ctr <= i2c_sm_online_ctr - 1;
+ end if;
+ end if;
+ if (i2c_sm_online_ctr > x"1d6") then
+ i2c_sm_online <= '1';
+ elsif (i2c_sm_online_ctr < x"01e") then
+ i2c_sm_online <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_I2C_OFFLINE_SCHMITT_TRIGGER;
+
PROC_NXYTER_OFFLINE: process(CLK_IN)
- variable offline_state : std_logic_vector(1 downto 0) := "00";
+ variable online_state : std_logic_vector(1 downto 0) := "00";
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- offline_on <= '0';
- online_on <= '0';
- offline_o <= '1';
- offline_last <= '0';
+ online_trigger <= '0';
+ online_o <= '1';
+ online_last <= '0';
else
- if (offline_force = '1' or offline_force_internal = '1') then
- offline_o <= '1';
+ if (i2c_sm_online = '1' and offline_force = '0') then
+ online_o <= '1';
else
- offline_o <= not I2C_ONLINE_IN;
+ online_o <= '0';
end if;
-- Offline State changes
- offline_on <= '0';
- online_on <= '0';
- offline_last <= offline_o;
- offline_state := offline_o & offline_last;
+ online_last <= online_o;
+ online_state := online_o & online_last;
- case offline_state is
- when "01" =>
- offline_on <= '1';
-
- when "10" =>
- online_on <= '0';
+ case online_state is
+ when "01" | "10" =>
+ online_trigger <= '1';
- when others => null;
+ when others =>
+ online_trigger <= '0';
end case;
end if;
end if;
nx_data_clk_dphase_o <= x"7";
nx_data_clk_finedelb_o <= x"0";
clear_notlock_counters <= '0';
+ pll_reset_o <= '0';
else
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
i2c_reg_reset_start <= '0';
nx_ts_reset_start <= '0';
clear_notlock_counters <= '0';
+ pll_reset_o <= '0';
if (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
offline_force <= SLV_DATA_IN(0);
slv_ack_o <= '1';
+ when x"0006" =>
+ pll_reset_o <= '1';
+ slv_ack_o <= '1';
+
when x"000a" =>
clear_notlock_counters <= '1';
slv_ack_o <= '1';
elsif (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
+ when x"0000" =>
+ slv_data_out_o(0) <= i2c_sm_reset_i;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
when x"0003" =>
slv_data_out_o(0) <= offline_force;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
when x"0004" =>
- slv_data_out_o(0) <= I2C_ONLINE_IN;
+ slv_data_out_o(0) <= i2c_sm_online;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
when x"0005" =>
- slv_data_out_o(0) <= offline_o;
+ slv_data_out_o(0) <= online_o;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
end process PROC_NX_REGISTERS;
-- Output Signals
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
+ i2c_sm_reset_i_x <= I2C_SM_RESET_OUT;
+
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
+
+ PLL_RESET_OUT <= pll_reset_o;
+ I2C_SM_RESET_OUT <= '0' when i2c_sm_reset_o = '1' else 'Z';
+ I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
+ NX_TS_RESET_OUT <= nx_ts_reset_o;
+ NX_ONLINE_OUT <= online_o;
- I2C_SM_RESET_OUT <= i2c_sm_reset_o;
- I2C_REG_RESET_OUT <= i2c_reg_reset_o;
- NX_TS_RESET_OUT <= nx_ts_reset_o;
- OFFLINE_OUT <= offline_o;
-
end Behavioral;
entity nx_status_event is
generic (
- BOARD_ID : std_logic_vector(1 downto 0) := "11"
+ BOARD_ID : std_logic_vector(1 downto 0) := "11";
+ VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1"
);
port (
CLK_IN : in std_logic;
-- Event Write
type E_STATES is (E_IDLE,
+ E_HEADER,
E_READ_NEXT,
E_READ,
E_NEXT_INDEX,
+ E_TRAILER,
E_END
);
when E_IDLE =>
index_ctr <= (others => '0');
if (event_write_start = '1') then
- E_STATE <= E_NEXT_INDEX;
+ E_STATE <= E_HEADER;
else
E_STATE <= E_IDLE;
end if;
-
+
+ when E_HEADER =>
+ fee_data_o(25 downto 0) <= (others => '1');
+ fee_data_o(29 downto 26) <= VERSION_NUMBER;
+ fee_data_o(31 downto 30) <= BOARD_ID;
+ fee_data_write_o <= '1';
+ E_STATE <= E_NEXT_INDEX;
+
when E_READ_NEXT =>
if (register_addr <= unsigned(reg_addr_end(index))) then
int_addr_o <= register_addr;
register_addr <= reg_addr_start(index);
E_STATE <= E_READ_NEXT;
else
- E_STATE <= E_END;
+ E_STATE <= E_TRAILER;
end if;
+ when E_TRAILER =>
+ fee_data_o <= (others => '1');
+ fee_data_write_o <= '1';
+ E_STATE <= E_END;
+
when E_END =>
event_write_done <= '1';
E_STATE <= E_IDLE;
end if;
end process PROC_NX_TIMESTAMP;
--- Gray_Encoder_1: Gray_Encoder
+-- gray_Encoder_1: gray_Encoder
-- generic map (
-- WIDTH => 8
-- )
RESET_IN : in std_logic;
NX_MAIN_CLK_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
+
TRIGGER_IN : in std_logic; -- must be in NX_MAIN_CLK_DOMAIN
TRIGGER_OUT : out std_logic;
TS_RESET_OUT : out std_logic;
TESTPULSE_OUT : out std_logic;
- TEST_IN : in std_logic_vector(31 downto 0);
-
+
+ TIMESTAMP_IN : in std_logic_vector(31 downto 0);
+ ADC_DATA_IN : in std_logic_vector(11 downto 0);
+ NEW_DATA_IN : in std_logic;
+ SELF_TRIGGER_OUT : out std_logic;
+
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
signal testpulse_rate_t : unsigned(27 downto 0);
signal rate_timer : unsigned(27 downto 0);
+ -- Self Trigger
+
+ type ST_STATES is (ST_IDLE,
+ ST_BUSY
+ );
+ signal ST_STATE : ST_STATES;
+
+ signal self_trigger_ctr : unsigned(4 downto 0);
+ signal self_trigger_busy : std_logic;
+ signal self_trigger : std_logic;
+ signal self_trigger_o : std_logic;
+
-- TRBNet Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal reg_ts_reset_on : std_logic;
signal testpulse_rate : unsigned(27 downto 0);
- signal test_debug : std_logic;
-
-- Reset
signal RESET_NX_MAIN_CLK_IN : std_logic;
begin
-- Debug Line
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= '0';--TRIGGER_IN;
- DEBUG_OUT(2) <= '0';
- DEBUG_OUT(3) <= start_cycle;
- DEBUG_OUT(4) <= '0';--wait_timer_done;
- DEBUG_OUT(5) <= ts_reset_o;
- DEBUG_OUT(6) <= testpulse_o_b;
- DEBUG_OUT(7) <= testpulse;
- DEBUG_OUT(8) <= test_debug;
- DEBUG_OUT(15 downto 9) <= (others => '0');
-
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= NEW_DATA_IN;
+ DEBUG_OUT(2) <= start_cycle;
+ DEBUG_OUT(3) <= ts_reset_o;
+ DEBUG_OUT(4) <= testpulse_o_b;
+ DEBUG_OUT(5) <= testpulse;
+ DEBUG_OUT(6) <= self_trigger;
+ DEBUG_OUT(7) <= self_trigger_o;
+ DEBUG_OUT(8) <= self_trigger_busy;
+ DEBUG_OUT(9) <= TRIGGER_BUSY_IN;
+ DEBUG_OUT(15 downto 10) <= (others => '0');
+
-----------------------------------------------------------------------------
-- Reset Domain Transfer
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
- PROC_TEST_DEBUG: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- test_debug <= '0';
- else
- if (TEST_IN = x"7f7f7f06" or TEST_IN = x"0000_0000") then
- test_debug <= '0';
- else
- test_debug <= '1';
- end if;
- end if;
- end if;
- end process PROC_TEST_DEBUG;
-
-- Timer
timer_1: timer
generic map (
end if;
end process PROC_CAL_RATES;
+ -----------------------------------------------------------------------------
+ -- Self Trigger
+ -----------------------------------------------------------------------------
+
+ PROC_SELF_TRIGGER: process(CLK_IN)
+ variable frame_bits : std_logic_vector(3 downto 0);
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ self_trigger_ctr <= (others => '0');
+ self_trigger_busy <= '0';
+ self_trigger <= '0';
+ else
+ frame_bits := TIMESTAMP_IN(31) &
+ TIMESTAMP_IN(23) &
+ TIMESTAMP_IN(15) &
+ TIMESTAMP_IN(7);
+ self_trigger <= '0';
+ self_trigger_busy <= '0';
+
+ case ST_STATE is
+ when ST_IDLE =>
+ if (TRIGGER_BUSY_IN = '0' and
+ NEW_DATA_IN = '1' and
+ frame_bits = "1000") then
+ self_trigger_ctr <= "10100"; -- 20
+ self_trigger <= '1';
+ ST_STATE <= ST_BUSY;
+ else
+ self_trigger_ctr <= (others => '0');
+ ST_STATE <= ST_IDLE;
+ end if;
+
+ when ST_BUSY =>
+ if (self_trigger_ctr > 0) then
+ self_trigger_ctr <= self_trigger_ctr - 1;
+ self_trigger_busy <= '1';
+ ST_STATE <= ST_BUSY;
+ else
+ ST_STATE <= ST_IDLE;
+ end if;
+ end case;
+
+ end if;
+ end if;
+ end process PROC_SELF_TRIGGER;
+
+ pulse_to_level_SELF_TRIGGER: pulse_to_level
+ generic map (
+ NUM_CYCLES => 8
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ PULSE_IN => self_trigger,
+ LEVEL_OUT => self_trigger_o
+ );
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
TRIGGER_OUT <= trigger_o;
TS_RESET_OUT <= ts_reset_o;
TESTPULSE_OUT <= testpulse_o_b;
-
+ SELF_TRIGGER_OUT <= self_trigger_o;
+
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
case STATE is
when S_IDLE =>
if (LVL1_VALID_NOTIMING_TRG_IN = '1') then
- -- Calibration Trigger .. ignore
- TRIGGER_TYPE <= T_IGNORE; --T_SETUP;
+ -- Calibration Trigger
+ if (LVL1_TRG_TYPE_IN = x"e") then
+ -- Status Trigger
+ TRIGGER_TYPE <= T_SETUP;
+ status_trigger_o <= '1';
+ else
+ -- Something else, Ignore
+ TRIGGER_TYPE <= T_IGNORE;
+ end if;
STATE <= S_WAIT_TRG_DATA_VALID;
elsif (LVL1_VALID_TIMING_TRG_IN = '1') then
end if;
when S_WAIT_TIMING_TRIGGER_DONE =>
- if (TRIGGER_BUSY_0_IN = '1') then
+ if ((TRIGGER_TYPE = T_TIMING and TRIGGER_BUSY_0_IN = '1') or
+ (TRIGGER_TYPE = T_SETUP and TRIGGER_BUSY_1_IN = '1')
+ ) then
STATE <= S_WAIT_TIMING_TRIGGER_DONE;
else
fee_data_finished_o <= '1';
entity nx_trigger_validate is
generic (
- BOARD_ID : std_logic_vector(1 downto 0) := "11"
+ BOARD_ID : std_logic_vector(1 downto 0) := "11";
+ VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1"
);
port (
CLK_IN : in std_logic;
DATA_CLK_IN : in std_logic;
TIMESTAMP_IN : in std_logic_vector(13 downto 0);
CHANNEL_IN : in std_logic_vector(6 downto 0);
- TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); -- 2: parity
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: pileup
- NX_TOKEN_RETURN_IN : in std_logic; -- 0: ovfl
+ TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); -- 2: Parity Err
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: Pileup
+ NX_TOKEN_RETURN_IN : in std_logic; -- 0: Ovfl
NX_NOMORE_DATA_IN : in std_logic;
TRIGGER_IN : in std_logic;
end entity;
architecture Behavioral of nx_trigger_validate is
- constant VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1";
+
constant S_PARITY : integer := 2;
constant S_PILEUP : integer := 1;
signal out_of_window_error_ctr : unsigned(15 downto 0);
signal readout_mode : std_logic_vector(3 downto 0);
+ signal timestamp_fpga_i : unsigned(11 downto 0);
signal timestamp_fpga : unsigned(11 downto 0);
signal timestamp_ref : unsigned(11 downto 0);
signal busy_time_ctr_last : unsigned(11 downto 0);
begin
-- Debug Line
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= TRIGGER_IN;
- DEBUG_OUT(2) <= trigger_busy_o;
- DEBUG_OUT(3) <= DATA_CLK_IN;
- DEBUG_OUT(4) <= out_of_window_l;
- DEBUG_OUT(5) <= out_of_window_h;
- DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN;
- DEBUG_OUT(7) <= NX_NOMORE_DATA_IN;
- DEBUG_OUT(8) <= channel_all_done;
- DEBUG_OUT(9) <= store_to_fifo;
- DEBUG_OUT(10) <= data_clk_o;
- DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
- DEBUG_OUT(12) <= token_update; --TRIGGER_BUSY_IN; --wait_timer_done;
- DEBUG_OUT(13) <= min_val_time_expired;
- DEBUG_OUT(14) <= token_update;
- DEBUG_OUT(15) <= nomore_data_o;
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= TRIGGER_IN;
+ DEBUG_OUT(2) <= trigger_busy_o;
+ DEBUG_OUT(3) <= DATA_CLK_IN;
+ DEBUG_OUT(4) <= out_of_window_l;
+ DEBUG_OUT(5) <= out_of_window_h;
+ DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN;
+ DEBUG_OUT(7) <= NX_NOMORE_DATA_IN;
+ DEBUG_OUT(8) <= channel_all_done;
+ DEBUG_OUT(9) <= store_to_fifo;
+ DEBUG_OUT(10) <= data_clk_o;
+ DEBUG_OUT(11) <= out_of_window_error or EVT_BUFFER_FULL_IN;
+ DEBUG_OUT(12) <= TIMESTAMP_STATUS_IN(S_PARITY);-- token_update; --TRIGGER_BUSY_IN; --wait_timer_done;
+ DEBUG_OUT(13) <= min_val_time_expired;
+ DEBUG_OUT(14) <= token_update;
+ DEBUG_OUT(15) <= nomore_data_o;
-- Timer
timer_1: timer
end if;
end if;
- --TS Window Disabled, always store data
+ -- TS Window Disabled, always store data
if (readout_mode(2) = '1' or
self_trigger_mode = '1') then
store_data := '1';
variable min_validation_time : unsigned(19 downto 0);
begin
if( rising_edge(CLK_IN) ) then
+ timestamp_fpga_i <= TIMESTAMP_FPGA_IN;
if (RESET_IN = '1' or FAST_CLEAR_IN = '1') then
store_to_fifo <= '0';
trigger_busy_o <= '0';
if (wait_timer_done_ns = '0') then
STATE <= S_WAIT_DATA;
else
- timestamp_fpga <=
- TIMESTAMP_FPGA_IN + fpga_timestamp_offset;
- timestamp_ref <= timestamp_fpga;
+ -- If Self-Trigger-Mode active set TS Ref to zero
+ if (self_trigger_mode = '1') then
+ timestamp_fpga <= (others => '0');
+ else
+ timestamp_fpga <=
+ timestamp_fpga_i + fpga_timestamp_offset;
+ timestamp_ref <= timestamp_fpga;
+ end if;
STATE <= S_WRITE_HEADER;
end if;
when x"0001" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(ts_window_offset(11 downto 0));
- slv_data_out_o(31 downto 11) <= (others => '0');
+ if (ts_window_offset(11) = '1') then
+ slv_data_out_o(31 downto 12) <= (others => '1');
+ else
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ end if;
slv_ack_o <= '1';
when x"0002" =>
slv_ack_o <= '1';
when x"0001" =>
- if ((signed(SLV_DATA_IN(11 downto 0)) > -1024) and
- (signed(SLV_DATA_IN(11 downto 0)) < 1024)) then
+ if ((signed(SLV_DATA_IN(11 downto 0)) > -2048) and
+ (signed(SLV_DATA_IN(11 downto 0)) < 2048)) then
ts_window_offset(11 downto 0) <=
signed(SLV_DATA_IN(11 downto 0));
end if;
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
NX_DATA_CLK_TEST_IN : in std_logic;
+ PLL_RESET_OUT : in std_logic;
TRIGGER_OUT : out std_logic;
I2C_SDA_INOUT : inout std_logic;
I2C_SCL_INOUT : inout std_logic;
- I2C_SM_RESET_OUT : out std_logic;
+ I2C_SM_RESET_OUT : inout std_logic;
I2C_REG_RESET_OUT : out std_logic;
SPI_SCLK_OUT : out std_logic;
SPI_SDIO_INOUT : inout std_logic;
-- TRBNet Registers
-------------------------------------------------------------------------------
-component nx_setup
+component nx_register_setup
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ I2C_ONLINE_IN : in std_logic;
I2C_COMMAND_OUT : out std_logic_vector(31 downto 0);
I2C_COMMAND_BUSY_IN : in std_logic;
I2C_DATA_IN : in std_logic_vector(31 downto 0);
I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0);
I2C_LOCK_OUT : out std_logic;
- I2C_ONLINE_OUT : out std_logic;
I2C_REG_RESET_IN : in std_logic;
SPI_COMMAND_OUT : out std_logic_vector(31 downto 0);
SPI_COMMAND_BUSY_IN : in std_logic;
);
end component;
-component nx_control
+component nx_status
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
PLL_ADC_SCLK_LOCK_IN : in std_logic;
- I2C_SM_RESET_OUT : out std_logic;
+ PLL_RESET_OUT : out std_logic;
+ I2C_SM_RESET_OUT : inout std_logic;
I2C_REG_RESET_OUT : out std_logic;
NX_TS_RESET_OUT : out std_logic;
- I2C_ONLINE_IN : in std_logic;
- OFFLINE_OUT : out std_logic;
+ NX_ONLINE_OUT : out std_logic;
ERROR_ALL_IN : in std_logic_vector(7 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
component nx_data_receiver
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- NX_DATA_CLK_TEST_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- NX_TIMESTAMP_CLK_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- ADC_CLK_DAT_IN : in std_logic;
- ADC_FCLK_IN : in std_logic_vector(1 downto 0);
- ADC_DCLK_IN : in std_logic_vector(1 downto 0);
- ADC_SAMPLE_CLK_OUT : out std_logic;
- ADC_A_IN : in std_logic_vector(1 downto 0);
- ADC_B_IN : in std_logic_vector(1 downto 0);
- ADC_NX_IN : in std_logic_vector(1 downto 0);
- ADC_D_IN : in std_logic_vector(1 downto 0);
- ADC_SCLK_LOCK_OUT : out std_logic;
- NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
- ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- NEW_DATA_OUT : out std_logic;
- TIMESTAMP_CURRENT_IN : in unsigned(11 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- ERROR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NX_DATA_CLK_TEST_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_TIMESTAMP_RESET_OUT : out std_logic;
+ ADC_CLK_DAT_IN : in std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SAMPLE_CLK_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
+ ADC_SCLK_LOCK_OUT : out std_logic;
+ NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
+ ADC_DATA_OUT : out std_logic_vector(11 downto 0);
+ NEW_DATA_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ ERROR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
RESET_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0);
ADC_DATA_IN : in std_logic_vector(11 downto 0);
- NEW_DATA_IN : in std_logic;
+ DATA_CLK_IN : in std_logic;
TIMESTAMP_OUT : out std_logic_vector(13 downto 0);
CHANNEL_OUT : out std_logic_vector(6 downto 0);
TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- DATA_VALID_OUT : out std_logic;
- SELF_TRIGGER_OUT : out std_logic;
+ DATA_CLK_OUT : out std_logic;
NX_TOKEN_RETURN_OUT : out std_logic;
NX_NOMORE_DATA_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ ERROR_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
component nx_trigger_validate
generic (
- BOARD_ID : std_logic_vector(1 downto 0)
+ BOARD_ID : std_logic_vector(1 downto 0);
+ VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1"
);
port (
CLK_IN : in std_logic;
component nx_status_event
generic (
- BOARD_ID : std_logic_vector(1 downto 0));
+ BOARD_ID : std_logic_vector(1 downto 0);
+ VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1"
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
component pll_nx_clk250
port (
CLK : in std_logic;
+ RESET : in std_logic;
CLKOP : out std_logic;
CLKOK : out std_logic;
LOCK : out std_logic
component pll_adc_clk
port (
CLK : in std_logic;
+ RESET : in std_logic;
CLKOP : out std_logic;
LOCK : out std_logic
);
CLK_IN : in std_logic;
RESET_IN : in std_logic;
NX_MAIN_CLK_IN : in std_logic;
- TIMESTAMP_SYNC_IN : in std_logic;
+ TIMESTAMP_RESET_IN : in std_logic;
+ TIMESTAMP_RESET_OUT : out std_logic;
TRIGGER_IN : in std_logic;
TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0);
- TIMESTAMP_SYNCED_OUT : out std_logic;
TIMESTAMP_TRIGGER_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
NX_MAIN_CLK_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
TRIGGER_IN : in std_logic;
TRIGGER_OUT : out std_logic;
TS_RESET_OUT : out std_logic;
TESTPULSE_OUT : out std_logic;
- TEST_IN : in std_logic_vector(31 downto 0);
+ TIMESTAMP_IN : in std_logic_vector(31 downto 0);
+ ADC_DATA_IN : in std_logic_vector(11 downto 0);
+ NEW_DATA_IN : in std_logic;
+ SELF_TRIGGER_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
PLL_NX_CLK_LOCK_IN : in std_logic;
PLL_ADC_DCLK_LOCK_IN : in std_logic;
NX_DATA_CLK_TEST_IN : in std_logic;
+ PLL_RESET_OUT : out std_logic;
TRIGGER_OUT : out std_logic;
-- I2C Ports
I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
- I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine
+ I2C_SM_RESET_OUT : inout std_logic; -- reset nXyter I2C SMachine
I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers
-- ADC SPI
architecture Behavioral of nXyter_FEE_board is
-
+ -- Data Format Version
+ constant VERSION_NUMBER : std_logic_vector(3 downto 0) := x"1";
+
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-
+
-- Bus Handler
constant NUM_PORTS : integer := 13;
signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0);
-- TRB Register
- signal i2c_sm_reset_o : std_logic;
- signal nx_ts_reset_1 : std_logic;
- signal nx_ts_reset_2 : std_logic;
- signal nx_ts_reset_o : std_logic;
+ signal nx_timestamp_reset_1 : std_logic;
+ signal nx_timestamp_reset_2 : std_logic;
+ signal nx_timestamp_reset_3 : std_logic;
+ signal nx_timestamp_reset : std_logic;
+ signal nx_timestamp_reset_o : std_logic;
signal i2c_reg_reset_o : std_logic;
- signal nxyter_offline : std_logic;
+ signal nxyter_online : std_logic;
-- NX Register Access
signal i2c_lock : std_logic;
signal spi_command : std_logic_vector(31 downto 0);
signal spi_command_busy : std_logic;
signal spi_data : std_logic_vector(31 downto 0);
- signal nxyter_online_i2c : std_logic;
-
+
-- SPI Interface ADC
signal spi_sdi : std_logic;
signal spi_sdo : std_logic;
-- Data Receiver
- signal adc_data_valid : std_logic;
- signal adc_new_data : std_logic;
+ signal timestamp_recv : std_logic_vector(31 downto 0);
+ signal adc_data_recv : std_logic_vector(11 downto 0);
+ signal data_clk_recv : std_logic;
signal self_trigger : std_logic;
- signal new_timestamp : std_logic_vector(31 downto 0);
- signal new_adc_data : std_logic_vector(11 downto 0);
- signal new_data : std_logic;
signal pll_sadc_clk_lock : std_logic;
-- Data Delay
- signal new_timestamp_delayed : std_logic_vector(31 downto 0);
- signal new_adc_data_delayed : std_logic_vector(11 downto 0);
- signal new_data_delayed : std_logic;
- signal new_data_fifo_delay : std_logic_vector(7 downto 0);
+ signal timestamp_delayed : std_logic_vector(31 downto 0);
+ signal adc_data_delayed : std_logic_vector(11 downto 0);
+ signal data_clk_delayed : std_logic;
+ signal data_fifo_delay : std_logic_vector(7 downto 0);
-- Data Validate
signal timestamp : std_logic_vector(13 downto 0);
signal timestamp_channel_id : std_logic_vector(6 downto 0);
signal timestamp_status : std_logic_vector(2 downto 0);
signal adc_data : std_logic_vector(11 downto 0);
- signal data_valid : std_logic;
+ signal data_clk : std_logic;
signal nx_token_return : std_logic;
signal nx_nomore_data : std_logic;
-- FPGA Timestamp
signal timestamp_current : unsigned(11 downto 0);
signal timestamp_hold : unsigned(11 downto 0);
- signal nx_timestamp_sync : std_logic;
signal nx_timestamp_trigger_o : std_logic;
-- Trigger Generator
-- Error
signal error_all : std_logic_vector(7 downto 0);
signal error_data_receiver : std_logic;
+ signal error_data_validate : std_logic;
signal error_event_buffer : std_logic;
-- Debug Handler
-- Errors
-------------------------------------------------------------------------------
error_all(0) <= error_data_receiver;
- error_all(1) <= error_event_buffer;
- error_all(7 downto 2) <= (others => '0');
+ error_all(1) <= error_data_validate;
+ error_all(2) <= error_event_buffer;
+ error_all(7 downto 3) <= (others => '0');
-------------------------------------------------------------------------------
-- Port Maps
generic map(
PORT_NUMBER => NUM_PORTS,
- PORT_ADDRESSES => ( 0 => x"0100", -- NX Control Handler
+ PORT_ADDRESSES => ( 0 => x"0100", -- NX Status Handler
1 => x"0040", -- I2C Master
2 => x"0500", -- Data Receiver
3 => x"0600", -- Data Buffer
6 => x"0120", -- Data Validate
7 => x"0160", -- Trigger Handler
8 => x"0400", -- Trigger Validate
- 9 => x"0200", -- NX Setup
+ 9 => x"0200", -- NX Register Setup
10 => x"0800", -- NX Histograms
11 => x"0020", -- Debug Handler
- 12 => x"0130", -- Data Delay
+ 12 => x"0180", -- Data Delay
others => x"0000"
),
- PORT_ADDR_MASK => ( 0 => 4, -- NX Control Handler
+ PORT_ADDR_MASK => ( 0 => 4, -- NX Status Handler
1 => 1, -- I2C master
2 => 5, -- Data Receiver
3 => 3, -- Data Buffer
4 => 0, -- SPI Master
5 => 3, -- Trigger Generator
- 6 => 4, -- Data Validate
+ 6 => 5, -- Data Validate
7 => 4, -- Trigger Handler
8 => 5, -- Trigger Validate
- 9 => 9, -- NX Setup
+ 9 => 9, -- NX Register Setup
10 => 10, -- NX Histograms
11 => 0, -- Debug Handler
12 => 2, -- Data Delay
-------------------------------------------------------------------------------
-- Registers
-------------------------------------------------------------------------------
- nx_control_1: nx_control
+ nx_status_1: nx_status
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN,
PLL_ADC_DCLK_LOCK_IN => PLL_ADC_DCLK_LOCK_IN,
PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock,
+ PLL_RESET_OUT => PLL_RESET_OUT,
- I2C_SM_RESET_OUT => i2c_sm_reset_o,
+ I2C_SM_RESET_OUT => I2C_SM_RESET_OUT,
I2C_REG_RESET_OUT => i2c_reg_reset_o,
- NX_TS_RESET_OUT => nx_ts_reset_1,
- I2C_ONLINE_IN => nxyter_online_i2c,
- OFFLINE_OUT => nxyter_offline,
+ NX_TS_RESET_OUT => nx_timestamp_reset_1,
+ NX_ONLINE_OUT => nxyter_online,
ERROR_ALL_IN => error_all,
DEBUG_OUT => debug_line(0)
);
- nx_setup_1: nx_setup
+ nx_register_setup_1: nx_register_setup
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+ I2C_ONLINE_IN => nxyter_online,
I2C_COMMAND_OUT => i2c_command,
I2C_COMMAND_BUSY_IN => i2c_command_busy,
I2C_DATA_IN => i2c_data,
I2C_DATA_BYTES_IN => i2c_data_bytes,
I2C_LOCK_OUT => i2c_lock,
- I2C_ONLINE_OUT => nxyter_online_i2c,
- I2C_REG_RESET_IN => i2c_reg_reset_o,
+ I2C_REG_RESET_IN => not i2c_reg_reset_o,
SPI_COMMAND_OUT => spi_command,
SPI_COMMAND_BUSY_IN => spi_command_busy,
SPI_DATA_IN => spi_data,
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
NX_MAIN_CLK_IN => CLK_NX_MAIN_IN,
- TIMESTAMP_SYNC_IN => nx_ts_reset_o,
+ TIMESTAMP_RESET_IN => nx_timestamp_reset,
+ TIMESTAMP_RESET_OUT => nx_timestamp_reset_o,
TRIGGER_IN => timestamp_trigger,
TIMESTAMP_CURRENT_OUT => timestamp_current,
TIMESTAMP_HOLD_OUT => timestamp_hold,
- TIMESTAMP_SYNCED_OUT => nx_timestamp_sync,
TIMESTAMP_TRIGGER_OUT => nx_timestamp_trigger_o,
SLV_READ_IN => open,
SLV_WRITE_IN => open,
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
NX_MAIN_CLK_IN => CLK_NX_MAIN_IN,
- NXYTER_OFFLINE_IN => nxyter_offline,
+ NXYTER_OFFLINE_IN => not nxyter_online,
TIMING_TRIGGER_IN => TIMING_TRIGGER_IN,
LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
NX_MAIN_CLK_IN => CLK_NX_MAIN_IN,
+
+ TRIGGER_BUSY_IN => trigger_busy,
TRIGGER_IN => trigger_testpulse,
TRIGGER_OUT => trigger_intern,
- TS_RESET_OUT => nx_ts_reset_2,
+ TS_RESET_OUT => nx_timestamp_reset_2,
TESTPULSE_OUT => nx_testpulse_o,
- TEST_IN => new_timestamp,
+
+ TIMESTAMP_IN => timestamp_recv,
+ ADC_DATA_IN => adc_data_recv,
+ NEW_DATA_IN => data_clk_recv,
+ SELF_TRIGGER_OUT => self_trigger,
+
SLV_READ_IN => slv_read(5),
SLV_WRITE_IN => slv_write(5),
SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
nx_data_receiver_1: nx_data_receiver
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- NX_DATA_CLK_TEST_IN => NX_DATA_CLK_TEST_IN,
- TRIGGER_IN => trigger_timing,
-
- NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN,
- NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_DATA_CLK_TEST_IN => NX_DATA_CLK_TEST_IN,
+ TRIGGER_IN => trigger_timing,
+
+ NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN,
+ NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
+ NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset_3,
- ADC_CLK_DAT_IN => CLK_ADC_IN,
- ADC_FCLK_IN => ADC_FCLK_IN,
- ADC_DCLK_IN => ADC_DCLK_IN,
- ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT,
- ADC_A_IN => ADC_A_IN,
- ADC_B_IN => ADC_B_IN,
- ADC_NX_IN => ADC_NX_IN,
- ADC_D_IN => ADC_D_IN,
- ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock,
-
- NX_TIMESTAMP_OUT => new_timestamp,
- ADC_DATA_OUT => new_adc_data,
- NEW_DATA_OUT => new_data,
-
- TIMESTAMP_CURRENT_IN => timestamp_current,
-
- SLV_READ_IN => slv_read(2),
- SLV_WRITE_IN => slv_write(2),
- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
- SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
- SLV_ACK_OUT => slv_ack(2),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
- ERROR_OUT => error_data_receiver,
- DEBUG_OUT => debug_line(7)
+ ADC_CLK_DAT_IN => CLK_ADC_IN,
+ ADC_FCLK_IN => ADC_FCLK_IN,
+ ADC_DCLK_IN => ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT,
+ ADC_A_IN => ADC_A_IN,
+ ADC_B_IN => ADC_B_IN,
+ ADC_NX_IN => ADC_NX_IN,
+ ADC_D_IN => ADC_D_IN,
+ ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock,
+
+ NX_TIMESTAMP_OUT => timestamp_recv,
+ ADC_DATA_OUT => adc_data_recv,
+ NEW_DATA_OUT => data_clk_recv,
+
+ SLV_READ_IN => slv_read(2),
+ SLV_WRITE_IN => slv_write(2),
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
+ SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
+ SLV_ACK_OUT => slv_ack(2),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
+ ERROR_OUT => error_data_receiver,
+ DEBUG_OUT => debug_line(7)
);
-------------------------------------------------------------------------------
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- NX_FRAME_IN => new_timestamp,
- ADC_DATA_IN => new_adc_data,
- NEW_DATA_IN => new_data,
- NX_FRAME_OUT => new_timestamp_delayed,
- ADC_DATA_OUT => new_adc_data_delayed,
- NEW_DATA_OUT => new_data_delayed,
- FIFO_DELAY_IN => new_data_fifo_delay,
+ NX_FRAME_IN => timestamp_recv,
+ ADC_DATA_IN => adc_data_recv,
+ NEW_DATA_IN => data_clk_recv,
+
+ NX_FRAME_OUT => timestamp_delayed,
+ ADC_DATA_OUT => adc_data_delayed,
+ NEW_DATA_OUT => data_clk_delayed,
+
+ FIFO_DELAY_IN => data_fifo_delay,
SLV_READ_IN => slv_read(12),
SLV_WRITE_IN => slv_write(12),
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- NX_TIMESTAMP_IN => new_timestamp_delayed,
- ADC_DATA_IN => new_adc_data_delayed,
- NEW_DATA_IN => new_data_delayed,
+ NX_TIMESTAMP_IN => timestamp_delayed,
+ ADC_DATA_IN => adc_data_delayed,
+ DATA_CLK_IN => data_clk_delayed,
TIMESTAMP_OUT => timestamp,
CHANNEL_OUT => timestamp_channel_id,
TIMESTAMP_STATUS_OUT => timestamp_status,
ADC_DATA_OUT => adc_data,
- DATA_VALID_OUT => data_valid,
- SELF_TRIGGER_OUT => self_trigger,
+ DATA_CLK_OUT => data_clk,
NX_TOKEN_RETURN_OUT => nx_token_return,
NX_NOMORE_DATA_OUT => nx_nomore_data,
SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
+ ERROR_OUT => error_data_validate,
DEBUG_OUT => debug_line(9)
);
nx_trigger_validate_1: nx_trigger_validate
generic map (
- BOARD_ID => BOARD_ID
+ BOARD_ID => BOARD_ID,
+ VERSION_NUMBER => VERSION_NUMBER
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- DATA_CLK_IN => data_valid,
+ DATA_CLK_IN => data_clk,
TIMESTAMP_IN => timestamp,
CHANNEL_IN => timestamp_channel_id,
TIMESTAMP_STATUS_IN => timestamp_status,
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_validate_busy,
TIMESTAMP_FPGA_IN => timestamp_hold,
- DATA_FIFO_DELAY_OUT => new_data_fifo_delay,
+ DATA_FIFO_DELAY_OUT => data_fifo_delay,
DATA_OUT => trigger_data,
DATA_CLK_OUT => trigger_data_clk,
nx_event_buffer_1: nx_event_buffer
generic map (
- BOARD_ID => BOARD_ID
+ BOARD_ID => BOARD_ID
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
RESET_DATA_BUFFER_IN => event_buffer_clear,
- NXYTER_OFFLINE_IN => nxyter_offline,
+ NXYTER_OFFLINE_IN => not nxyter_online,
DATA_IN => trigger_data,
DATA_CLK_IN => trigger_data_clk,
nx_status_event_1: nx_status_event
generic map (
- BOARD_ID => BOARD_ID
+ BOARD_ID => BOARD_ID,
+ VERSION_NUMBER => VERSION_NUMBER
)
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- NXYTER_OFFLINE_IN => nxyter_offline,
+ NXYTER_OFFLINE_IN => not nxyter_online,
TRIGGER_IN => trigger_status,
FAST_CLEAR_IN => fast_clear,
TRIGGER_BUSY_OUT => trigger_evt_busy_1,
-------------------------------------------------------------------------------
-- nXyter Signals
-------------------------------------------------------------------------------
- nx_ts_reset_o <= nx_ts_reset_1 or nx_ts_reset_2;
- NX_RESET_OUT <= not nx_ts_reset_o;
- NX_TESTPULSE_OUT <= nx_testpulse_o;
+ nx_timestamp_reset <= nx_timestamp_reset_1 or
+ nx_timestamp_reset_2 or
+ nx_timestamp_reset_3;
+ NX_RESET_OUT <= not nx_timestamp_reset_o;
+ NX_TESTPULSE_OUT <= nx_testpulse_o;
-------------------------------------------------------------------------------
-- I2C Signals
-------------------------------------------------------------------------------
- I2C_SM_RESET_OUT <= not i2c_sm_reset_o;
- I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
+ I2C_REG_RESET_OUT <= i2c_reg_reset_o;
-------------------------------------------------------------------------------
-- Others
0x8125 : r Frame Rate (in Hz)
-- NX Data Delay
-0x8130 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns).
+0x8180 : r FIFO Delay, i.e. Trigger Delay (8 Bit, in 32ns).
Calculation is based on CTS Trigger Delay
(see NX Trigger Validate)
-0x8131 : r/w Debug Multiplexer (0=Dta Delay, 1=FIFO)
+0x8181 : r/w Debug Multiplexer (0=Data Delay, 1=FIFO)
-- NX Trigger Validate
0x8400 : r/w Readout Mode: 4 Bits
-- Debug Multiplexer
0x8020 : r/w Select Debug Entity
- 0: nx_control
- 1: nx_setup
+ 0: nx_status
+ 1: nx_register_setup
2: nx_i2c_master
3: adc_spi_master
4: nx_fpga_timestamp
-n 1
-y
-s 12
--t 11
+-t 26
-c 1
-e 2
-m nodelist.txt
add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
add_file -vhdl -lib "work" "source/nx_status_event.vhd"
-add_file -vhdl -lib "work" "source/nx_control.vhd"
-add_file -vhdl -lib "work" "source/nx_setup.vhd"
+add_file -vhdl -lib "work" "source/nx_status.vhd"
+add_file -vhdl -lib "work" "source/nx_register_setup.vhd"
add_file -vhdl -lib "work" "source/nx_histogram.vhd"
add_file -vhdl -lib "work" "source/nx_histograms.vhd"
USE PRIMARY NET "clk_100_i_c";
USE PRIMARY NET "CLK_PCLK_RIGHT_c";
- USE PRIMARY2EDGE NET "clk_adc_dat_1";
- #USE PRIMARY2EDGE NET "clk_adc_dat_2";
+ USE PRIMARY2EDGE NET "nx1_clk_adc_dat";
+ #USE PRIMARY2EDGE NET "nx2_clk_adc_dat";
#################################################################
# Reset Nets
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o" 10 ns;
MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY*" 20 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_control_*/nx_ts_reset_o" 10 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_status_*/nx_ts_reset_o" 10 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 10 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 20 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns;
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*.nx_event_buffer_*.fifo_almost_full_thr" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*.nx_event_buffer_*.fifo_almost_full_thr_*" 100 ns;
BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*";
NX1_RESET_OUT : out std_logic;
NX1_I2C_SDA_INOUT : inout std_logic;
NX1_I2C_SCL_INOUT : inout std_logic;
- NX1_I2C_SM_RESET_OUT : out std_logic;
+ NX1_I2C_SM_RESET_OUT : inout std_logic;
NX1_I2C_REG_RESET_OUT : out std_logic;
NX1_SPI_SCLK_OUT : out std_logic;
NX1_SPI_SDIO_INOUT : inout std_logic;
signal time_counter : unsigned(31 downto 0);
-- nXyter-FEB-Board Clocks
- signal nx_main_clk : std_logic;
- signal nx_data_clk_test : std_logic;
- signal pll_nx_clk_lock : std_logic;
- signal clk_adc_dat_1 : std_logic;
- signal pll_adc_clk_lock_1 : std_logic;
-
- signal nx1_adc_sample_clk : std_logic;
+ signal nx_main_clk : std_logic;
+ signal nx_pll_clk_lock : std_logic;
+ signal nx_data_clk_test : std_logic;
+ signal nx_pll_reset : std_logic;
+ signal nx1_clk_adc_dat : std_logic;
+ signal nx1_pll_adc_clk_lock : std_logic;
+ signal nx1_adc_sample_clk : std_logic;
+
-- nXyter 1 Regio Bus
signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
signal nx1_regio_data_in : std_logic_vector (31 downto 0);
CLK_IN => clk_100_i,
RESET_IN => reset_i,
CLK_NX_MAIN_IN => nx_main_clk,
- CLK_ADC_IN => clk_adc_dat_1,
- PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock,
- PLL_ADC_DCLK_LOCK_IN => pll_adc_clk_lock_1,
+ CLK_ADC_IN => nx1_clk_adc_dat,
+ PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock,
+ PLL_ADC_DCLK_LOCK_IN => nx1_pll_adc_clk_lock,
NX_DATA_CLK_TEST_IN => nx_data_clk_test,
-
+ PLL_RESET_OUT => nx_pll_reset,
+
TRIGGER_OUT => fee1_trigger,
I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
pll_nx_clk250_1: entity work.pll_nx_clk250
port map (
CLK => CLK_PCLK_RIGHT,
+ RESET => nx_pll_reset,
CLKOP => nx_main_clk,
CLKOK => nx_data_clk_test,
- LOCK => pll_nx_clk_lock
+ LOCK => nx_pll_clk_lock
);
-- Port FF for Nxyter Main Clocks
pll_adc_clk_1: pll_adc_clk
port map (
CLK => CLK_PCLK_RIGHT,
- CLKOP => clk_adc_dat_1,
- LOCK => pll_adc_clk_lock_1
+ RESET => nx_pll_reset,
+ CLKOP => nx1_clk_adc_dat,
+ LOCK => nx1_pll_adc_clk_lock
);
end architecture;
IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25;
IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25;
-IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
IOBUF PORT "NX1_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4;
-IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
+IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4;
#IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25;
#IOBUF PORT "NX2_RESET_OUT" IO_TYPE=LVDS25;
#
-#IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-#IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+#IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+#IOBUF PORT "NX2_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
#IOBUF PORT "NX2_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
#IOBUF PORT "NX2_I2C_SCL_INOUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
#
jspc29 / trb3.git / commitdiff