trying to find bugfix for reading same data word several times.

diff --git a/mupix/Mupix8/sources/Datapath/CircularMemory.vhd b/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
index 21fe871157fae6facfdfc3dd75e501ff1dee43ac..d7a4c0855789bbb22bc64fd5f51907792379eb4e 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
+++ b/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
@@ -144,6 +144,7 @@ RAM_DP_4096_32_1: entity work.RAM_DP_8192_32
             writepointer <= writepointer + 1;
             readpointer  <= readpointer + 1;
           elsif rd_en_i = '1' then -- update read counter
+            writepointer <= writepointer;
             readpointer  <= readpointer + 1;
           else -- do nothing
             readpointer <= readpointer;

diff --git a/mupix/Mupix8/sources/Datapath/DataFilter.vhd b/mupix/Mupix8/sources/Datapath/DataFilter.vhd
index 9d908474f7572c8ca8e4f747e0ae722d739109ce..dc85b2a5b12d5e5864fb79d3be881e4d7aa6800c 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/DataFilter.vhd
+++ b/mupix/Mupix8/sources/Datapath/DataFilter.vhd
@@ -18,9 +18,7 @@ entity MupixDataFilter is
         dataout_valid : out std_logic; -- data out valid signal
         counterA : out std_logic_vector(31 downto 0); -- last counter value link A
         counterB : out std_logic_vector(31 downto 0); -- last counter value link B
-        counterC : out std_logic_vector(31 downto 0); -- last counter value link C
-        counterD : out std_logic_vector(31 downto 0) -- last counter value link D
-        );
+        counterC : out std_logic_vector(31 downto 0)); -- last counter value link C
 end entity MupixDataFilter;
 
 
@@ -31,7 +29,6 @@ architecture RTL of MupixDataFilter is
     signal counterA_i : std_logic_vector(31 downto 0) := (others => '0');
     signal counterB_i : std_logic_vector(31 downto 0) := (others => '0');
     signal counterC_i : std_logic_vector(31 downto 0) := (others => '0');
-    signal counterD_i : std_logic_vector(31 downto 0) := (others => '0');
 
 begin
 
@@ -43,7 +40,6 @@ begin
                 counterA_i <= (others => '0');
                 counterB_i <= (others => '0');
                 counterC_i <= (others => '0');
-                counterD_i <= (others => '0');
                 dataout_valid_i <= '0';
             else
                 dataout_valid_i <= '0';
@@ -75,6 +71,5 @@ begin
     counterA <= counterA_i;
     counterB <= counterB_i;
     counterC <= counterC_i;
-    counterD <= counterD_i;
 
 end architecture;

diff --git a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
index 611fe4ee72e5f83d93b30f1ac522f9ee5c562538..67020b1c060bc2472d7fc031b32d66865f49f24d 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
+++ b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
@@ -96,8 +96,7 @@ architecture rtl of MupixTRBReadout is
         dataout_valid : out std_logic;
         counterA      : out std_logic_vector(31 downto 0);
         counterB      : out std_logic_vector(31 downto 0);
-        counterC      : out std_logic_vector(31 downto 0);
-        counterD      : out std_logic_vector(31 downto 0));
+        counterC      : out std_logic_vector(31 downto 0));
 end component MupixDataFilter;
 
   component ReadoutController
@@ -149,7 +148,6 @@ end component MupixDataFilter;
   signal mupix_filter_counterA_i      : std_logic_vector(g_datawidthtrb - 1 downto 0);
   signal mupix_filter_counterB_i      : std_logic_vector(g_datawidthtrb - 1 downto 0);
   signal mupix_filter_counterC_i      : std_logic_vector(g_datawidthtrb - 1 downto 0);
-  signal mupix_filter_counterD_i      : std_logic_vector(g_datawidthtrb - 1 downto 0);
 
   signal start_readout_slow_to_buffer  : std_logic := '0';
   signal start_readout                 : std_logic := '0';
@@ -211,8 +209,7 @@ begin
       dataout_valid => mupix_filter_dataout_valid_i,
       counterA      => mupix_filter_counterA_i,
       counterB      => mupix_filter_counterB_i,
-      counterC      => mupix_filter_counterC_i,
-      counterD      => mupix_filter_counterD_i);
+      counterC      => mupix_filter_counterC_i);
 
   cycl_buffer_1 : entity work.CircularMemory
     generic map(
@@ -313,7 +310,6 @@ begin
   --0x10c: counter link A (read-only)
   --0x10d: counter link B (read-only)
   --0x10e: counter link C (read-only)
-  --0x10f: counter link D (read-only)
   -----------------------------------------------------------------------------------
   slv_bus_handler : process(clk) is
   begin
@@ -422,9 +418,6 @@ begin
             when x"010e" =>
               SLV_DATA_OUT <= mupix_filter_counterC_i;
               SLV_ACK_OUT              <= '1';
-            when x"010f" =>
-              SLV_DATA_OUT <= mupix_filter_counterD_i;
-              SLV_ACK_OUT              <= '1';
             when others =>
               slv_unknown_addr_out <= '1';
           end case;

diff --git a/mupix/Mupix8/sources/Datapath/ReadoutController.vhd b/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
index 6c3cc35429f17f17e3c70c06c432fed0ed86fb88..d623cd1ef0f3c0cd2914a16f89604be6b8b78099 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
+++ b/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
@@ -158,24 +158,13 @@ begin
             data_out    <= data_in;
             wordcounter <= wordcounter + 1;
             readout_fsm <= read;
-            if mode = "01" then
-              if wordcounter < unsigned(max_words) - 2 and almost_empty = '0' then
-                rd_en <= '1';
-              else
-                rd_en <= '0';
-              end if;
-              if almost_empty_edge = "01" or wordcounter = unsigned(max_words) - 1 then
-                readout_fsm <= trailer;
-              end if;
+            if wordcounter < unsigned(max_words) - 2 and almost_empty = '0' then
+              rd_en <= '1';
             else
-              if wordcounter < unsigned(max_words) - 2 and almost_empty = '0' then
-                rd_en <= '1';
-              else
-                rd_en <= '0';
-              end if;
-              if almost_empty_edge = "01" or wordcounter = unsigned(max_words) - 1 then
-                readout_fsm <= trailer;
-              end if;
+              rd_en <= '0';
+            end if;
+            if almost_empty_edge = "01" or wordcounter = unsigned(max_words) - 1 then
+              readout_fsm <= trailer;
             end if;
           when wait_trigger =>
             busy               <= '1';