*** empty log message ***

diff --git a/trb_net16_api_ipu_streaming.vhd b/trb_net16_api_ipu_streaming.vhd
index 81c2d972530f06c43447b59bfe17e023e085953e..0add059dc1a5b32486ece6e8fe26cdda0b7209d1 100644 (file)
--- a/trb_net16_api_ipu_streaming.vhd
+++ b/trb_net16_api_ipu_streaming.vhd
@@ -1,4 +1,12 @@
 
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
 entity trb_net16_api_ipu_streaming is
   port(
     CLK    : in std_logic;
@@ -53,7 +61,7 @@ entity trb_net16_api_ipu_streaming is
                                              --has been read.
 
     MY_ADDRESS_IN         : in  std_logic_vector (15 downto 0);
-    CTRL_SEQNR_RESET      : in std_logic;
+    CTRL_SEQNR_RESET      : in std_logic
 
     );
 end entity;
@@ -71,8 +79,28 @@ architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming is
   signal APL_FEE_DTYPE_IN         : std_logic_vector(3 downto 0);
   signal APL_FEE_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
   signal APL_FEE_SEND_IN          : std_logic;
+  signal APL_FEE_DATA_OUT         : std_logic_vector(15 downto 0);
+  signal APL_FEE_PACKET_NUM_OUT   : std_logic_vector(2 downto 0);
+  signal APL_FEE_DATAREADY_OUT    : std_logic;
+  signal APL_FEE_READ_IN          : std_logic;
+  signal APL_FEE_TYP_OUT          : std_logic_vector(2 downto 0);
+  signal APL_FEE_RUN_OUT          : std_logic;
+  signal APL_FEE_SEQNR_OUT        : std_logic_vector(7 downto 0);
+  signal APL_FEE_LENGTH_IN        : std_logic_vector(15 downto 0);
+
   signal APL_CTS_TYP_OUT          : std_logic_vector(2 downto 0);
 
+
+  signal APL_CTS_DATA_IN        : std_logic_vector(15 downto 0);
+  signal APL_CTS_PACKET_NUM_IN  : std_logic_vector(2 downto 0);
+  signal APL_CTS_DATAREADY_IN   : std_logic;
+  signal APL_CTS_READ_OUT       : std_logic;
+  signal APL_CTS_SHORT_TRANSFER_IN : std_logic;
+  signal APL_CTS_DTYPE_IN       : std_logic_vector(3 downto 0);
+  signal APL_CTS_SEND_IN        : std_logic;
+  signal APL_CTS_RUN_OUT        : std_logic;
+  signal APL_CTS_LENGTH_IN      : std_logic_vector(15 downto 0);
+
   signal buf_CTS_CODE_OUT               : std_logic_vector(7 downto 0);
   signal buf_CTS_INFORMATION_OUT        : std_logic_vector(7 downto 0);
   signal buf_CTS_READOUT_TYPE_OUT       : std_logic_vector(3 downto 0);
@@ -90,8 +118,8 @@ begin
   THE_CTS_API: trb_net16_api_base
     generic map (
       API_TYPE          => c_API_PASSIVE,
-      FIFO_TO_INT_DEPTH => FIFO_BRAM,
-      FIFO_TO_APL_DEPTH => FIFO_BRAM,
+      FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+      FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
       FORCE_REPLY       => cfg_FORCE_REPLY(1),
       USE_VENDOR_CORES   => c_YES,
       SECURE_MODE_TO_APL => c_YES,
@@ -133,10 +161,10 @@ begin
       INT_MASTER_DATAREADY_IN  => '0',
       INT_MASTER_DATA_IN       => (others => '0'),
       INT_MASTER_PACKET_NUM_IN => (others => '0'),
-      INT_MASTER_READ_OUT      => '0',
-      INT_SLAVE_DATAREADY_OUT  => '0'
-      INT_SLAVE_DATA_OUT       => (others => '0'),
-      INT_SLAVE_PACKET_NUM_OUT => (others => '0'),
+      INT_MASTER_READ_OUT      => open,
+      INT_SLAVE_DATAREADY_OUT  => open,
+      INT_SLAVE_DATA_OUT       => open,
+      INT_SLAVE_PACKET_NUM_OUT => open,
       INT_SLAVE_READ_IN        => '0',
       INT_SLAVE_DATAREADY_IN => CTS_INIT_DATAREADY_IN,
       INT_SLAVE_DATA_IN      => CTS_INIT_DATA_IN,
@@ -158,8 +186,8 @@ begin
   THE_FEE_API: trb_net16_api_base
     generic map (
       API_TYPE          => c_API_ACTIVE,
-      FIFO_TO_INT_DEPTH => FIFO_BRAM,
-      FIFO_TO_APL_DEPTH => FIFO_BRAM,
+      FIFO_TO_INT_DEPTH => c_FIFO_BRAM,
+      FIFO_TO_APL_DEPTH => c_FIFO_BRAM,
       FORCE_REPLY       => cfg_FORCE_REPLY(1),
       USE_VENDOR_CORES   => c_YES,
       SECURE_MODE_TO_APL => c_YES,
@@ -201,10 +229,10 @@ begin
       INT_MASTER_DATAREADY_IN  => '0',
       INT_MASTER_DATA_IN       => (others => '0'),
       INT_MASTER_PACKET_NUM_IN => (others => '0'),
-      INT_MASTER_READ_OUT      => '0',
-      INT_SLAVE_DATAREADY_OUT  => '0'
-      INT_SLAVE_DATA_OUT       => (others => '0'),
-      INT_SLAVE_PACKET_NUM_OUT => (others => '0'),
+      INT_MASTER_READ_OUT      => open,
+      INT_SLAVE_DATAREADY_OUT  => open,
+      INT_SLAVE_DATA_OUT       => open,
+      INT_SLAVE_PACKET_NUM_OUT => open,
       INT_SLAVE_READ_IN        => '0',
       INT_SLAVE_DATAREADY_IN => FEE_REPLY_DATAREADY_IN,
       INT_SLAVE_DATA_IN      => FEE_REPLY_DATA_IN,

diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd
index 923e208a6f06e45478129b7ec1c34c433ca4ac6e..d51dff45b9a0d28880a5be2454cceab62b3125a1 100644 (file)
--- a/trb_net16_regio_bus_handler.vhd
+++ b/trb_net16_regio_bus_handler.vhd
@@ -47,8 +47,8 @@ end entity;
 
 architecture regio_bus_handler_arch of trb_net16_regio_bus_handler is
 
-  signal port_select_int      : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
-  signal next_port_select_int : integer range 0 to c_BUS_HANDLER_MAX_PORTS;
+  signal port_select_int      : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
+  signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
 
   signal buf_BUS_READ_OUT         : std_logic_vector(PORT_NUMBER downto 0);
   signal buf_BUS_WRITE_OUT        : std_logic_vector(PORT_NUMBER downto 0);