BROADCAST_BITMASK => x"FF",
BROADCAST_SPECIAL_ADDR => x"45",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000000",
+ REGIO_HARDWARE_VERSION => x"9100b000",
REGIO_INIT_ADDRESS => x"f351",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
LED_GREEN <= not med_stat_op(9);
LED_RED <= not (med_stat_op(10) or med_stat_op(11));
- LED_LINKOK(1) <= not med_stat_op(9);
- LED_TX(1) <= not med_stat_op(10);
- LED_RX(1) <= not med_stat_op(11);
+ LED_LINKOK(1) <= not med_stat_op(9); --link established
+ LED_TX(1) <= not (med_stat_op(10) or med_stat_op(11)); --data RX or TX
+ LED_RX(1) <= not med_stat_op(12); --DLM RX
LED_LINKOK(6 downto 2) <= "11111";
LED_TX(6 downto 2) <= "11111";
LED_RX(6 downto 2) <= "11111";
-FPGA5_COMM(3) <= '0';
-FPGA5_COMM(2) <= '0';
-
+ --no link to central FPGA
+ FPGA5_COMM(3) <= '0';
+ FPGA5_COMM(2) <= '0';
+
+
+
---------------------------------------------------------------------------
-- Test Connector
---------------------------------------------------------------------------
LED_GREEN <= not med_stat_op(9);
LED_RED <= not (med_stat_op(10) or med_stat_op(11));
- LED_LINKOK(1) <= not med_stat_op(16+9);
- LED_TX(1) <= not med_stat_op(16+10);
- LED_RX(1) <= not med_stat_op(16+11);
+ LED_LINKOK(1) <= not med_stat_op(16+9); --link established
+ LED_TX(1) <= not (med_stat_op(16+10) or med_stat_op(16+11)); --data RX or TX
+ LED_RX(1) <= not med_stat_op(16+12); --DLM RX
LED_LINKOK(6 downto 2) <= "11111";
LED_TX(6 downto 2) <= "11111";