signal num_pakets : unsigned(3 downto 0) := (others => '0');
signal use_crc : std_logic := '0';
---signal next_use_crc : std_logic := '0';
+signal last_use_crc : std_logic := '0';
signal load_use_crc : std_logic := '0';
--signal last_load_use_crc : std_logic := '0';
signal disable_crc : std_logic := '0';
last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100);
last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100);
---last_load_use_crc <= load_use_crc when rising_edge(CLK_100);
+last_use_crc <= use_crc when rising_edge(CLK_100);
--use_crc <= next_use_crc when rising_edge(CLK_100);
process begin
end if;
end if;
- if use_crc = '0' then --check disabled, just dummy counter
- if buf_rx_write_out = '1' then
- good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+1);
- end if;
+ if last_use_crc = '0' and buf_rx_write_out = '1' then
+ good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+1);
elsif pulse_good_100 = '1' then
- got_pulse_good <= '1';
good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
end if;
-
+
+ if pulse_good_100 = '1' then
+ got_pulse_good <= '1';
+ end if;
if pulse_bad_100 = '1' then
got_pulse_bad <= '1';
end if;