tdc slow control is updated - cu

diff --git a/trb3/TdcDataFormat.tex b/trb3/TdcDataFormat.tex
index f5ac04e2ddbe2da01770b3201832e9abbfaa57dc..1cc9ba73173f6d5570d48afe43ead55e15d674a2 100644 (file)
--- a/trb3/TdcDataFormat.tex
+++ b/trb3/TdcDataFormat.tex
@@ -27,7 +27,7 @@ Any word starting with the bits "001" indicates a header word from the TDC in th
 
 The trigger random code \textendash\ 8 bits \textendash\ is generated by the trbnet for each trigger in order to distinguish the trigger. It is repeated in the TDC HEADER, so data \& trigger matching can be tested.
 
-The error bits are used to indicate any error might occured in the TDC since the last trigger. The error bits coded in the header is given in Table \ref{tab:tdcHeaderErrorBits}
+The error bits are used to indicate any error might occurred in the TDC since the last trigger. The error bits coded in the header is given in Table \ref{tab:tdcHeaderErrorBits}
 
 \begin{table}[h]
   \centering

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index 54e439cb81c83b9504419879abf2e47161582927..d3bccf23c48a13bb9730e67f9d6a2ae0541baaec 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -9,7 +9,7 @@ A set of control registers are assigned in order to access the basic controls, e
       \multirow{5}{*}{0xc0}    & \multirow{5}{*}{Basic controls}       & 3-0   & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
                                &                                       & 4     & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
                                &                                       & 11-5  & reserved.\\
-                               &                                       & 12    & Used to select the trigger mode. 1 - with trigger mode; 0 - triggerless mode (For more details see \ref{sec:tdcTrigWin}).\\
+                               &                                       & 12    & Used to select the trigger mode. 1 - with trigger mode; 0 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
                                &                                       & 31-13 & reserved.\\
       \hline
       \multirow{5}{*}{0xc1}    & \multirow{5}{*}{Trigger window}       & 10-0  & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
@@ -35,7 +35,7 @@ A set of control registers are assigned in order to access the basic controls, e
       \hline
       Control Bits             & Bit   & \multicolumn{1}{c|}{Explanation}\\
       \hline \hline
-      \multirow{9}{*}{x"1"}    & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+      \multirow{9}{*}{x"1"}    & 7-0   & Debug word of the TDC Readout FSM (see \ref{tab:tdcReadoutFsm})\\
                                & 8     & REFERENCE\_TIME input\\
                                & 9     & VALID\_TIMING\_TRG\_IN input\\
                                & 10    & VALID\_NOTIMING\_TRG\_IN input\\
@@ -53,7 +53,7 @@ A set of control registers are assigned in order to access the basic controls, e
                                & 8     & fifo write pulse\\
                                & 15-9  & fine time bits between 6-0\\
       \hline
-      \multirow{4}{*}{x"2"}    & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+      \multirow{4}{*}{x"3"}    & 7-0   & Debug word of the TDC Readout FSM (see \ref{tab:tdcReadoutFsm})\\
                                & 8     & REFERENCE\_TIME input\\
                                & 9     & DATA\_WRITE\_OUT output\\
                                & 15-9  & DATA\_OUT output bits 27-22\\
@@ -64,7 +64,52 @@ A set of control registers are assigned in order to access the basic controls, e
   \end{center}  
 \end{table}
 
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|W{1cm}|rL|}
+      \hline
+      FSM debug                                & \multicolumn{2}{c|}{Explanation}\\
+      \hline \hline
+      x"01"                            & IDLE                          & waiting for a readout trigger\\\hline
+      x"02"                            & WAIT\_FOR\_TRG\_WIND\_END     & waiting until the end of the trigger window\\\hline
+      x"03"                            & WR\_HEADER                    & sending signals to write TDC header\\\hline
+      x"04"                            & WAIT\_FOR\_FIFO\_NR\_A        &\multirow{2}{7cm}{waiting for the decision of the next channel buffer to read}\\
+      x"05"                            & WAIT\_FOR\_FIFO\_NR\_B        &\\\hline
+      \multirow{2}{*}{x"06"}           & \multirow{2}{*}{APPLY\_MASK}  &\multirow{2}{7cm}{checking if there is any other channel buffer to read}\\
+                                       &                               &\\\hline
+      x"07"                            & RD\_CHANNEL\_A                &\multirow{3}{7cm}{sending necessary signals to read the buffer, writing the date to the endpoint buffer, checking the end of the buffer}\\
+      x"08"                            & RD\_CHANNEL\_B                &\\
+      x"09"                            & RD\_CHANNEL\_C                &\\\hline
+      x"0A"                            & WAIT\_FOR\_LVL1\_TRG\_A       &\multirow{3}{7cm}{waiting for a trigger data validation and checking if it was a spurious trigger}\\
+      x"0B"                            & WAIT\_FOR\_LVL1\_TRG\_B       &\\
+      x"0C"                            & WAIT\_FOR\_LVL1\_TRG\_C       &\\\hline
+      \multirow{2}{*}{x"0D"}           & \multirow{2}{*}{SEND\_STATUS} &\multirow{2}{7cm}{writing status information in case of a type "E" trigger or enabled \textit{Debug Mode}}\\
+                                       &                               &\\\hline
+      \multirow{3}{1cm}{x"0E" x"0F"}   & \multirow{3}{4.31cm}{SEND\_TRG\_RELEASE\_A SEND\_TRG\_RELEASE\_B}     &\multirow{3}{7cm}{sending a trigger release signal and waiting one extra clock cycle before going to the IDLE state}\\
+                                       &                               &\\
+                                       &                               &\\
+      \hline
+    \end{tabularx}
+  \caption{TDC Readout FSM debug word bitmap.}
+  \label{tab:tdcReadoutFsm}
+  \end{center}  
+\end{table}
 
+\begin{table}[htbp]
+  \begin{center}
+    \begin{tabularx}{\textwidth}{|W{1cm}|rL|}
+      \hline
+      FSM debug                        & \multicolumn{2}{c|}{Explanation}\\
+      \hline \hline
+      x"01"                    & IDLE                                  & waiting for a physical trigger\\\hline
+      x"02"                    & ENCODER\_FINISHED                     & waiting until the encoder is finished with conversion\\\hline
+      \multirow{2}{*}{x"03"}   & \multirow{2}{*}{LOOK\_FOR\_VALIDITY}  & waiting for a validity from the endpoint entity to write the data to the buffer\\
+      \hline
+    \end{tabularx}
+  \caption{TDC Reference Channel FSM debug word bitmap.}
+  \label{tab:tdcReferenceFsm}
+  \end{center}  
+\end{table}
 
 \begin{table}[htbp]
   \begin{center}
@@ -90,7 +135,7 @@ A set of control registers are assigned in order to access the basic controls, e
                                &                                       & 31-24 & reserved\\ \hline
       \multirow{2}{*}{0x88}    & \multirow{2}{3.5cm}{Multi timing trigger number}      & 23-0  & Number of multi timing triggers (triggers received before trigger is released) received\\
                                &                                       & 31-24 & reserved\\ \hline
-      \multirow{2}{*}{0x89}    & \multirow{2}{3.5cm}{Spurious trigger number}  & 23-0  & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-triggerless trigger)\\
+      \multirow{2}{*}{0x89}    & \multirow{2}{3.5cm}{Spurious trigger number}  & 23-0  & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-trigger-less trigger)\\
                                &                                       & 31-24 & reserved\\ \hline
       \multirow{2}{*}{0x8a}    & \multirow{2}{3.5cm}{Wrong readout number}     & 23-0  & Number of wrong readouts due to spurious triggers\\
                                &                                       & 31-24 & reserved\\ \hline