//#define PEXOR_TRB_DEBUG
#ifdef PEXOR_DEBUGPRINT
-#define pexor_dbg( args... ) \
+#define pexor_dbg( args... ) \
printk( args );
#else
#define pexor_dbg( args... ) ;
#endif
-#define pexor_msg( args... ) \
+#define pexor_msg( args... ) \
printk( args );
/* ---------------------------------------------------------------------- */
};
struct pexor_locks {
- struct semaphore sem_buf; /* lock semaphore for DMA buffer */
- struct semaphore sem_ioctl; /* lock semaphore for ioctl operations */
- spinlock_t spin_lock0; /* Spin Lock #0 */
-};
+ struct semaphore sem_buf; /* lock semaphore for DMA buffer */
+ struct semaphore sem_ioctl; /* lock semaphore for ioctl operations */
+ spinlock_t spin_lock0; /* Spin Lock #0 */
+};
+
+struct pexor_privdata
+{
+ atomic_t state; /* run state of device */
+ dev_t devno; /* device number (major and minor) */
+ int devid; /* local id (counter number) */
+ struct pci_dev* pdev; /* PCI device */
+ struct device* class_dev; /* Class device */
+ struct cdev cdev; /* char device struct */
+ struct dev_pexor pexor; /* mapped pexor address pointers */
+ unsigned long bases[6]; /* contains pci resource bases */
+ unsigned long reglen[6]; /* contains pci resource length */
+ void* iomem[6]; /* points to mapped io memory of the bars */
+
+ struct pexor_dma dma; /* dma buffer */
+ u32* memwrite_buffer; /* buffer for register_write_mem */
+ int magic; /* magic number to identify irq */
+
+ struct pexor_locks locks; /* all Spin and Semaphore Locks */
+ ssize_t pexor_read_buffer_ctr; /* size of pexor buffer */
-struct pexor_privdata
-{
- atomic_t state; /* run state of device */
- dev_t devno; /* device number (major and minor) */
- int devid; /* local id (counter number) */
- struct pci_dev* pdev; /* PCI device */
- struct device* class_dev; /* Class device */
- struct cdev cdev; /* char device struct */
- struct dev_pexor pexor; /* mapped pexor address pointers */
- unsigned long bases[6]; /* contains pci resource bases */
- unsigned long reglen[6]; /* contains pci resource length */
- void* iomem[6]; /* points to mapped io memory of the bars */
- struct pexor_dma dma; /* dma buffer */
- u32* memwrite_buffer; /* buffer for register_write_mem */
- int magic; /* magic number to identify irq */
- struct pexor_locks locks; /* all Spin and Semaphore Locks */
};
/* ---------------------------------------------------------------------- */
-#ifdef PEXOR_DEBUGPRINT
static unsigned char get_pci_revision(struct pci_dev* dev);
-#endif
static ssize_t pexor_sysfs_codeversion_show(struct device* dev,
struct device_attribute* attr,
static void cleanup_device(struct pexor_privdata* priv);
-struct pexor_privdata* get_privdata(struct file* filp);
+static struct pexor_privdata* get_privdata(struct file* filp);
static void set_pexor(struct dev_pexor* pg,
void* membase,
return priv;
}
-#ifdef PEXOR_DEBUGPRINT
-static unsigned char get_pci_revision(struct pci_dev* dev)
+unsigned char get_pci_revision(struct pci_dev* dev)
{
u8 revision;
pci_read_config_byte(dev, PCI_REVISION_ID, &revision);
return revision;
}
-#endif
-static void remove(struct pci_dev* dev)
+void remove(struct pci_dev* dev)
{
struct pexor_privdata* priv = (struct pexor_privdata* )pci_get_drvdata(dev);
cleanup_device(priv);
u16 comstat = 0;
u8 typ = 0;
- pexor_dbg(KERN_NOTICE "\n test_pci found PCI revision number %x\n",
- get_pci_revision(dev));
+ printk(KERN_NOTICE "\n test_pci found PCI revision number %x\n",
+ get_pci_revision(dev));
/*********** Test the address regions*/
for (bar = 0; bar < 6; bar++) {
/* Initialize Spin Locks, not needed at the moment */
spin_lock_init(&(priv->locks.spin_lock0));
+ /* set buffer empty */
+ priv->pexor_read_buffer_ctr = 0;
+
////////////////// here chardev registering
priv->devid = atomic_inc_return(&pexor_numdevs) - 1;
if (priv->devid >= PEXOR_MAX_DEVS) {
return 0;
}
-static ssize_t pexor_read_buffer_ctr = 0;
-
ssize_t pexor_read(struct file* filp,
char __user * buf,
size_t count,
goto out_read;
}
- if (count > pexor_read_buffer_ctr) {
+ if (count > priv->pexor_read_buffer_ctr) {
pexor_msg(KERN_ERR "ERROR> pexor_read: requested count (%d) > "
"Buffer: %d\n",
- (int)count, (int)pexor_read_buffer_ctr);
+ (int)count, (int)priv->pexor_read_buffer_ctr);
retval = -EFAULT;
goto out_read;
}
- pexor_read_buffer_ctr -= count;
+ priv->pexor_read_buffer_ctr -= count;
if (copy_to_user(buf, priv->dma.buffer, count)) {
pexor_msg(KERN_ERR "ERROR> pexor_read: copy_to_user failed\n");
if (channel >= PEXOR_TRB_NUM_CHANNELS)
return -1;
- pexor_read_buffer_ctr = 0;
+ priv->pexor_read_buffer_ctr = 0;
for (sg_ctr = 0; sg_ctr < priv->dma.nr_sglist; sg_ctr++) {
sg_length = sg_dma_len(&priv->dma.sglist[sg_ctr]);
for (i = 0; i < sg_length; i++) {
val = ioread32(priv->pexor.trbnet_receiver_data[channel]);
rmb();
if ((val & MASK_FIFO_TRB_ACT) == 0) {
- pexor_read_buffer_ctr += ctr * 4;
+ priv->pexor_read_buffer_ctr += ctr * 4;
return ctr;
}
} while (((val & MASK_FIFO_VALID) == 0) &&
cred1 = ioread32(priv->pexor.dma_debug2);
rmb();
- pexor_read_buffer_ctr = 0;
+ priv->pexor_read_buffer_ctr = 0;
/* Start DMA transfer */
pexor_dbg(KERN_ERR "Start DMA transfer\n");
}
status = dmaSize;
- pexor_read_buffer_ctr = dmaSize * 4;
+ priv->pexor_read_buffer_ctr = dmaSize * 4;
/* Check dmaSize */
if ((dmaSize * 4) >= (priv->dma.size * PAGE_SIZE)) {
{
int i;
pexor_msg(KERN_ERR "DMA: dmaSize: %d pexor_read_buffer_ctr: %d\n",
- dmaSize, (int)pexor_read_buffer_ctr);
+ dmaSize, (int)priv->pexor_read_buffer_ctr);
for (i = 0; i < dmaSize; i++) {
volatile u32 val = 0;
val = ioread32((i % 2 == 0)