signal gen_num : std_logic_vector(31 downto 0) := (others => '0');
signal gen_pause : std_logic_vector(31 downto 0) := (others => '0');
signal gen_down : std_logic_vector(31 downto 0) := (others => '0');
-signal gen_wren : std_logic := '0';
+signal gen_wren : std_logic_vector(3 downto 0) := (others => '0');
signal gen_chansel : chan_type := ("00", "01", "10", "11");
signal gen_data : data_type;
data_pause => gen_pause,
data_down => gen_down,
chan_sel => gen_chansel(J),
- writeEn => gen_wren,
+ writeEn => gen_wren(J),
data_out => gen_data(J)
);
port map(
CLK => clk,
RST => reset,
- WriteEn => gen_wren,
+ WriteEn => gen_wren(J),
ReadEn => fifo_rden(J),
DataIn => gen_data(J),
DataOut => fifo_data(J),
add_file -vhdl -lib "work" "sources/MupixDataLink.vhd"
add_file -vhdl -lib "work" "sources/TriggerHandler.vhd"
add_file -vhdl -lib "work" "sources/Arbiter.vhd"
+add_file -vhdl -lib "work" "sources/DatasourceSelector.vhd"
+add_file -vhdl -lib "work" "sources/FrameGenMux2.vhd"
+add_file -vhdl -lib "work" "sources/Generator3.vhd"