REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC
LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_LEFT" ;
LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_RIGHT" ;
+
+# read from SCI can be delayed due to long read strobe
+MULTICYCLE FROM ASIC THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+# write strobe can be delayed due to A/D being stable after access
+MULTICYCLE TO ASIC THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+# read from SCI can be delayed due to long read strobe
+MULTICYCLE FROM ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
+# write strobe can be delayed due to A/D being stable after access
+MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+# SCI write signal problem...
+#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i;
+#BLOCK INTERCLOCKDOMAIN PATHS;
RX_DLM_OUT(1) => open,
RX_DLM_OUT(2) => open,
RX_DLM_OUT(3) => rx_dlm_i,
--- RX_DLM_WORD_OUT => open,
RX_DLM_WORD_OUT(23 downto 0) => open,
RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
TX_DLM_IN => rx_dlm_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => '1',
SD_PRSNT_N_IN(1) => '1',
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
DESTROY_LINK_IN => x"0",
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
SD_PRSNT_N_IN(0) => backplane_rx_present(0),
SD_PRSNT_N_IN(1) => backplane_rx_present(1),
)
port map(
-- Clocks and reset
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => clk_full_osc, -- CLK_SUPPL_PCLK
SYSCLK => clk_sys,
- SAMPLE_CLK => CLK_SUPPL_PCLK,
RESET => reset_i, -- check
-- Media Interface TX/RX
MEDIA_MED2INT(0) => open,