update mimosis design with own GbE link on AddOn

diff --git a/mimosis/config.vhd b/mimosis/config.vhd
index 27af7ac57f6674da685671ca6544a01332bc180d..b2db4446f90045d0671b3d11f5f2f89c2bde8455 100644 (file)
--- a/mimosis/config.vhd
+++ b/mimosis/config.vhd
@@ -37,6 +37,7 @@ package config is
 
   constant EVENT_BUFFER_SIZE        : integer range 9 to 15 := 15; -- size of the event buffer, 2**N
   constant EVENT_MAX_SIZE           : integer := 15000;             --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+  constant USE_GBE                  : integer := c_YES;
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
@@ -83,7 +84,7 @@ package config is
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
     constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
-    
+    constant BROADCAST_BITMASK      : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');    
     
 end;
 
@@ -105,6 +106,7 @@ function generateIncludedFeatures return std_logic_vector is
 --     t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
 --     t(15)           := '1'; --TDC
 --     t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+    t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1));
     t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1));
     
     t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));

diff --git a/mimosis/par.p2t b/mimosis/par.p2t
index cd64b6adf758f02976458140df5cd9ba76392191..2c43fcd3957d759fcf9654b2e6f42ae8c23fa3e4 100644 (file)
--- a/mimosis/par.p2t
+++ b/mimosis/par.p2t
@@ -4,7 +4,7 @@
 #-m nodelist.txt       # Controlled by the compile.pl script.
 #-n 1                          # Controlled by the compile.pl script.
 -s 10
--t 3
+-t 4
 -c 2
 -e 2
 -i 10

diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj
index 0f12a462cf4455ec2e0eeeb9a996fa489e9f3610..79f9de9a5c1946913f3716a554e99124060df0f3 100644 (file)
--- a/mimosis/trb5sc_mimosis.prj
+++ b/mimosis/trb5sc_mimosis.prj
@@ -178,6 +178,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
@@ -248,15 +249,15 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"

diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd
index 98bca21fcad322b65dcc5931af91f5d4b75f7393..c38e9795075697823a8c76c68eb53c8bccf32974 100644 (file)
--- a/mimosis/trb5sc_mimosis.vhd
+++ b/mimosis/trb5sc_mimosis.vhd
@@ -120,8 +120,8 @@ architecture arch of trb5sc_mimosis is
   signal readout_rx                  : READOUT_RX;\r
   signal readout_tx                  : readout_tx_array_t(0 to 0);\r
 \r
-  signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx  : CTRLBUS_TX;\r
-  signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX;\r
+  signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in,  busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx  : CTRLBUS_TX;\r
+  signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx  : CTRLBUS_RX;\r
 \r
   signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
   signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
@@ -139,7 +139,6 @@ architecture arch of trb5sc_mimosis is
   signal out_data          : std_logic_vector(15 downto 0);\r
   signal out_i             : std_logic_vector( 7 downto 0);\r
   signal inp_i             : std_logic_vector( 7 downto 0);\r
-  signal dummy             : std_logic_vector( 1 downto 0);\r
   \r
   \r
   signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
@@ -148,6 +147,18 @@ architecture arch of trb5sc_mimosis is
   signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
   signal i2c_go_100, i2c_go : std_logic;\r
   signal i2c_reg_5_40       : std_logic_vector(31 downto 0);\r
+\r
+  --signal fwd_dst_mac  : std_logic_vector(47 downto 0);\r
+  --signal fwd_dst_ip   : std_logic_vector(31 downto 0);\r
+  --signal fwd_dst_port : std_logic_vector(15 downto 0);\r
+  --signal fwd_data     : std_logic_vector(7  downto 0);\r
+  --signal fwd_datavalid : std_logic;\r
+  --signal fwd_sop       : std_logic;\r
+  --signal fwd_eop       : std_logic;\r
+  --signal fwd_ready     : std_logic;\r
+  --signal fwd_full      : std_logic; \r
+  --signal fwd_length    : std_logic_vector(15 downto 0);\r
+  --signal fwd_do_send   : std_logic;  \r
   \r
 begin\r
 \r
@@ -246,7 +257,7 @@ RJ(0) <= clk_40;
   THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
     generic map (\r
       ADDRESS_MASK              => x"FFFF",\r
-      BROADCAST_BITMASK         => x"FF",\r
+      BROADCAST_BITMASK         => BROADCAST_BITMASK,\r
       REGIO_INIT_ENDPOINT_ID    => x"0001",\r
       REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
       TIMING_TRIGGER_RAW        => c_YES,\r
@@ -257,14 +268,16 @@ RJ(0) <= clk_40;
       DATA_BUFFER_FULL_THRESH   => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
       TRG_RELEASE_AFTER_DATA    => c_YES,\r
       HEADER_BUFFER_DEPTH       => 9,\r
-      HEADER_BUFFER_FULL_THRESH => 2**9-16\r
+      HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+      USE_GBE                   => USE_GBE\r
       )\r
 \r
     port map(\r
       --  Misc\r
-      CLK    => clk_sys,\r
-      RESET  => reset_i,\r
-      CLK_EN => '1',\r
+      CLK     => clk_sys,\r
+      RESET   => reset_i,\r
+      CLK_125 => CLK_125,\r
+      CLEAR_N => GSR_N,\r
 \r
       --  Media direction port\r
       MEDIA_MED2INT => med2int(0),\r
@@ -299,8 +312,8 @@ RJ(0) <= clk_40;
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
     generic map(\r
       PORT_NUMBER      => 5,\r
-      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", others => x"0000"),\r
-      PORT_ADDR_MASK   => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0),\r
+      PORT_ADDRESSES   => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
+      PORT_ADDR_MASK   => (0 => 12,      1 => 9,       2 => 1,       3 => 12,      4 => 5,       5 => 8,       6 => 8,       7 => 8,       others => 0),\r
       PORT_MASK_ENABLE => 1\r
       )\r
     port map(\r
@@ -315,11 +328,17 @@ RJ(0) <= clk_40;
       BUS_RX(2) => bustc_rx,            --Clock switch\r
       BUS_RX(3) => busmimosis_rx,\r
       BUS_RX(4) => busi2c_rx,\r
+      --BUS_RX(5) => busgbeip_rx,\r
+      --BUS_RX(6) => busgbereg_rx, \r
+      --BUS_RX(7) => busfwd_rx,\r
       BUS_TX(0) => bustools_tx,\r
       BUS_TX(1) => bussci_tx,\r
       BUS_TX(2) => bustc_tx,\r
       BUS_TX(3) => busmimosis_tx,\r
       BUS_TX(4) => busi2c_tx,\r
+      --BUS_TX(5) => busgbeip_tx,\r
+      --BUS_TX(6) => busgbereg_tx,\r
+      --BUS_TX(7) => busfwd_tx,\r
       STAT_DEBUG => open\r
       );\r
 \r
@@ -498,6 +517,143 @@ end process;
   TEST(14) <= flash_ncs_i;\r
   FLASH_NCS <= flash_ncs_i;    \r
 \r
+  \r
+-----------------------------------------------------------------------------\r
+---- GbE\r
+-----------------------------------------------------------------------------\r
+  --GBE : entity work.gbe_wrapper\r
+    --generic map(\r
+      --DO_SIMULATION             => 0,\r
+      --INCLUDE_DEBUG             => 0,\r
+      --USE_INTERNAL_TRBNET_DUMMY => 0,\r
+      --USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+      --RX_PATH_ENABLE            => 1,\r
+      --FIXED_SIZE_MODE           => 1,\r
+      --INCREMENTAL_MODE          => 1,\r
+      --FIXED_SIZE                => 100,\r
+      --FIXED_DELAY_MODE          => 1,\r
+      --UP_DOWN_MODE              => 0,\r
+      --UP_DOWN_LIMIT             => 100,\r
+      --FIXED_DELAY               => 100,\r
+\r
+      --NUMBER_OF_GBE_LINKS       => 1,\r
+      --LINKS_ACTIVE              => "0001",\r
+\r
+      --LINK_HAS_READOUT          => "0000",\r
+      --LINK_HAS_SLOWCTRL         => "0000",\r
+      --LINK_HAS_DHCP             => "0001",\r
+      --LINK_HAS_ARP              => "0001",\r
+      --LINK_HAS_PING             => "0001",\r
+      --LINK_HAS_FWD              => "0001"\r
+    --)\r
+    --port map(\r
+      --CLK_SYS_IN               => clk_sys,\r
+      --CLK_125_IN               => CLK_125,\r
+      --RESET                    => reset_i,\r
+      --GSR_N                    => GSR_N,\r
+      ---- Trigger\r
+      --TRIGGER_IN               => '0', \r
+      ---- SFP\r
+      --SD_PRSNT_N_IN(0)         => SFP_MOD_0,\r
+      --SD_LOS_IN(0)             => SFP_LOS,\r
+      --SD_TXDIS_OUT(0)          => SFP_TX_DIS,\r
+      ---- trigger channel\r
+      ---- only for LINK_HAS_READOUT\r
+      --CTS_NUMBER_IN            => (others => '0'),\r
+      --CTS_CODE_IN              => (others => '0'),\r
+      --CTS_INFORMATION_IN       => (others => '0'),\r
+      --CTS_READOUT_TYPE_IN      => (others => '0'),\r
+      --CTS_START_READOUT_IN     => '0',\r
+      --CTS_DATA_OUT             => open,                    \r
+      --CTS_DATAREADY_OUT        => open,                    \r
+      --CTS_READOUT_FINISHED_OUT => open,\r
+      --CTS_READ_IN              => '1',                     \r
+      --CTS_LENGTH_OUT           => open,                    \r
+      --CTS_ERROR_PATTERN_OUT    => open,\r
+      ---- data channel      \r
+      ---- only for LINK_HAS_READOUT\r
+      --FEE_DATA_IN              => (others => '0'),\r
+      --FEE_DATAREADY_IN         => '0',\r
+      --FEE_READ_OUT             => open,\r
+      --FEE_STATUS_BITS_IN       => (others => '0'),\r
+      --FEE_BUSY_IN              => '0',\r
+      ---- unique adresses\r
+      --MC_UNIQUE_ID_IN          => timer.uid,\r
+      --MY_TRBNET_ADDRESS_IN     => timer.network_address,\r
+      --ISSUE_REBOOT_OUT         => open, --BUG: needs to be connected\r
+      ---- slow control by GbE\r
+      --GSC_CLK_IN               => open,            \r
+      --GSC_INIT_DATAREADY_OUT   => open,   \r
+      --GSC_INIT_DATA_OUT        => open,        \r
+      --GSC_INIT_PACKET_NUM_OUT  => open,  \r
+      --GSC_INIT_READ_IN         => '1',        \r
+      --GSC_REPLY_DATAREADY_IN   => '0',  \r
+      --GSC_REPLY_DATA_IN        => (others => '0'),       \r
+      --GSC_REPLY_PACKET_NUM_IN  => (others => '0'), \r
+      --GSC_REPLY_READ_OUT       => open,       \r
+      --GSC_BUSY_IN              => '0',\r
+      ---- readout\r
+      --BUS_IP_RX                => busgbeip_rx, -- registers inside GbE\r
+      --BUS_IP_TX                => busgbeip_tx, -- registers inside GbE\r
+      --BUS_REG_RX               => busgbereg_rx, -- registers inside GbE\r
+      --BUS_REG_TX               => busgbereg_tx, -- registers inside GbE\r
+    ---- Forwarder\r
+      --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac,\r
+      --FWD_DST_IP_IN(31 downto 0)  => fwd_dst_ip,\r
+      --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port,\r
+      --FWD_DATA_IN(7 downto 0)     => fwd_data,\r
+      --FWD_DATA_VALID_IN(0)        => fwd_datavalid,\r
+      --FWD_SOP_IN(0)               => fwd_sop,\r
+      --FWD_EOP_IN(0)               => fwd_eop,\r
+      --FWD_READY_OUT(0)            => fwd_ready,\r
+      --FWD_FULL_OUT(0)             => fwd_full,\r
+    ---- reset\r
+      --MAKE_RESET_OUT           => open, -- reset by GbE --BUG: needs to be connected\r
+      ---- debug and status\r
+      --STATUS_OUT               => open,\r
+      --DEBUG_OUT                => open\r
+    --);\r
+      \r
+\r
+\r
+-----------------------------------------------------------------------------\r
+---- Test registers\r
+-----------------------------------------------------------------------------   \r
+--THE_REGS : process begin\r
+  --wait until rising_edge(clk_sys);\r
+  --busfwd_tx.ack <= '0';\r
+  --busfwd_tx.nack <= '0';\r
+  --busfwd_tx.unknown <= '0';\r
+  \r
+  --if busfwd_rx.write = '1' then\r
+    --busfwd_tx.ack <= '1';\r
+    --case busfwd_rx.addr(7 downto 0) is\r
+      --when x"00" => fwd_dst_ip    <= busfwd_rx.data;\r
+      --when x"01" => fwd_dst_port  <= busfwd_rx.data(15 downto 0);\r
+      --when x"02" => fwd_dst_mac(31 downto 0)  <= busfwd_rx.data;\r
+      --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0);\r
+      --when x"04" => fwd_length    <= busfwd_rx.data(15 downto 0);\r
+      --when x"05" => fwd_do_send   <= busfwd_rx.data(0);\r
+      --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+    --end case;\r
+  --elsif busfwd_rx.read = '1' then\r
+    --busfwd_tx.ack <= '1';\r
+    --case busfwd_rx.addr(7 downto 0) is\r
+      --when x"00" => busfwd_tx.data <= fwd_dst_ip;\r
+      --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port;\r
+      --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0);\r
+      --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32);\r
+      --when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
+      --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
+      --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+    --end case;  \r
+  --end if;\r
+  --if reset_i = '1' then\r
+    --fwd_do_send <= '0';\r
+  --end if;\r
+--end process;  \r
+      \r
+      \r
 ---------------------------------------------------------------------------\r
 -- Output stage\r
 ---------------------------------------------------------------------------   \r
@@ -526,8 +682,8 @@ end process;
       when 3 => out_data <= x"0000";\r
       when 4 => out_data <= x"5555";\r
       when 5 => out_data <= x"5555";\r
-      when 6 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
-      when 7 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy;\r
+      when 6 => out_data <= x"5555";\r
+      when 7 => out_data <= x"5555";\r
     end case;\r
   end process;  \r
 \r
@@ -535,15 +691,6 @@ end process;
   H4(3 downto 0) <= out_i(7 downto 4);\r
 \r
   \r
-  process begin\r
-    wait until rising_edge(clk_160);\r
-    if add_reg(31) = '0' then\r
-      dummy <= "01";\r
-    else\r
-      dummy <= not dummy;\r
-    end if;\r
-  end process;\r
-  \r
 ---------------------------------------------------------------------------\r
 -- Input stage\r
 ---------------------------------------------------------------------------\r
@@ -571,7 +718,7 @@ end process;
 -- readout_tx(0).data_write    <= '0';\r
 -- readout_tx(0).busy_release  <= '1';      \r
   \r
-  \r
+SFP_ADDON_TX_DIS <= (others => '0');  \r
 end architecture;\r
 \r
 \r