Revert "TRIGGER_OUT in adc clock domain"

This reverts commit 28614f883959e6e9c0691236e245beea34a7caed.

Conflicts:
	ADC/source/adc_processor_cfd.vhd

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index 27e2c19e8b3faa0fa67ce1e063ed9169187d8014..ad857482af8ffb2558669c031ab2828a5649dc32 100644 (file)
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -36,13 +36,13 @@ architecture arch of adc_processor_cfd is
   attribute syn_preserve : boolean;
   attribute syn_hier of arch : architecture is "hard";
 
-  signal CONF_adc : cfg_cfd_t := cfg_cfd_t_INIT;
-  attribute syn_keep of CONF_adc : signal is true;
-  attribute syn_preserve of CONF_adc : signal is true;
+  signal CONF_adc, CONF_sys : cfg_cfd_t := cfg_cfd_t_INIT;
+  attribute syn_keep of CONF_adc, CONF_sys : signal is true;
+  attribute syn_preserve of CONF_adc, CONF_sys : signal is true;
 
   signal trigger_gen, trigger_mask : std_logic_vector(CHANNELS - 1 downto 0);
   type debug_t is array (CHANNELS - 1 downto 0) of debug_cfd_t;
-  signal debug_adc : debug_t;
+  signal debug_adc, debug_sys : debug_t;
 
   signal reg_buffer_addr : std_logic_vector(4 downto 0) := (others => '0');
   signal reg_buffer_read : std_logic;
@@ -71,15 +71,17 @@ architecture arch of adc_processor_cfd is
   signal trigger_delay : unsigned(11 downto 0);
 begin
   CONF_adc <= CONFIG when rising_edge(CLK_ADC);
+  CONF_sys <= CONFIG when rising_edge(CLK_SYS);
   trigger_delay <= CONFIG.TriggerDelay when rising_edge(CLK_SYS);
   
-  trigger_mask <= CONF_adc.TriggerEnable((DEVICE + 1) * CHANNELS - 1 downto DEVICE * CHANNELS);
-  TRIGGER_OUT  <= or_all(trigger_gen and trigger_mask) when rising_edge(CLK_ADC);
+  trigger_mask <= CONF_sys.TriggerEnable((DEVICE + 1) * CHANNELS - 1 downto DEVICE * CHANNELS);
+  TRIGGER_OUT  <= or_all(trigger_gen and trigger_mask) when rising_edge(CLK_SYS);
 
+  debug_sys <= debug_adc when rising_edge(CLK_SYS);
   busy_in_adc <= busy_in_sys when rising_edge(CLK_ADC);
   busy_out_sys <= busy_out_adc when rising_edge(CLK_SYS);
   gen_cfd : for i in 0 to CHANNELS - 1 generate
-    trigger_gen(i) <= debug_adc(i).Trigger;
+    trigger_gen(i) <= debug_sys(i).Trigger;
     epoch_counter(i) <= debug_adc(i).EpochCounter when rising_edge(CLK_SYS);
     
     THE_CFD : entity work.adc_processor_cfd_ch