+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
---USE IEEE.std_logic_ARITH.ALL;
---USE IEEE.std_logic_UNSIGNED.ALL;
-USE IEEE.numeric_std.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
--- use work.trb_net16_hub_func.all;
-use work.version.all;
-use work.jtag_constants.all;
-use work.jtag_misc.all;
---use work.minmax.all;
---use work.monitor_config.all;
---use debug.fifo32bit;
-
-
-
-
-entity jtag_cmd_m26c is
- generic(
- MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
- MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
- MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
- MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
- MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
- MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
- MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
- MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
- MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
-
- WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
-
- READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
-
- JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
- JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
- JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
- JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
-
- RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit.
--- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
- JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
- JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
- JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2; -- ceil of ld( value plus one)
- RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz
-);
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- JTAG_TMS_OUT : out std_logic;
- JTAG_TCK_OUT : out std_logic;
- JTAG_TDI_OUT : out std_logic;
- JTAG_TDO_IN : in std_logic;
-
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- BUS_ADDR_IN : in std_logic_vector(8 downto 0);
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
-
- BUS_DATAREADY_OUT : out std_logic;
- BUS_NO_MORE_DATA_OUT : out std_logic;
- BUS_WRITE_ACK_OUT : out std_logic;
- BUS_UNKNOWN_ADDR_OUT : out std_logic;
-
- --OFF_SPILL_IN : in std_logic;
- RUN_REQUEST_IN : in std_logic;
- WRITE_ONCE_REQUEST_IN : in std_logic;
- MY_STATUS_OUT : out std_logic_vector(8 downto 0);
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- REQUEST_RESET_OUT : out std_logic;
- IDLE_OUT : out std_logic;
- PROG_JTAG_FINISHED_OUT:out std_logic;
- READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
- WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
- DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
- SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
- RUN_COUNTER_OUT : out std_logic_vector(31 downto 0);
-
- STARTED_OUT : out std_logic;
- LAST_RUN_SUCCESSFUL_OUT : out std_logic;
- LAST_DATA_CHANGED_OUT : out std_logic;
- LAST_WRITE_ERRORS_OUT : out std_logic;
- LAST_READ_ERRORS_OUT : out std_logic;
- CRC_ERROR_OUT : out std_logic
-
- --BUS_TIMEOUT_IN : in std_logic;
- );
-end entity;
-
-
-architecture arch_cmd_m26c of jtag_cmd_m26c is
-
--- component fifo32bit IS
--- port (
--- clk: IN std_logic;
--- din: IN std_logic_VECTOR(31 downto 0);
--- rd_en: IN std_logic;
--- rst: IN std_logic;
--- wr_en: IN std_logic;
--- dout: OUT std_logic_VECTOR(31 downto 0);
--- empty: OUT std_logic;
--- full: OUT std_logic;
--- overflow: OUT std_logic;
--- underflow: OUT std_logic);
--- end component;
-
-
-component jtag_pulses is
- generic (
- time_bits : integer := 10
- );
- port (
- CLK_IN : std_logic;
- RESET_IN : std_logic;
- -- input times
- JTAG_CLOCK_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
- JTAG_CLOCK_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
- JTAG_SAMPLE_TIME1_IN: in std_logic_vector(time_bits -1 downto 0);
- JTAG_SAMPLE_TIME2_IN: in std_logic_vector(time_bits -1 downto 0);
- JTAG_SAMPLE_TIME3_IN: in std_logic_vector(time_bits -1 downto 0);
- JTAG_SET_DATA_TIME_IN: in std_logic_vector(time_bits -1 downto 0);
-
-
- JTAG_CLOCK_CYCLE_LENGTH_IN: in std_logic_vector(time_bits -1 downto 0);
-
- -- output pulses
- BEGIN_JTAGBITCALC_OUT : out std_logic;
- JTAG_CLOCK_PULSE1_OUT : out std_logic;
- JTAG_CLOCK_PULSE2_OUT : out std_logic;
- JTAG_SAMPLE_PULSE1_OUT : out std_logic;
- JTAG_SAMPLE_PULSE2_OUT : out std_logic;
- JTAG_SAMPLE_PULSE3_OUT : out std_logic;
- JTAG_SET_DATA_PULSE_OUT : out std_logic
-
- );
-end component;
-
-component jtag_tck_out_component is
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- JTAG_CLOCK_PULSE1_IN : in std_logic;
- JTAG_CLOCK_PULSE2_IN : in std_logic;
- ENABLE_JTAG_TCK_IN : in std_logic;
-
- TCK_OUT : out std_logic
- );
-end component;
-
-component jtag_write_m10 is
- generic (
- RAM_JTAG_REGISTERS_DEPTH : integer;
- MAX_NUMCHIPS : integer;
- MAX_NUMCHIPS_LD : integer;
- MAX_NUMCHIPS_PLUS_ONE_LD : integer;
- MAX_REGISTERS_LD : integer;
- MAX_REGISTERS_PLUS_ONE_LD : integer;
- MAX_REGLEN_LD : integer;
- MAX_REGLEN_PLUS_ONE_LD : integer
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
-
- -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
- -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
- -- which should be interpreted as unsigned
- -- the zero'th entry points to the first not removed chip
- -- a value of (others => '1') means that no more non-removed chips follow
- NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
-
- BEGIN_JTAGBITCALC_IN : in std_logic;
- TRIGGER_BEGIN_WRITE_IN : in std_logic;
- IDLE_OUT : out std_logic;
-
- IS_DR_BIT_OUT : out std_logic;
- IS_FIRSTBIT_OUT : out std_logic;
- IS_LASTBIT_OUT : out std_logic;
- CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
- REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
- ENABLE_JTAG_CLOCK_OUT : out std_logic;
- LAST_TCK_CYCLE_OUT : out std_logic;
- TMS_OUT : out std_logic;
- TDI_OUT : out std_logic;
- EXPECTED_TDO_OUT : out std_logic;
-
- -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
- NUMREGS_CONFIGURED_OUT : out std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
-
- LAST_ERROR_CODE_OUT : out std_logic_vector(2 downto 0)
-
-
- );
-end component;
-
-component jtag_tdo_sample is
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
- -- the first sample is taken directly after this pulse
- SAMPLE_PULSE1_IN : in std_logic;
- SAMPLE_PULSE2_IN : in std_logic;
- SAMPLE_PULSE3_IN : in std_logic;
-
- -- TDO signal, which is to be sampled
- TDO_IN : in std_logic;
- -- sampled value of TDO
- TDO_SAMPLED_OUT : out std_logic;
- -- sampling error
- SAMPLING_ERROR_OUT : out std_logic
- );
-end component;
-
-component jtag_mux_buffer_tms_tdi_out_and_metainfo is
- generic (
- MAX_NUMCHIPS_LD : integer;
- MAX_REGISTERS_LD : integer
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- pulse when READ/WRITE/... entity's data should be taken and update
- -- the output values for TMS,TDI
- JTAG_SET_DATA_IN : in std_logic;
-
- -- read DEV_ID inputs
- RD_TMS_IN : in std_logic;
- RD_TDI_IN : in std_logic;
- RD_IS_DR_BIT_IN: in std_logic;
- RD_IS_FIRSTBIT_IN : in std_logic;
- RD_IS_LASTBIT_IN : in std_logic;
- RD_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
- RD_ENABLE_JTAG_CLOCK_IN : in std_logic;
- RD_LAST_TCK_CYCLE_IN : in std_logic;
- RD_EXPECTED_TDO_OUT : in std_logic;
-
- -- write registers inputs
- WR_TMS_IN : in std_logic;
- WR_TDI_IN : in std_logic;
- WR_IS_DR_BIT_IN: in std_logic;
- WR_IS_FIRSTBIT_IN : in std_logic;
- WR_IS_LASTBIT_IN : in std_logic;
- WR_CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
- WR_REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
- WR_ENABLE_JTAG_CLOCK_IN : in std_logic;
- WR_LAST_TCK_CYCLE_IN : in std_logic;
- WR_EXPECTED_TDO_OUT : in std_logic;
-
- -- test chain inputs
- TC_TMS_IN : in std_logic;
- TC_TDI_IN : in std_logic;
- TC_ENABLE_JTAG_CLOCK_IN : in std_logic;
- TC_LAST_TCK_CYCLE_IN : in std_logic;
-
- TMS_OUT : out std_logic;
- TDI_OUT : out std_logic;
- IS_DR_BIT_OUT: out std_logic;
- IS_FIRSTBIT_OUT : out std_logic;
- IS_LASTBIT_OUT : out std_logic;
- CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
- REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
- ENABLE_JTAG_CLOCK_OUT : out std_logic;
- LAST_TCK_CYCLE_OUT : out std_logic;
- EXPECTED_TDO_OUT : out std_logic
- );
-end component;
-
-component jtag_delay_expected_values is
- generic (
--- delay : integer := 0 -- number of whole jtag clock cycles to delay the expected values
--- -- because of total distance of the tck-line to the last chip and
--- -- the length of tdo of this chip back to the fpga
- ld_maxdelay : integer := 2;
- MAX_NUMCHIPS_LD : integer;
- MAX_REGISTERS_PLUS_ONE_LD : integer
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- SAMPLE_PULSE1_IN : in std_logic;
-
- -- chipcount as unsigned
- CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
- -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
- REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
-
- IS_DR_BIT_IN : in std_logic;
- -- firstbit signal: reset counters before sampling this bit
- IS_FIRSTBIT_IN : in std_logic;
- -- finish signal: dataout => RAM1b, compareout => RAM2
- IS_LASTBIT_IN : in std_logic;
-
- TDO_EXPECTED_IN : in std_logic;
-
-
- -- chipcount as unsigned
- OUT_CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
- -- active register as unsigned, =register 1,2,... of jtag_write_m10 or 0 for jtag_read_m10
- OUT_REGNUM_OUT : out std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
-
- OUT_IS_DR_BIT_OUT : out std_logic;
- -- firstbit signal: reset counters before sampling this bit
- OUT_IS_FIRSTBIT_OUT : out std_logic;
- -- finish signal: dataout => RAM1b, compareout => RAM2
- OUT_IS_LASTBIT_OUT : out std_logic;
-
- OUT_TDO_EXPECTED_OUT : out std_logic;
- DELAY_IN : in std_logic_vector(ld_maxdelay -1 downto 0)
-
- );
-end component;
-
-component jtag_tdo_compare_count_m10
- generic (
- MAX_NUMCHIPS_LD : integer;
- MAX_REGISTERS_PLUS_ONE_LD : integer;
- RAM_MATCH_DIFF_COUNT_DEPTH : integer;
- MAX_REGLEN_LD : integer
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- SAMPLE_PULSE3_D1_IN : in std_logic;
- -- active chip as unsigned
- CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
- -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
- REGNUM_IN : in std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
-
- ENABLE_COUNTERS_IN : in std_logic;
- IS_FIRSTBIT_IN : in std_logic;
- IS_LASTBIT_IN : in std_logic;
-
- TDO_EXPECTED_IN : in std_logic;
- TDO_SAMPLED_IN : in std_logic;
- TDO_SAMPLING_ERROR_IN : in std_logic;
-
-
- -- RAM2
- RAM_MATCH_DIFF_COUNT_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
- --RAM_MATCH_DIFF_COUNT_D_IN : in std_logic_vector(31 downto 0);
- RAM_MATCH_DIFF_COUNT_WE_OUT : out std_logic;
- RAM_MATCH_DIFF_COUNT_D_OUT : out std_logic_vector(31 downto 0)
-
- ---- internal error out: signals that read/write sampling has been mixed
- --INTERNAL_ERROR_OUT : out std_logic
-
- -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- );
-end component;
-
-component jtag_tdo_compare_counttotal_noram_m10
- generic (
- numcounts : integer := 3;
- se_counter_width : integer := 32; -- sampling error counter width
- diff_counter_width : integer := 16 -- counter width for number of runs in which there were differences
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- -- pulse always comes in same interval (at fixed distance to begin_jtag_bitcalc)
- -- sample_pulse3 delayed by one clock cycle
- SAMPLE_PULSE3_D1_IN : in std_logic;
- -- should this bit be counted as error if not matching expected value? (e.g. is this a dr bit while writing register or reading device id?)
- ENABLE_COUNTERS_IN : in std_logic;
-
- TDO_EXPECTED_IN : in std_logic;
- TDO_SAMPLED_IN : in std_logic;
- TDO_SAMPLING_ERROR_IN : in std_logic;
- BEGIN_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
- END_COUNT_I_IN : in std_logic_vector(numcounts-1 downto 0);
-
- -- should be zero if timing is good
- SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(diff_counter_width-1 downto 0);
- COUNTS_OUT : out std_logic_vector(numcounts*diff_counter_width-1 downto 0);
- LAST_VALUES_OUT : out std_logic_vector(numcounts-1 downto 0)
-
-
- );
-end component;
-
-
-component jtag_tdo_data_to_ram_m10
- generic (
- enable_ram1b : std_logic := '1';
- MAX_NUMCHIPS_LD : integer;
- MAX_REGISTERS_PLUS_ONE_LD : integer;
- MAX_REGLEN_LD : integer;
- RAM_JTAG_REGISTERS_DEPTH : integer
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- SAMPLE_PULSE3_D1_IN : in std_logic;
- -- active chip as unsigned
- CHIPNUM_IN : in std_logic_vector(MAX_NUMCHIPS_LD -1 downto 0);
- -- active register as unsigned, 0=read dev_id, 1,2,...=register 0,1,... of jtag_write_m10
- REGNUM_IN : in std_logic_vector(MAX_REGISTERS_PLUS_ONE_LD -1 downto 0);
-
- -- dataout => RAM1b
- ENABLE_DATAOUT_IN : in std_logic;
- IS_FIRSTBIT_IN : in std_logic;
- IS_LASTBIT_IN : in std_logic;
- TDO_SAMPLED_IN : in std_logic;
- -- RAM1b
- RAM_JTAG_REGISTERS_READOUT_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM_JTAG_REGISTERS_READOUT_D_IN : in std_logic_vector(31 downto 0);
- RAM_JTAG_REGISTERS_READOUT_WE_OUT : out std_logic;
- RAM_JTAG_REGISTERS_READOUT_D_OUT : out std_logic_vector(31 downto 0)
-
- -- Monitoring: 16 bit usable per FIFO, depth=512 = 8192 bits, this is enough for a 7 Mi26 chain (registers 1152 bits each)
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- );
-end component;
-
-component jtag_read_m26devid_m10 is
- generic (
- RAM_JTAG_REGISTERS_DEPTH : integer;
- MAX_NUMCHIPS_PLUS_ONE_LD : integer;
- MAX_NUMCHIPS : integer;
- MAX_NUMCHIPS_LD : integer
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- RAM_JTAG_REGISTERS_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM_JTAG_REGISTERS_D_IN : in std_logic_vector(31 downto 0);
-
- -- number of next chip which is not removed from the jtag chain. for chip i ( in range 0...N) this next chip is
- -- encoded by the bits NEXT_NOT_REMOVED((i+1)*MAX_NUMCHIPS_LD + MAX_NUMCHIPS_LD-1 downto (i+1)*MAX_NUMCHIPS_LD)
- -- which should be interpreted as unsigned
- -- the zero'th entry points to the first not removed chip
- -- a value of (others => '1') means that no more non-removed chips follow
- NEXT_NOT_REMOVED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
-
- BEGIN_JTAGBITCALC_IN : in std_logic;
- TRIGGER_BEGIN_READ_IN : in std_logic;
-
-
-
- IS_DR_BIT_OUT : out std_logic;
- IS_FIRSTBIT_OUT : out std_logic;
- IS_LASTBIT_OUT : out std_logic;
- CHIPNUM_OUT : out std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
- ENABLE_JTAG_CLOCK_OUT : out std_logic;
- LAST_TCK_CYCLE_OUT : out std_logic;
- TMS_OUT : out std_logic;
- TDI_OUT : out std_logic;
- EXPECTED_TDO_OUT : out std_logic;
- IDLE_OUT : out std_logic
- );
-end component;
-
-
-component jtag_bypassreg_testchain_m10 is
- generic (
--- delay : integer := 0; -- this is the same value as in jtag_delay_expected_values
- MAX_NUMCHIPS : integer;
- MAX_NUMCHIPS_LD : integer;
- JTAG_M26_IRLEN : integer;
-
- max_bitcounter_ld : integer;-- set to: MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-- bitcounter counts to ir_fill_ones_length, to zerofill_length aswell as from begin of sending pattern to end of receiving pattern (zerofill_length). should write something like: max(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD, 7)+1.
-
- ld_maxdelay : integer := 2; -- floor of ld maxdelay
- pattern_length : integer := 4;
- pattern : std_logic_vector(4-1 downto 0) := "1001";
- zerofill_numzeros_required : integer := 5 -- minimum number of zeros appearing at tdo while first zero filling phase
- );
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- BEGIN_JTAGBITCALC_IN : in std_logic;
- TRIGGER_BEGIN_TESTCHAIN_IN : in std_logic;
- IDLE_OUT : out std_logic;
-
- -- length in chips of the chain -- corresponds to the number of bits the
- -- output is shifted compared to the input, because the BYPASS registers
- -- are selected, which are only one bit long
- CHAIN_LENGTH_OUT : out std_logic_vector(max_bitcounter_ld-1 downto 0);
- -- if after feeding in a sufficiently long sequence
- -- the expected output pattern doesnt occur
- CHAIN_BROKEN_OUT : out std_logic;
-
- ENABLE_JTAG_CLOCK_OUT : out std_logic;
- LAST_TCK_CYCLE_OUT : out std_logic;
- TMS_OUT : out std_logic;
- TDI_OUT : out std_logic;
- TDO_IN : in std_logic;
- DELAY_IN : in std_logic_vector(ld_maxdelay-1 downto 0)
- );
-end component;
-
-component jtag_update_error_counts_ram3a is
- generic (
- MAX_NUMCHIPS : integer;
- MAX_NUMCHIPS_LD : integer;
- MAX_NUMCHIPS_PLUS_ONE_LD : integer;
- MAX_REGISTERS_LD : integer;
- MAX_REGISTERS_PLUS_ONE_LD : integer;
- MAX_REGISTERS_PLUS_TWO_LD : integer;
- RAM_MATCH_DIFF_COUNT_DEPTH : integer;
- RAM_ERROR_COUNTS_DEPTH : integer;
- WRITE_ERROR_THRESHOLD : integer;
- READ_ERROR_THRESHOLD : integer
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- TRIGGER_UPDATE_DATA_CHANGED_IN : in std_logic;
- TRIGGER_UPDATE_READ_ERRORS_IN : in std_logic;
- TRIGGER_UPDATE_WRITE_ERRORS_IN : in std_logic;
- TRIGGER_UPDATE_RUN_COUNTER_IN : in std_logic;
- RUN_COUNTER_IN : in std_logic_vector(31 downto 0);
- -- RAM2
- RAM2_A_OUT : out std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
- RAM2_D_IN : in std_logic_vector(31 downto 0);
- -- RAM3a
- RAM3A_A_OUT : out std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
- RAM3A_D_IN : in std_logic_vector(31 downto 0);
- RAM3A_D_OUT : out std_logic_vector(31 downto 0);
- RAM3A_WR_OUT :out std_logic;
-
- REMOVED_CHIPS_IN : in std_logic_vector(MAX_NUMCHIPS -1 downto 0);
- NUMCHIPS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
- -- from (i+1)*MAX_REGISTERS_PLUS_ONE_LD-1 downto (i)*MAX_REGISTERS_PLUS_ONE_LD: numregs configured of chip i=(0, 1, 2, ...)
- NUMREGS_CONFIGURED_IN : in std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
-
- -- if true, there were read errors in last dev_id read
- READ_ERRORS_OUT : out std_logic;
- -- if true, there were read errors the last double write to registers (value read the second time didn't equal programmed value)
- WRITE_ERRORS_OUT : out std_logic;
- -- if true, the data read from the registers wasn't equal to the data programmed a period before (for example in the last spill break)
- DATA_CHANGED_OUT : out std_logic;
-
- IDLE_OUT : out std_logic
- );
-end component;
-
-component jtag_init_ram1b is
- generic (
- RAM_JTAG_REGISTERS_DEPTH : integer;
- MAX_NUMCHIPS_LD : integer;
- MAX_REGISTERS_LD : integer
- );
- port (
- CLK_IN : std_logic;
- RESET_IN : std_logic;
- TRIGGER_INIT_IN : std_logic;
- -- RAM1a
- RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM1A_D_IN : in std_logic_vector(31 downto 0);
- -- RAM1b
- RAM1B_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM1B_D_IN : in std_logic_vector(31 downto 0);
- RAM1B_WE_OUT : out std_logic;
- RAM1B_D_OUT : out std_logic_vector(31 downto 0);
-
- IDLE_OUT : out std_logic
- );
-end component;
-
-
-component copy_ram is
- generic (
- ram_depth : integer;
- ram_width : integer := 32
- );
- port (
- CLK_IN : std_logic;
- RESET_IN : std_logic;
- TRIGGER_COPY_IN : std_logic;
- -- RAM3a
- RAMA_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
- RAMA_D_IN : in std_logic_vector(ram_width-1 downto 0);
- -- RAM3b
- RAMB_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
- RAMB_D_OUT : out std_logic_vector(ram_width-1 downto 0);
- RAMB_WR_OUT :out std_logic;
-
- IDLE_OUT : out std_logic
- );
-end component;
-
-component blank_ram is
- generic (
- ram_depth : integer;
- ram_width : integer := 32
- );
- port (
- CLK_IN : std_logic;
- RESET_IN : std_logic;
- TRIGGER_BLANK_IN : std_logic;
- -- RAM
- RAM_A_OUT : out std_logic_vector(ram_depth-1 downto 0);
- RAM_D_OUT : out std_logic_vector(ram_width-1 downto 0);
- RAM_WR_OUT :out std_logic;
-
- IDLE_OUT : out std_logic
- );
-end component;
-
-
-component jtag_check_crc_ram1a is
- generic (
- RAM_JTAG_REGISTERS_DEPTH : integer;
- MAX_NUMCHIPS : integer;
- MAX_NUMCHIPS_LD : integer;
- MAX_NUMCHIPS_PLUS_ONE_LD : integer;
- MAX_REGLEN_PLUS_ONE_LD : integer;
- MAX_REGISTERS_LD : integer
- );
- port (
- CLK_IN : std_logic;
- RESET_IN : std_logic;
- TRIGGER_CHECK_IN : std_logic;
- -- RAM1a
- RAM1A_A_OUT : out std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- RAM1A_D_IN : in std_logic_vector(31 downto 0);
-
- NUMCHIPS_IN : in std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
- CRC_OK_OUT : out std_logic_vector(MAX_NUMCHIPS-1 downto 0);
- IDLE_OUT : out std_logic
- );
-end component;
-
-
-component ram_dp is
- generic(
- depth : integer := 9;
- width : integer := 32
- );
- port(
- CLK : in std_logic;
- wr1 : in std_logic;
- a1 : in std_logic_vector(depth-1 downto 0);
- dout1 : out std_logic_vector(width-1 downto 0);
- din1 : in std_logic_vector(width-1 downto 0);
- a2 : in std_logic_vector(depth-1 downto 0);
- dout2 : out std_logic_vector(width-1 downto 0)
- );
-end component;
-
-component ram_mux2to1_readport is
- generic (
- depth : integer;
- width : integer := 32
- );
- port (
- SELECT_IN : std_logic;
- A0_IN : in std_logic_vector(depth-1 downto 0);
- D0_OUT : out std_logic_vector(width-1 downto 0);
- A1_IN : in std_logic_vector(depth-1 downto 0);
- D1_OUT : out std_logic_vector(width-1 downto 0);
-
- RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
- RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
- );
-end component;
-
-component ram_mux4to1_readport is
- generic (
- depth : integer;
- width : integer := 32
- );
- port (
- SELECT_IN : in std_logic_vector(1 downto 0); -- two bit select input
- A0_IN : in std_logic_vector(depth-1 downto 0);
- D0_OUT : out std_logic_vector(width-1 downto 0);
- A1_IN : in std_logic_vector(depth-1 downto 0);
- D1_OUT : out std_logic_vector(width-1 downto 0);
- A2_IN : in std_logic_vector(depth-1 downto 0);
- D2_OUT : out std_logic_vector(width-1 downto 0);
- A3_IN : in std_logic_vector(depth-1 downto 0);
- D3_OUT : out std_logic_vector(width-1 downto 0);
-
- RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
- RAM_DOUT_IN : in std_logic_vector(width-1 downto 0)
- );
-end component;
-
-component ram_mux2to1_writeport is
- generic (
- depth : integer;
- width : integer := 32
- );
- port (
- SELECT_IN : in std_logic;
- A0_IN : in std_logic_vector(depth-1 downto 0);
- D0_OUT : out std_logic_vector(width-1 downto 0);
- WR0_IN : in std_logic;
- DIN0_IN : in std_logic_vector(width-1 downto 0);
-
- A1_IN : in std_logic_vector(depth-1 downto 0);
- D1_OUT : out std_logic_vector(width-1 downto 0);
- WR1_IN : in std_logic;
- DIN1_IN : in std_logic_vector(width-1 downto 0);
-
- RAM_A_OUT : out std_logic_vector(depth-1 downto 0);
- RAM_DOUT_IN : in std_logic_vector(width-1 downto 0);
- RAM_WR_OUT : out std_logic;
- RAM_DIN_OUT : out std_logic_vector(width-1 downto 0)
- );
-end component;
-
-
-
--- component priorityencoder_seq is
- -- generic ( n : positive;
- -- ldn:positive -- rounded up ld(n + 1)
- -- );
- -- Port ( CLK_IN : in STD_LOGIC;
- -- RESET_IN : in STD_LOGIC;
- -- input_vect_IN : in STD_LOGIC_VECTOR (n - 1 downto 0);
- -- enc_pos_OUT : out STD_LOGIC_VECTOR (ldn - 1 downto 0);
- -- start_IN : in STD_LOGIC;
- -- enc_pos_valid_OUT : out STD_LOGIC );
--- end component;
-
--- function ld(m:positive) return natural is
--- variable n : positive;
--- begin
--- n = 0;
--- a: loop
--- if (2**n >= m) then
--- return n;
--- end if;
--- n = n + 1;
--- end loop a;
--- end;
-
-component trb_net16_regio_bus_handler is
- generic(
- PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;
- PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
- PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
- DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
- DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
- DAT_READ_ENABLE_IN : in std_logic; -- read pulse
- DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse
- DAT_TIMEOUT_IN : in std_logic; -- access timed out
- DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested
- DAT_WRITE_ACK_OUT : out std_logic; -- data accepted
- DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
- DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
-
- BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);
- BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);
- BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);
-
- BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);
- BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
- BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);
-
- STAT_DEBUG : out std_logic_vector(31 downto 0)
- );
-end component;
-
-constant STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
-constant STATUS_WRITE_ERROR : integer := MAX_NUMCHIPS;
-constant STATUS_WRITE_ERROR2 : integer := 2*MAX_NUMCHIPS;
-constant STATUS_READ_ERROR : integer := 3*MAX_NUMCHIPS;
-constant STATUS_READ_ERROR2 : integer := 4*MAX_NUMCHIPS;
-constant STATUS_DATA_CHANGED : integer := 5*MAX_NUMCHIPS;
-
-constant WRITE_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
-constant WRITE_STATUS_DATA_CHANGED : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant READ_STATUS_JTAG_ERROR : integer := 0; -- length MAX_NUMCHIPS
-constant READ_STATUS_BIT_ERROR : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-
-constant RAM_MATCH_DIFF_COUNT_DEPTH : integer := MAX_NUMCHIPS_LD + MAX_REGISTERS_PLUS_ONE_LD + 1;--9; -- maximum 32 counts / chip (one for read DEV_ID register, rest for read/write data registers), maximum 16 chips, each count 32 bits
-constant RAM_ERROR_COUNTS_DEPTH : integer := MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD; --10; -- ld(8+4*MAX_REGISTERS)+MAX_NUMCHIPS_LD= MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUMCHIPS_LD
-
-
-
-
---type BUS_RW_STATE_TYPE is (BUS_RW_STATE_IDLE, BUS_RW_STATE_READ_RAM_WAIT, BUS_RW_STATE_READ_RAM, BUS_RW_STATE_WRITE_RAM, BUS_RW_STATE_RETURN_READ, BUS_RW_STATE_RETURN_WRITE);
-
---signal bus_rw_state, bus_rw_state_next : BUS_RW_STATE_TYPE;
---signal dev_state, dev_state_next : DEVICE_STATE_TYPE;
-signal data_register, data_register_next : std_logic_vector(31 downto 0);
---signal cmd_register, cmd_register_next : std_logic_vector(31 downto 0);
---signal length_register, length_register_next : std_logic_vector(31 downto 0);
-signal jtag_refresh_active, jtag_refresh_active_next : std_logic;
-signal jtag_check1_active, jtag_check1_active_next : std_logic;
-signal jtag_refresh_active_last, jtag_refresh_active_last_next : std_logic;
--- has to fit number of 32 bit words needed to represent the status register
---signal status_register_pos, status_register_pos_next : std_logic_vector(MAX_NUMCHIPS_LD+2+MAX_REGISTERS_LD-5 downto 0);
---signal status_register_read_running, status_register_read_running_next : std_logic;
-
--- mostly for debug purposes: status bits
---signal my_status, my_status_next : std_logic_vector(8 downto 0);
-
--- status register layout:
--- bits MAX_NUMCHIPS -1 downto 0 : JTAG ERROR
--- bits 2*MAX_NUMCHIPS -1 downto MAX_NUMCHIPS : WRITE ERROR
--- bits 3*MAX_NUMCHIPS -1 downto 2*MAX_NUMCHIPS : WRITE ERROR2
--- bits 4*MAX_NUMCHIPS -1 downto 3*MAX_NUMCHIPS : READ ERROR
--- bits 5*MAX_NUMCHIPS -1 downto 4*MAX_NUMCHIPS : READ ERROR2
--- bits 6*MAX_NUMCHIPS -1 downto 5*MAX_NUMCHIPS : DATA CHANGED
-
---signal status_register, status_register_next : std_logic_vector(6*MAX_NUMCHIPS-1 downto 0);
-signal crc_status_register, crc_status_register_next : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
-
---signal status_register_read_error2, status_register_read_error2_next : std_logic;
-
---signal already_written, already_written_next : std_logic;
--- contains a "1" at the positions of deactivated sensors
-signal removed_chips, removed_chips_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
-signal last_not_removed, last_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
-signal first_not_removed, first_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0);
---signal reactivate_sensor, reactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
---signal reactivate_sensor_strobe , reactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
---signal deactivate_sensor, deactivate_sensor_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
---signal deactivate_sensor_strobe , deactivate_sensor_strobe_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0);
-
---signal disable_write, disable_write_next : std_logic;
---signal disable_writeerror_for_remove, disable_writeerror_for_remove_next : std_logic;
---signal disable_remove, disable_remove_next : std_logic;
---signal debug_one_remove, debug_one_remove_next : std_logic;
---signal debug_one_remove_strobe, debug_one_remove_strobe_next : std_logic;
---signal removed_strobe, removed_strobe_next : std_logic;
---signal m26c_sensor_cand, m26c_sensor_cand_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-
-signal cc_chip_i, cc_chip_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
-signal cc_nextnotremoved_i, cc_nextnotremoved_i_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
-signal chip_counter_start, chip_counter_start_next : std_logic;
-type CC_STATE_TYPE is (CC_IDLE, CC_COUNT_SENSOR, CC_SETNUMCHIPS);
-signal cc_state, cc_state_next : CC_STATE_TYPE;
-
-
---type REGISTER_POINTER_TYPE is range MAX_REGISTERS-1 downto 0;
--- signal status_register_reg_sel, status_register_reg_sel_next : std_logic_vector(MAX_REGISTERS_LD -1 downto 0);
--- signal status_register_reg_sel_pos, status_register_reg_sel_pos_next : std_logic_vector( (MAX_NUMCHIPS_LD +2 -5)-1 downto 0);
---signal mux_sel, mux_sel_next : std_logic;
---signal driver_data_out : std_logic;
---signal driver_ready_for_cmd : std_logic;
---signal driver_state_out : std_logic_vector(8 downto 0);
---signal driver_data_arrived : std_logic;
---signal driver_data_in : std_logic;
---signal driver_cmd_in : std_logic_vector(3 downto 0);
---signal driver_speed , driver_speed_next : std_logic_vector(15 downto 0);
-
---signal bus_data_out_buffer, bus_data_out_buffer_next : std_logic_vector(31 downto 0);
---signal bus_dataready, bus_dataready_next : std_logic;
---signal bus_no_more_data, bus_no_more_data_next : std_logic;
---signal bus_write_ack, bus_write_ack_next : std_logic;
---signal bus_unknown_addr, bus_unknown_addr_next : std_logic;
-
-signal ram1a_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal ram1a_dout2 : std_logic_vector(31 downto 0);
-
-signal ram1a_a1_base_addr, ram1a_a1_base_addr_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-signal ram1a_a1_rel_addr, ram1a_a1_rel_addr_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
-signal ram1a_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal ram1a_din1, ram1a_din1_next : std_logic_vector(31 downto 0);
-signal ram1a_wr1, ram1a_wr1_next : std_logic;
-signal ram1a_dout1 : std_logic_vector(31 downto 0);
-
-signal ram1b_a2, ram1b_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal ram1b_dout2 : std_logic_vector(31 downto 0);
-
-signal ram1a_select, ram1a_select_next : std_logic_vector(1 downto 0);
-
-signal ram1b_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal ram1b_din1 : std_logic_vector(31 downto 0);
-signal ram1b_wr1 : std_logic;
-signal ram1b_dout1 : std_logic_vector(31 downto 0);
-signal ram1b_select, ram1b_select_next : std_logic;
-
-signal init_ram1b_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal init_ram1b_ram1a_d : std_logic_vector(31 downto 0);
-signal init_ram1b_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal init_ram1b_ram1b_dout : std_logic_vector(31 downto 0);
-signal init_ram1b_ram1b_din : std_logic_vector(31 downto 0);
-signal init_ram1b_ram1b_wr : std_logic;
-
-signal jtag_data_to_ram_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal jtag_data_to_ram_ram1b_dout : std_logic_vector(31 downto 0);
-signal jtag_data_to_ram_ram1b_din : std_logic_vector(31 downto 0);
-signal jtag_data_to_ram_ram1b_wr : std_logic;
-
-signal jtag_check_crc_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal jtag_check_crc_ram1a_d : std_logic_vector(31 downto 0);
-
-
--- ram2 port 2: local flipflops
---signal ram2_a2, ram2_a2_next : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
---signal ram2_dout2 : std_logic_vector(31 downto 0);
--- ram2 port 1: non local flipflops, all connected to components
-signal ram2_a1 : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
-signal ram2_din1 : std_logic_vector(31 downto 0);
-signal ram2_wr1 : std_logic;
-signal ram2_dout1 : std_logic_vector(31 downto 0);
-signal ram2_select, ram2_select_next : std_logic;
-
--- ram3a port 2: local flipflops
-signal ram3a_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal ram3a_dout2 : std_logic_vector(31 downto 0);
-
--- ram3a port 1: non local flipflops, all connected to components
-signal ram3a_a1 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal ram3a_din1 : std_logic_vector(31 downto 0);
-signal ram3a_wr1 : std_logic;
-signal ram3a_dout1 : std_logic_vector(31 downto 0);
-
--- ram3b port 1: non local flipflops, all connected to components
- -- see jtag_copy_ram3* signals
--- ram3b port 2: local flipflops
-signal ram3b_a2_base_addr, ram3b_a2_base_addr_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0);
-signal ram3b_a2_rel_addr, ram3b_a2_rel_addr_next : std_logic_vector(3 downto 0);
-signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal ram3b_dout2 : std_logic_vector(31 downto 0);
-
-signal ram3a_select, ram3a_select_next : std_logic;
-signal ram3a_rd_select, ram3a_rd_select_next : std_logic;
-
-signal jtag_tdo_compare_count_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
-signal jtag_tdo_compare_count_ram_dout : std_logic_vector(31 downto 0);
-signal jtag_tdo_compare_count_ram_din : std_logic_vector(31 downto 0);
-signal jtag_tdo_compare_count_ram_wr : std_logic;
-
---signal jtag_update_error_counts_ram_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
---signal jtag_update_error_counts_ram_d : std_logic_vector(31 downto 0);
-
-
-
-
-
---signal trigger_counter, trigger_counter_next : std_logic_vector(27 downto 0);
---signal trigger_counter, trigger_counter_next : std_logic_vector(10 downto 0);
-
-
-
-signal idle_out_signal, idle_out_signal_next : std_logic;
-
---signal write_status_register : std_logic_vector((3*MAX_NUMCHIPS) * MAX_REGISTERS -1 downto 0);
---signal write_status_register_or, write_status_register_or_next : std_logic_vector((3*MAX_NUMCHIPS) -1 downto 0);
---signal write_crc_status_register : std_logic_vector(MAX_REGISTERS - 1 downto 0);
---signal write_cmd_out : std_logic_vector(3 downto 0);
---signal write_data_out : std_logic;
---signal write_idle : std_logic;
---signal write_trigger, write_trigger_next : std_logic;
---signal write_idle_last, write_idle_last_next : std_logic;
---signal write_state_out : std_logic_vector(7 downto 0);
---type ERROR_COUNTER_TYPE is array (MAX_NUMCHIPS -1 downto 0) of std_logic_vector(9 downto 0);
---signal write_error_counter, write_error_counter_next : ERROR_COUNTER_TYPE;
---signal write_error_over_threshold_counter, write_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
---signal write_data_changed_counter, write_data_changed_counter_next : ERROR_COUNTER_TYPE;
---constant MAX_ERROR_COUNT : std_logic_vector(9 downto 0) := "1111111111";
-
---signal read_cmd_out : std_logic_vector(3 downto 0);
---signal read_data_out : std_logic;
---signal read_trigger, read_trigger_next : std_logic;
---signal read_status_register : std_logic_vector(3*MAX_NUMCHIPS -1 downto 0);
---signal read_idle : std_logic;
---signal read_idle_last, read_idle_last_next : std_logic;
---signal read_state_out : std_logic_vector(7 downto 0);
---signal read_error_counter, read_error_counter_next : ERROR_COUNTER_TYPE;
---signal read_error_over_threshold_counter, read_error_over_threshold_counter_next : ERROR_COUNTER_TYPE;
-
-signal numchips_configured, numchips_configured_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
-signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
-signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0);
-
-signal debug_m26cs_state, debug_m26cs_state_next : std_logic_vector(7 downto 0);
-signal debug_test, debug_test_next : std_logic_vector(31 downto 0);
-
-signal debug_trigger_counter, debug_trigger_counter_next : unsigned(31 downto 0);
-
---signal bus2_ram_addr_out : std_logic_vector(7 downto 0);
-signal bus2_ram_addr_out : std_logic_vector(15 downto 0);
-signal bus2_ram_data_out : std_logic_vector(31 downto 0);
-signal bus2_ram_read_enable_out : std_logic;
-signal bus2_ram_write_enable_out : std_logic;
-signal bus2_ram_timeout_out : std_logic;
-
-signal bus2_ram_data_in, bus2_ram_data_in_next : std_logic_vector(31 downto 0);
-signal bus2_ram_dataready_in, bus2_ram_dataready_in_next : std_logic;
-signal bus2_ram_write_ack_in, bus2_ram_write_ack_in_next : std_logic;
-signal bus2_ram_no_more_data_in, bus2_ram_no_more_data_in_next : std_logic;
-signal bus2_ram_unknown_addr_in, bus2_ram_unknown_addr_in_next : std_logic;
-
---signal bus2_status_addr_out : std_logic_vector(4 downto 0);
-signal bus2_status_addr_out : std_logic_vector(15 downto 0);
-signal bus2_status_data_out : std_logic_vector(31 downto 0);
-signal bus2_status_read_enable_out : std_logic;
-signal bus2_status_write_enable_out : std_logic;
-signal bus2_status_timeout_out : std_logic;
-
-signal bus2_status_data_in, bus2_status_data_in_next : std_logic_vector(31 downto 0);
-signal bus2_status_dataready_in, bus2_status_dataready_in_next : std_logic;
-signal bus2_status_write_ack_in, bus2_status_write_ack_in_next : std_logic;
-signal bus2_status_no_more_data_in, bus2_status_no_more_data_in_next : std_logic;
-signal bus2_status_unknown_addr_in, bus2_status_unknown_addr_in_next : std_logic;
-
---signal bus2_status2_addr_out : std_logic_vector(4 downto 0);
-signal bus2_status2_addr_out : std_logic_vector(15 downto 0);
-signal bus2_status2_data_out : std_logic_vector(31 downto 0);
-signal bus2_status2_read_enable_out : std_logic;
-signal bus2_status2_write_enable_out : std_logic;
-signal bus2_status2_timeout_out : std_logic;
-
-signal bus2_status2_data_in, bus2_status2_data_in_next : std_logic_vector(31 downto 0);
-signal bus2_status2_dataready_in, bus2_status2_dataready_in_next : std_logic;
-signal bus2_status2_write_ack_in, bus2_status2_write_ack_in_next : std_logic;
-signal bus2_status2_no_more_data_in, bus2_status2_no_more_data_in_next : std_logic;
-signal bus2_status2_unknown_addr_in, bus2_status2_unknown_addr_in_next : std_logic;
-
-signal bus2_status2_read_ram3b, bus2_status2_read_ram3b_next : std_logic;
-signal buf_bus2_status2_read_ram3b, buf_bus2_status2_read_ram3b_next : std_logic;
-
-signal status2_run_counter, status2_run_counter_next : unsigned(31 downto 0);
-
-signal status2_chain_status, status2_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
-signal status2_copy_finished: std_logic;
-
-
---signal bus2_control_addr_out : std_logic_vector(4 downto 0);
-signal bus2_control_addr_out : std_logic_vector(15 downto 0);
-signal bus2_control_data_out : std_logic_vector(31 downto 0);
-signal bus2_control_read_enable_out : std_logic;
-signal bus2_control_write_enable_out : std_logic;
-signal bus2_control_timeout_out : std_logic;
-
-signal bus2_control_data_in, bus2_control_data_in_next : std_logic_vector(31 downto 0);
-signal bus2_control_dataready_in, bus2_control_dataready_in_next : std_logic;
-signal bus2_control_write_ack_in, bus2_control_write_ack_in_next : std_logic;
-signal bus2_control_no_more_data_in, bus2_control_no_more_data_in_next : std_logic;
-signal bus2_control_unknown_addr_in, bus2_control_unknown_addr_in_next : std_logic;
-
---signal bus2_debug_addr_out : std_logic_vector(4 downto 0);
-signal bus2_debug_addr_out : std_logic_vector(15 downto 0);
-signal bus2_debug_data_out : std_logic_vector(31 downto 0);
-signal bus2_debug_read_enable_out : std_logic;
-signal bus2_debug_write_enable_out : std_logic;
-signal bus2_debug_timeout_out : std_logic;
-
-signal bus2_debug_data_in, bus2_debug_data_in_next : std_logic_vector(31 downto 0);
-signal bus2_debug_dataready_in, bus2_debug_dataready_in_next : std_logic;
-signal bus2_debug_write_ack_in, bus2_debug_write_ack_in_next : std_logic;
-signal bus2_debug_no_more_data_in, bus2_debug_no_more_data_in_next : std_logic;
-signal bus2_debug_unknown_addr_in, bus2_debug_unknown_addr_in_next : std_logic;
-
-signal buf_bus2_ram_read_enable_out, buf_bus2_ram_read_enable_out_next : std_logic;
-signal buf_buf_bus2_ram_read_enable_out, buf_buf_bus2_ram_read_enable_out_next : std_logic;
--- monitoring
---signal read_mon_write_out : std_logic;
--- off_spill timer (htcounter)
---signal htcounter_next, htcounter : unsigned(26 downto 0); -- 27 bit = approx 1.34 seconds
---signal have_time_for_write, have_time_for_write_next : std_logic;
-signal prog_jtag_finished, prog_jtag_finished_next : std_logic;
---signal last_write_successful, last_write_successful_next : std_logic;
-
--- BEGIN NEW SIGNALS
-signal jtag_next_not_removed, jtag_next_not_removed_next : std_logic_vector(MAX_NUMCHIPS_PLUS_ONE_LD*(MAX_NUMCHIPS+1)-1 downto 0);
-signal jtag_write_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal jtag_write_ram1a_d : std_logic_vector(31 downto 0);
-signal trigger_jtag_write, trigger_jtag_write_next : std_logic;
-signal jtag_write_is_dr_bit : std_logic;
-signal jtag_write_is_firstbit : std_logic;
-signal jtag_write_is_lastbit : std_logic;
-signal jtag_write_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-signal jtag_write_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
-signal jtag_write_enable_jtag_clock : std_logic;
-signal jtag_write_last_tck_cycle : std_logic;
-signal jtag_write_tms : std_logic;
-signal jtag_write_tdi : std_logic;
-signal jtag_write_expected_tdo : std_logic;
-signal jtag_write_idle : std_logic;
-signal jtag_write_last_error_code: std_logic_vector(2 downto 0);
-signal jtag_write_numregs_configured : std_logic_vector(MAX_NUMCHIPS*(MAX_REGISTERS_PLUS_ONE_LD)-1 downto 0);
-
-signal jtag_read_ram1a_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal jtag_read_ram1a_d : std_logic_vector(31 downto 0);
-signal trigger_jtag_read, trigger_jtag_read_next : std_logic;
-signal jtag_read_is_dr_bit : std_logic;
-signal jtag_read_is_firstbit : std_logic;
-signal jtag_read_is_lastbit : std_logic;
-signal jtag_read_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-signal jtag_read_enable_jtag_clock : std_logic;
-signal jtag_read_last_tck_cycle : std_logic;
-signal jtag_read_tms : std_logic;
-signal jtag_read_tdi : std_logic;
-signal jtag_read_expected_tdo : std_logic;
-signal jtag_read_idle : std_logic;
-
---signal trigger_bypassreg, trigger_bypassreg_next : std_logic;
-signal jtag_bypassreg_idle : std_logic;
-signal jtag_bypassreg_length : std_logic_vector(MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7-1 downto 0);
-signal jtag_bypassreg_chain_broken : std_logic;
-signal jtag_bypassreg_enable_jtag_clock : std_logic;
-signal jtag_bypassreg_last_tck_cycle : std_logic;
-signal jtag_bypassreg_tms : std_logic;
-signal jtag_bypassreg_tdi : std_logic;
--- begin: global_jtag_counter settings
-signal jtag_clock_cycle_length, jtag_clock_cycle_length_next : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us)
-signal jtag_clock_time1, jtag_clock_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
-signal jtag_clock_time2, jtag_clock_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
-signal jtag_sample_time1, jtag_sample_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
-signal jtag_sample_time2, jtag_sample_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
-signal jtag_sample_time3, jtag_sample_time3_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
-signal jtag_set_data_time, jtag_set_data_time_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution
--- begin: periodic pulses, periodic with global_jtag_counter
-signal begin_jtag_bitcalc : std_logic;
-signal jtag_sample_pulse1 : std_logic;
-signal jtag_sample_pulse2 : std_logic;
-signal jtag_sample_pulse3 : std_logic;
-signal jtag_sample_pulse3_d1, jtag_sample_pulse3_d1_next : std_logic;
-signal jtag_set_data_pulse : std_logic;
--- end: periodic pulses
-
-signal jtag_tdo_sampled : std_logic;
-signal jtag_tdo_sampling_error : std_logic;
-
-signal jtag_tms : std_logic;
-signal jtag_tdi : std_logic;
-signal jtag_enable_clock : std_logic;
-
-signal jtag_meta_is_dr_bit : std_logic;
-signal jtag_meta_is_firstbit : std_logic;
-signal jtag_meta_is_lastbit : std_logic;
-signal jtag_meta_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-signal jtag_meta_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
-signal jtag_meta_last_tck_cycle : std_logic;
-signal jtag_meta_expected_tdo : std_logic;
-
-signal jtag_delayed_is_dr_bit : std_logic;
-signal jtag_delayed_is_firstbit : std_logic;
-signal jtag_delayed_is_lastbit : std_logic;
-signal jtag_delayed_chipnum : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0);
-signal jtag_delayed_regnum : std_logic_vector(MAX_REGISTERS_LD-1 downto 0);
-signal jtag_delayed_tdo_expected : std_logic;
-
--- jtag_update_error_counts
-signal trigger_juec_update_d_ch, trigger_juec_update_d_ch_next : std_logic;
-signal trigger_juec_update_rd_err, trigger_juec_update_rd_err_next : std_logic;
-signal trigger_juec_update_wr_err, trigger_juec_update_wr_err_next : std_logic;
-signal trigger_juec_update_run_counter, trigger_juec_update_run_counter_next : std_logic;
-signal juec_ram2_a : std_logic_vector(RAM_MATCH_DIFF_COUNT_DEPTH-1 downto 0);
-signal juec_ram2_dout : std_logic_vector(31 downto 0);
-signal juec_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal juec_ram3a_dout : std_logic_vector(31 downto 0);
-signal juec_ram3a_din : std_logic_vector(31 downto 0);
-signal juec_ram3a_wr : std_logic;
-signal juec_idle : std_logic;
-signal juec_data_changed : std_logic;
-signal juec_read_errors : std_logic;
-signal juec_write_errors : std_logic;
-
-signal jtag_copy_ram3_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal jtag_copy_ram3_ram3a_dout : std_logic_vector(31 downto 0);
-signal jtag_copy_ram3_ram3b_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal jtag_copy_ram3_ram3b_din : std_logic_vector(31 downto 0);
-signal jtag_copy_ram3_ram3b_wr : std_logic;
-signal jtag_copy_ram3_idle : std_logic;
-
-
-signal trigger_blank_ram3a, trigger_blank_ram3a_next : std_logic;
-signal jtag_blank_ram3a_ram3a_a : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0);
-signal jtag_blank_ram3a_ram3a_din : std_logic_vector(31 downto 0);
-signal jtag_blank_ram3a_ram3a_wr : std_logic;
-signal jtag_blank_ram3a_idle : std_logic;
-
-
-type M26CS_STATE_TYPE is (M26CSS_STOPPED, M26CSS_CHECK1_WAIT_FOR_HAVE_TIME, M26CSS_WAIT_FOR_TRIGGER, M26CSS_CHECK_CRC_RAM1A_BEGIN, M26CSS_CHECK_CRC_RAM1A_WAIT, M26CSS_INIT_RAM1B_BEGIN, M26CSS_INIT_RAM1B_WAIT, M26CSS_DATA_CHANGED_BEGIN, M26CSS_DATA_CHANGED_WAIT, M26CSS_BLANK_RAM3A_WAIT, M26CSS_JUEC_DATA_CHANGED_BEGIN, M26CSS_JUEC_DATA_CHANGED_WAIT, M26CSS_COUNT_CHIPS_BEGIN, M26CSS_COUNT_CHIPS_WAIT, M26CSS_BYPASSREG_BEGIN, M26CSS_BYPASSREG_WAIT, M26CSS_READ1_BEGIN, M26CSS_READ1_WAIT, M26CSS_JUEC_READ_BEGIN, M26CSS_JUEC_READ_WAIT, M26CSS_REQUEST_RESET_BEGIN, M26CSS_REQUEST_RESET_WAIT, M26CSS_REQUESTED_RESET_WAIT, M26CSS_WRITE1_BEGIN, M26CSS_WRITE1_WAIT, M26CSS_WRITE2_BEGIN, M26CSS_WRITE2_WAIT, M26CSS_JUEC_WRITE_BEGIN, M26CSS_JUEC_WRITE_WAIT, M26CSS_JUEC_RUN_COUNTER_BEGIN, M26CSS_JUEC_RUN_COUNTER_WAIT,
-M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN, M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT, M26CSS_WRITEONCE_INIT_RAM1B_BEGIN, M26CSS_WRITEONCE_INIT_RAM1B_WAIT, M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN, M26CSS_WRITEONCE_COUNT_CHIPS_WAIT, M26CSS_WRITEONCE_WRITE1_BEGIN, M26CSS_WRITEONCE_WRITE1_WAIT );
-signal m26cs_state, m26cs_state_next : M26CS_STATE_TYPE;
---signal write_count, write_count_next : std_logic_vector(31 downto 0);
-signal m26cs_stopped : std_logic;
-signal m26cs_firstrun, m26cs_firstrun_next : std_logic;
-signal breakpoint_active, breakpoint_active_next : std_logic_vector(9 downto 0);
--- chain_status:
--- bit 0: chain broken
--- bit 1: CRC_error(s)
--- bit 2: programmed
--- bits 3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3: chain length
-signal chain_status, chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
-
-signal trigger_begin_bypassreg, trigger_begin_bypassreg_next : std_logic;
-signal trigger_copy_ram3, trigger_copy_ram3_next : std_logic;
---signal jtag_tdo_compare_count_internal_error : std_logic;
-signal run_counter, run_counter_next : unsigned(31 downto 0);
-signal jtag_status2_copy_requested, jtag_status2_copy_requested_next : std_logic;
-
-signal jtag_status2_copy_request_strobe, jtag_status2_copy_request_strobe_next : std_logic;
-type CPS2_STATE_TYPE is (CPS2_IDLE, CPS2_COPY_BEGIN, CPS2_COPY_WAIT);
-signal cps2_state, cps2_state_next : CPS2_STATE_TYPE;
-signal jtag_clock_pulse1 : std_logic;
-signal jtag_clock_pulse2 : std_logic;
-signal jtag_tck : std_logic;
-
-signal jtag_pulses_reset, jtag_pulses_reset_next : std_logic;
-signal jtag_pulses_reset_complete : std_logic;
-
-signal jtag_chain_broken_counter, jtag_chain_broken_counter_next : unsigned(JTAG_CHAIN_BROKEN_COUNTER_BITS-1 downto 0);
-
-signal jtag_check_crc_ram1a_crc_ok : std_logic_vector(MAX_NUMCHIPS-1 downto 0);
-signal jtag_check_crc_ram1a_idle : std_logic;
-signal trigger_check_crc_ram1a, trigger_check_crc_ram1a_next : std_logic;
-signal trigger_init_ram1b, trigger_init_ram1b_next : std_logic;
-signal jtag_init_ram1b_idle : std_logic;
-
-signal ram1b1c_copy_trigger_strobe, ram1b1c_copy_trigger_strobe_next : std_logic_vector(3 downto 0);
-signal trigger_copy_ram1b1c, trigger_copy_ram1b1c_next : std_logic;
-signal copy_ram1b1c_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal copy_ram1b1c_ram1b_dout : std_logic_vector(31 downto 0);
-signal copy_ram1b1c_ram1c_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal copy_ram1b1c_ram1c_din : std_logic_vector(31 downto 0);
-signal copy_ram1b1c_ram1c_wr : std_logic;
-signal copy_ram1b1c_idle : std_logic;
-
-signal ram1c_a2, ram1c_a2_next : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
-signal ram1c_dout2 : std_logic_vector(31 downto 0);
-
-signal ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_active_next : std_logic_vector(3 downto 0);
-signal ram1b_copy_requested, ram1b_copy_requested_next : std_logic;
-signal ram1c_run_counter, ram1c_run_counter_next : unsigned(31 downto 0);
-signal ram1c_chain_status, ram1c_chain_status_next : std_logic_vector(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0);
-
-type CPR1BC_STATE_TYPE is (CPR1BC_IDLE, CPR1BC_COPY_BEGIN, CPR1BC_COPY_WAIT);
-signal cpr1bc_state, cpr1bc_state_next : CPR1BC_STATE_TYPE;
-
--- DEBUGTDO fifo and control signals
-signal tdodebugsamples : std_logic_vector(31 downto 0);
-signal debugtdo_rd_en : std_logic;
-signal debugtdo_wr_en : std_logic;
-signal debugtdo_dout : std_logic_vector(31 downto 0);
-signal debugtdo_empty : std_logic;
-signal debugtdo_full : std_logic;
-signal debugtdo_overflow : std_logic;
-signal debugtdo_underflow : std_logic;
-signal resetdebugtdo_toffifo : std_logic;
-signal resetdebugtdo_strobe : std_logic;
-signal debugtdo_activate_strobe : std_logic;
-signal debugtdo_active : std_logic;
-signal debugtdo_timeout, debugtdo_timeout_next : std_logic_vector(31 downto 0);
-signal debugtdo_counter : std_logic_vector(31 downto 0);
-signal debugtdo_ran : std_logic;
-
-signal crc_error_on_last_check, crc_error_on_last_check_next : std_logic;
-signal last_run_successful, last_run_successful_next : std_logic;
-signal last_run_successful_tmp, last_run_successful_tmp_next : std_logic;
-signal begin_count_read_errors :std_logic;
-signal begin_count_write_errors :std_logic;
-signal begin_count_data_changed :std_logic;
-signal end_count_read_errors :std_logic;
-signal end_count_write_errors :std_logic;
-signal end_count_data_changed :std_logic;
-signal last_read_error : std_logic;
-signal last_write_error : std_logic;
-signal last_data_changed : std_logic;
-
-signal sREAD_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
-signal sWRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
-signal sDATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
-
--- INSERTLABEL: signals
-
-signal m26csoptions, m26csoptions_next : std_logic_vector(0 downto 0);
-signal jtag_delay_expvalues, jtag_delay_expvalues_next : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
-
-signal request_reset, request_reset_next : std_logic;
-signal reset_wait, reset_wait_next : unsigned(7 downto 0);
-constant reset_wait_zero : unsigned(7 downto 0) := "00000000";
-
-signal run_requested, run_requested_next : std_logic;
-signal write_once_requested, write_once_requested_next : std_logic;
-signal write_once_count, write_once_count_next : unsigned(COUNTER_WIDTHS-1 downto 0);
-
-
-
-begin
-
---fifo32bit_debugtdo : fifo32bit
---port map(
--- clk => CLK_IN,
--- din => tdodebugsamples(31 downto 0),
--- rd_en => debugtdo_rd_en,
--- rst => resetdebugtdo_toffifo,
--- wr_en => debugtdo_wr_en,
--- dout => debugtdo_dout(31 downto 0),
--- empty => debugtdo_empty,
--- full => debugtdo_full,
--- overflow => debugtdo_overflow,
--- underflow => debugtdo_underflow);
-
-
-
-jtag_bypassreg_enable_jtag_clock <= '0';
-
-
-resetdebugtdo_toffifo <= resetdebugtdo_strobe OR RESET_IN;
-debugtdo_wr_en <= '1' when debugtdo_active = '1' and debugtdo_timeout <= debugtdo_counter else '0';
-
-tdodebugsamples(31) <= begin_jtag_bitcalc;
-tdodebugsamples(30) <= jtag_clock_pulse1;
-tdodebugsamples(29) <= jtag_clock_pulse2;
-tdodebugsamples(28) <= jtag_sample_pulse1;
-tdodebugsamples(27) <= jtag_sample_pulse2;
-tdodebugsamples(26) <= jtag_sample_pulse3;
-tdodebugsamples(25) <= jtag_set_data_pulse;
-tdodebugsamples(1) <= JTAG_TDO_IN;
-
-RUN_COUNTER_OUT <= std_logic_vector(run_counter);
-STARTED_OUT <= jtag_refresh_active;
-CRC_ERROR_OUT <= crc_error_on_last_check;
-LAST_RUN_SUCCESSFUL_OUT <= last_run_successful;
-LAST_DATA_CHANGED_OUT <= last_data_changed;
-LAST_WRITE_ERRORS_OUT <= last_write_error;
-LAST_READ_ERRORS_OUT <= last_read_error;
-
-REQUEST_RESET_OUT <= request_reset;
-
-the_bus_handler : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 5,
- PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", others => (others => '0')),
- PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, others => 0)
- )
- port map(
- CLK => CLK_IN,
- RESET => RESET_IN,
- DAT_ADDR_IN(15 downto 9) => "0000000",
- DAT_ADDR_IN(8 downto 0)=> BUS_ADDR_IN, -- address bus
- DAT_DATA_IN => BUS_DATA_IN, -- data from TRB endpoint
- DAT_DATA_OUT => BUS_DATA_OUT, -- data to TRB endpoint
- DAT_READ_ENABLE_IN => BUS_READ_IN, -- read pulse
- DAT_WRITE_ENABLE_IN => BUS_WRITE_IN, -- write pulse
- DAT_TIMEOUT_IN => '0', -- access timed out
- DAT_DATAREADY_OUT => BUS_DATAREADY_OUT, -- your data, master, as requested
- DAT_WRITE_ACK_OUT => BUS_WRITE_ACK_OUT, -- data accepted
- DAT_NO_MORE_DATA_OUT => BUS_NO_MORE_DATA_OUT, -- don't disturb me now
- DAT_UNKNOWN_ADDR_OUT => BUS_UNKNOWN_ADDR_OUT, -- noone here to answer your request
-
- --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
- BUS_ADDR_OUT(0*16+15 downto 0*16) => bus2_ram_addr_out,
- --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
- BUS_ADDR_OUT(1*16+15 downto 1*16) => bus2_status_addr_out,
- --BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => bus2_control_addr_out,
- --BUS_ADDR_OUT(3*16+15 downto 3*16+5) => open,
- BUS_ADDR_OUT(3*16+15 downto 3*16) => bus2_debug_addr_out,
- BUS_ADDR_OUT(4*16+15 downto 4*16) => bus2_status2_addr_out,
- BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out,
- BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_status_data_out,
- BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_control_data_out,
- BUS_DATA_OUT(3*32+31 downto 3*32) => bus2_debug_data_out,
- BUS_DATA_OUT(4*32+31 downto 4*32) => bus2_status2_data_out,
- BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out,
- BUS_READ_ENABLE_OUT(1) => bus2_status_read_enable_out,
- BUS_READ_ENABLE_OUT(2) => bus2_control_read_enable_out,
- BUS_READ_ENABLE_OUT(3) => bus2_debug_read_enable_out,
- BUS_READ_ENABLE_OUT(4) => bus2_status2_read_enable_out,
- BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out,
- BUS_WRITE_ENABLE_OUT(1) => bus2_status_write_enable_out,
- BUS_WRITE_ENABLE_OUT(2) => bus2_control_write_enable_out,
- BUS_WRITE_ENABLE_OUT(3) => bus2_debug_write_enable_out,
- BUS_WRITE_ENABLE_OUT(4) => bus2_status2_write_enable_out,
- BUS_TIMEOUT_OUT(0) => bus2_ram_timeout_out,
- BUS_TIMEOUT_OUT(1) => bus2_status_timeout_out,
- BUS_TIMEOUT_OUT(2) => bus2_control_timeout_out,
- BUS_TIMEOUT_OUT(3) => bus2_debug_timeout_out,
- BUS_TIMEOUT_OUT(4) => bus2_status2_timeout_out,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in,
- BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => bus2_control_data_in,
- BUS_DATA_IN(3*32+31 downto 3*32) => bus2_debug_data_in,
- BUS_DATA_IN(4*32+31 downto 4*32) => bus2_status2_data_in,
- BUS_DATAREADY_IN(0) => bus2_ram_dataready_in,
- BUS_DATAREADY_IN(1) => bus2_status_dataready_in,
- BUS_DATAREADY_IN(2) => bus2_control_dataready_in,
- BUS_DATAREADY_IN(3) => bus2_debug_dataready_in,
- BUS_DATAREADY_IN(4) => bus2_status2_dataready_in,
- BUS_WRITE_ACK_IN(0) => bus2_ram_write_ack_in,
- BUS_WRITE_ACK_IN(1) => bus2_status_write_ack_in,
- BUS_WRITE_ACK_IN(2) => bus2_control_write_ack_in,
- BUS_WRITE_ACK_IN(3) => bus2_debug_write_ack_in,
- BUS_WRITE_ACK_IN(4) => bus2_status2_write_ack_in,
- BUS_NO_MORE_DATA_IN(0) => bus2_ram_no_more_data_in,
- BUS_NO_MORE_DATA_IN(1) => bus2_status_no_more_data_in,
- BUS_NO_MORE_DATA_IN(2) => bus2_control_no_more_data_in,
- BUS_NO_MORE_DATA_IN(3) => bus2_debug_no_more_data_in,
- BUS_NO_MORE_DATA_IN(4) => bus2_status2_no_more_data_in,
- BUS_UNKNOWN_ADDR_IN(0) => bus2_ram_unknown_addr_in,
- BUS_UNKNOWN_ADDR_IN(1) => bus2_status_unknown_addr_in,
- BUS_UNKNOWN_ADDR_IN(2) => bus2_control_unknown_addr_in,
- BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_unknown_addr_in,
- BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_unknown_addr_in,
-
-
-
-
-
-
- STAT_DEBUG => open
- );
-
-
-
--- RAM1a holds JTAG registers, written via trbnet
-ram_jtag_registers : ram_dp generic map(
- depth => RAM_JTAG_REGISTERS_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => ram1a_wr1,
- a1 => ram1a_a1,
- dout1 => ram1a_dout1,
- din1 => ram1a_din1,
- a2 => ram1a_a2,
- dout2 => ram1a_dout2
- );
-ram1a_readport_mux: ram_mux4to1_readport generic map(
- depth => RAM_JTAG_REGISTERS_DEPTH,
- width => 32
- )
- port map (
- SELECT_IN => ram1a_select,
- A0_IN => jtag_read_ram1a_a,
- D0_OUT => jtag_read_ram1a_d,
- A1_IN => jtag_write_ram1a_a,
- D1_OUT => jtag_write_ram1a_d,
- A2_IN => init_ram1b_ram1a_a,
- D2_OUT => init_ram1b_ram1a_d,
- A3_IN => jtag_check_crc_ram1a_a,
- D3_OUT => jtag_check_crc_ram1a_d,
-
- RAM_A_OUT => ram1a_a2,
- RAM_DOUT_IN => ram1a_dout2
- );
-
--- RAM1b holds JTAG registers, read from JTAG chain
-ram_jtag_registers_read : ram_dp generic map(
- depth => RAM_JTAG_REGISTERS_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => ram1b_wr1,
- a1 => ram1b_a1,
- dout1 => ram1b_dout1,
- din1 => ram1b_din1,
- a2 => copy_ram1b1c_ram1b_a,--ram1b_a2,
- dout2 => copy_ram1b1c_ram1b_dout--ram1b_dout2
- );
-
--- RAM1b holds JTAG registers, read from JTAG chain
-ram_jtag_registers_copy_read : ram_dp generic map(
- depth => RAM_JTAG_REGISTERS_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => copy_ram1b1c_ram1c_wr,
- a1 => copy_ram1b1c_ram1c_a,
- dout1 => open,
- din1 => copy_ram1b1c_ram1c_din,
- a2 => ram1c_a2,
- dout2 => ram1c_dout2
- );
-
-
-ram1b_mux2to1_writeport : ram_mux2to1_writeport generic map (
- depth => RAM_JTAG_REGISTERS_DEPTH,
- width => 32
- )
- port map ( SELECT_IN => ram1b_select,
- A0_IN => init_ram1b_ram1b_a,
- D0_OUT => init_ram1b_ram1b_dout,
- WR0_IN => init_ram1b_ram1b_wr,
- DIN0_IN => init_ram1b_ram1b_din,
-
- A1_IN => jtag_data_to_ram_ram1b_a,
- D1_OUT => jtag_data_to_ram_ram1b_dout,
- WR1_IN => jtag_data_to_ram_ram1b_wr,
- DIN1_IN => jtag_data_to_ram_ram1b_din,
-
- RAM_A_OUT => ram1b_a1,
- RAM_DOUT_IN => ram1b_dout1,
- RAM_WR_OUT => ram1b_wr1,
- RAM_DIN_OUT => ram1b_din1
- );
-
-
--- RAM2 holds counts of matching/not matching bits of each register of each chip
-ram_match_diff_count : ram_dp generic map(
- depth => RAM_MATCH_DIFF_COUNT_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => ram2_wr1,
- a1 => ram2_a1,
- dout1 => ram2_dout1,
- din1 => ram2_din1,
- a2 => "00000000",--ram2_a2,
- dout2 => open --ram2_dout2
- );
-ram2_mux2to1_writeport : ram_mux2to1_writeport generic map (
- depth => RAM_MATCH_DIFF_COUNT_DEPTH,
- width => 32
- )
- port map ( SELECT_IN => ram2_select,
- A0_IN => jtag_tdo_compare_count_ram_a,
- D0_OUT => jtag_tdo_compare_count_ram_dout,
- WR0_IN => jtag_tdo_compare_count_ram_wr,
- DIN0_IN => jtag_tdo_compare_count_ram_din,
-
- A1_IN => juec_ram2_a,
- D1_OUT => juec_ram2_dout,
- WR1_IN => '0',
- DIN1_IN => x"0000_0000",
-
- RAM_A_OUT => ram2_a1,
- RAM_DOUT_IN => ram2_dout1,
- RAM_WR_OUT => ram2_wr1,
- RAM_DIN_OUT => ram2_din1
- );
-
--- RAM3 holds counts of errors and 'error over threshold's of each register of each chip
-ram_error_counts_A : ram_dp generic map(
- depth => RAM_ERROR_COUNTS_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => ram3a_wr1,
- a1 => ram3a_a1,
- dout1 => ram3a_dout1,
- din1 => ram3a_din1,
- a2 => ram3a_a2,
- dout2 => ram3a_dout2
- );
--- ram_error_counts_A : ram_dp generic map(
--- depth => RAM_ERROR_COUNTS_DEPTH,
--- width => 32
--- )
--- port map ( CLK => CLK_IN,
--- wr1 => juec_ram3a_wr,
--- a1 => juec_ram3a_a,
--- dout1 => juec_ram3a_dout,
--- din1 => juec_ram3a_din,
--- a2 => jtag_copy_ram3_ram3a_a,
--- dout2 => jtag_copy_ram3_ram3a_dout
--- );
--- RAM3B is an on demand copy of RAM3A
-ram_error_counts_B : ram_dp generic map(
- depth => RAM_ERROR_COUNTS_DEPTH,
- width => 32
- )
- port map ( CLK => CLK_IN,
- wr1 => jtag_copy_ram3_ram3b_wr,
- a1 => jtag_copy_ram3_ram3b_a,
- dout1 => open,
- din1 => jtag_copy_ram3_ram3b_din,
- a2 => ram3b_a2,
- dout2 => ram3b_dout2
- );
-
-ram3a_mux2to1_writeport : ram_mux2to1_writeport generic map (
- depth => RAM_ERROR_COUNTS_DEPTH,
- width => 32
- )
- port map ( SELECT_IN => ram3a_select,
- A0_IN => juec_ram3a_a,
- D0_OUT => juec_ram3a_dout,
- WR0_IN => juec_ram3a_wr,
- DIN0_IN => juec_ram3a_din,
-
- A1_IN => jtag_blank_ram3a_ram3a_a,
- D1_OUT => open,
- WR1_IN => jtag_blank_ram3a_ram3a_wr,
- DIN1_IN => jtag_blank_ram3a_ram3a_din,
-
- RAM_A_OUT => ram3a_a1,
- RAM_DOUT_IN => ram3a_dout1,
- RAM_WR_OUT => ram3a_wr1,
- RAM_DIN_OUT => ram3a_din1
- );
-
-ram3a_readport_mux: ram_mux2to1_readport generic map(
- depth => RAM_ERROR_COUNTS_DEPTH,
- width => 32
- )
- port map (
- SELECT_IN => ram3a_rd_select,
- A0_IN => jtag_copy_ram3_ram3a_a,
- D0_OUT => jtag_copy_ram3_ram3a_dout,
- A1_IN => "000000000",
- D1_OUT => open,
-
- RAM_A_OUT => ram3a_a2,
- RAM_DOUT_IN => ram3a_dout2
- );
-
-
-
-the_jtag_init_ram1b: jtag_init_ram1b generic map(
- RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_REGISTERS_LD => MAX_REGISTERS_LD
-)
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_INIT_IN => trigger_init_ram1b,
- -- RAM1a
- RAM1A_A_OUT => init_ram1b_ram1a_a,
- RAM1A_D_IN => init_ram1b_ram1a_d,
- -- RAM1b
- RAM1B_A_OUT => init_ram1b_ram1b_a,
- RAM1B_D_IN => init_ram1b_ram1b_dout,
- RAM1B_WE_OUT => init_ram1b_ram1b_wr,
- RAM1B_D_OUT => init_ram1b_ram1b_din,
-
- IDLE_OUT => jtag_init_ram1b_idle
- );
-
-the_jtag_copy_ram1b1c : copy_ram
- generic map (
- ram_depth => RAM_JTAG_REGISTERS_DEPTH,
- ram_width => 32
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_COPY_IN => trigger_copy_ram1b1c,
- -- RAM3a
- RAMA_A_OUT => copy_ram1b1c_ram1b_a,
- RAMA_D_IN => copy_ram1b1c_ram1b_dout,
- -- RAM3b
- RAMB_A_OUT => copy_ram1b1c_ram1c_a,
- RAMB_D_OUT => copy_ram1b1c_ram1c_din,
- RAMB_WR_OUT => copy_ram1b1c_ram1c_wr,
-
- IDLE_OUT => copy_ram1b1c_idle
- );
-
-
-
-the_jtag_copy_ram3 : copy_ram
- generic map (
- ram_depth => RAM_ERROR_COUNTS_DEPTH,
- ram_width => 32
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_COPY_IN => trigger_copy_ram3,
- -- RAM3a
- RAMA_A_OUT => jtag_copy_ram3_ram3a_a,
- RAMA_D_IN => jtag_copy_ram3_ram3a_dout,
- -- RAM3b
- RAMB_A_OUT => jtag_copy_ram3_ram3b_a,
- RAMB_D_OUT => jtag_copy_ram3_ram3b_din,
- RAMB_WR_OUT => jtag_copy_ram3_ram3b_wr,
-
- IDLE_OUT => jtag_copy_ram3_idle
- );
-
-the_jtag_blank_ram3a : blank_ram
- generic map (
- ram_depth => RAM_ERROR_COUNTS_DEPTH,
- ram_width => 32
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_BLANK_IN => trigger_blank_ram3a,
- -- RAM
--- RAM_A_OUT => jtag_blank_ram3a_ram3a_a,
- RAM_A_OUT => open,
--- RAM_D_OUT => jtag_blank_ram3a_ram3a_din,
- RAM_D_OUT => open,
--- RAM_WR_OUT => jtag_blank_ram3a_ram3a_wr, -- disabling blanking ram 29.10.2012
- RAM_WR_OUT => open,
-
- IDLE_OUT => jtag_blank_ram3a_idle
- );
-jtag_blank_ram3a_ram3a_a <= (others => '0');
-jtag_blank_ram3a_ram3a_din <= (others => '0');
-jtag_blank_ram3a_ram3a_wr <= '0';
-
-
-the_jtag_update_error_counts_ram3a : jtag_update_error_counts_ram3a
- generic map (
- MAX_NUMCHIPS => MAX_NUMCHIPS,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
- MAX_REGISTERS_LD => MAX_REGISTERS_LD,
- MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
- MAX_REGISTERS_PLUS_TWO_LD => MAX_REGISTERS_PLUS_TWO_LD,
- RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
- RAM_ERROR_COUNTS_DEPTH => RAM_ERROR_COUNTS_DEPTH,
- WRITE_ERROR_THRESHOLD => WRITE_ERROR_THRESHOLD,
- READ_ERROR_THRESHOLD => READ_ERROR_THRESHOLD
- )
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_UPDATE_DATA_CHANGED_IN => trigger_juec_update_d_ch,
- TRIGGER_UPDATE_READ_ERRORS_IN => trigger_juec_update_rd_err,
- TRIGGER_UPDATE_WRITE_ERRORS_IN => trigger_juec_update_wr_err,
- TRIGGER_UPDATE_RUN_COUNTER_IN => trigger_juec_update_run_counter,
- RUN_COUNTER_IN => std_logic_vector(run_counter),
- -- RAM2
- RAM2_A_OUT => juec_ram2_a,
- RAM2_D_IN => juec_ram2_dout,
- -- RAM3a
- RAM3A_A_OUT => juec_ram3a_a,
- RAM3A_D_IN => juec_ram3a_dout,
- RAM3A_D_OUT => juec_ram3a_din,
- RAM3A_WR_OUT => juec_ram3a_wr,
-
- REMOVED_CHIPS_IN => removed_chips,
- NUMCHIPS_CONFIGURED_IN => std_logic_vector(numchips_configured),
- NUMREGS_CONFIGURED_IN => jtag_write_numregs_configured,
-
- DATA_CHANGED_OUT => juec_data_changed,
- READ_ERRORS_OUT => juec_read_errors,
- WRITE_ERRORS_OUT => juec_write_errors,
-
- IDLE_OUT => juec_idle
- );
-
--- the_jtag_bypassreg_testchain_m10: jtag_bypassreg_testchain_m10
--- generic map (
--- ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
--- MAX_NUMCHIPS => MAX_NUMCHIPS,
--- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
--- JTAG_M26_IRLEN => JTAG_M26_IRLEN,
--- max_bitcounter_ld => MAX_NUMCHIPS_LD+JTAG_M26_IRLEN_LD + 7
--- )
--- port map(
--- CLK_IN => CLK_IN,
--- RESET_IN => RESET_IN,
--- BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
--- TRIGGER_BEGIN_TESTCHAIN_IN => trigger_begin_bypassreg,
--- IDLE_OUT => jtag_bypassreg_idle,
--- CHAIN_LENGTH_OUT => jtag_bypassreg_length,
--- CHAIN_BROKEN_OUT => jtag_bypassreg_chain_broken,
--- ENABLE_JTAG_CLOCK_OUT => jtag_bypassreg_enable_jtag_clock,
--- LAST_TCK_CYCLE_OUT => jtag_bypassreg_last_tck_cycle,
--- TMS_OUT => jtag_bypassreg_tms,
--- TDI_OUT => jtag_bypassreg_tdi,
--- TDO_IN => jtag_tdo_sampled,
--- DELAY_IN => jtag_delay_expvalues
--- );
-
-the_jtag_read_m26devid_m10: jtag_read_m26devid_m10
- generic map (
- RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
- MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
- MAX_NUMCHIPS => MAX_NUMCHIPS,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD
- )
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- RAM_JTAG_REGISTERS_A_OUT => jtag_read_ram1a_a,
- RAM_JTAG_REGISTERS_D_IN => jtag_read_ram1a_d,
- NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
- BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
- TRIGGER_BEGIN_READ_IN => trigger_jtag_read,
- IS_DR_BIT_OUT => jtag_read_is_dr_bit,
- IS_FIRSTBIT_OUT => jtag_read_is_firstbit,
- IS_LASTBIT_OUT => jtag_read_is_lastbit,
- CHIPNUM_OUT => jtag_read_chipnum,
- ENABLE_JTAG_CLOCK_OUT => jtag_read_enable_jtag_clock,
- LAST_TCK_CYCLE_OUT => jtag_read_last_tck_cycle,
- TMS_OUT => jtag_read_tms,
- TDI_OUT => jtag_read_tdi,
- EXPECTED_TDO_OUT => jtag_read_expected_tdo,
- IDLE_OUT => jtag_read_idle
- );
-
-the_jtag_tdo_data_to_ram_m10 : jtag_tdo_data_to_ram_m10
- generic map (
- enable_ram1b => '1',
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
- MAX_REGLEN_LD => MAX_REGLEN_LD,
- RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH
- )
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
- CHIPNUM_IN => jtag_delayed_chipnum,
- REGNUM_IN => jtag_delayed_regnum,
- ENABLE_DATAOUT_IN => jtag_delayed_is_dr_bit,
- IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
- IS_LASTBIT_IN => jtag_delayed_is_lastbit,
- TDO_SAMPLED_IN => jtag_tdo_sampled,
- -- RAM1b
- RAM_JTAG_REGISTERS_READOUT_A_OUT => jtag_data_to_ram_ram1b_a,
- RAM_JTAG_REGISTERS_READOUT_D_IN => jtag_data_to_ram_ram1b_dout,
- RAM_JTAG_REGISTERS_READOUT_WE_OUT => jtag_data_to_ram_ram1b_wr,
- RAM_JTAG_REGISTERS_READOUT_D_OUT => jtag_data_to_ram_ram1b_din
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- );
-
-the_jtag_tdo_compare_count_m10 : jtag_tdo_compare_count_m10
- generic map (
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
- RAM_MATCH_DIFF_COUNT_DEPTH => RAM_MATCH_DIFF_COUNT_DEPTH,
- MAX_REGLEN_LD => MAX_REGLEN_LD
- )
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
- CHIPNUM_IN => jtag_delayed_chipnum,
- REGNUM_IN => jtag_delayed_regnum,
- ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
- IS_FIRSTBIT_IN => jtag_delayed_is_firstbit,
- IS_LASTBIT_IN => jtag_delayed_is_lastbit,
- TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
- TDO_SAMPLED_IN => jtag_tdo_sampled,
- TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
- RAM_MATCH_DIFF_COUNT_A_OUT => jtag_tdo_compare_count_ram_a,
- RAM_MATCH_DIFF_COUNT_WE_OUT => jtag_tdo_compare_count_ram_wr,
- RAM_MATCH_DIFF_COUNT_D_OUT => jtag_tdo_compare_count_ram_din
- --INTERNAL_ERROR_OUT => jtag_tdo_compare_count_internal_error
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- );
-
-
-the_jtag_tdo_compare_counttotal_noram_m10 : jtag_tdo_compare_counttotal_noram_m10
- generic map (
- numcounts => 3,
- se_counter_width => COUNTER_WIDTHS, -- sampling error counter width
- diff_counter_width => COUNTER_WIDTHS -- counter width for number of runs in which there were differences
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SAMPLE_PULSE3_D1_IN => jtag_sample_pulse3_d1,
- ENABLE_COUNTERS_IN => jtag_delayed_is_dr_bit,
- TDO_EXPECTED_IN => jtag_delayed_tdo_expected,
- TDO_SAMPLED_IN => jtag_tdo_sampled,
- TDO_SAMPLING_ERROR_IN => jtag_tdo_sampling_error,
- BEGIN_COUNT_I_IN(2) => begin_count_read_errors,
- BEGIN_COUNT_I_IN(1) => begin_count_write_errors,
- BEGIN_COUNT_I_IN(0) => begin_count_data_changed,
-
- END_COUNT_I_IN(2) => end_count_read_errors,
- END_COUNT_I_IN(1) => end_count_write_errors,
- END_COUNT_I_IN(0) => end_count_data_changed,
-
- SAMPLING_ERRORS_COUNT_OUT => SAMPLING_ERRORS_COUNT_OUT,
- COUNTS_OUT(0*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 0*COUNTER_WIDTHS) => sDATA_CHANGED_COUNT_OUT,
- COUNTS_OUT(1*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 1*COUNTER_WIDTHS) => sWRITE_ERRORS_COUNT_OUT,
- COUNTS_OUT(2*COUNTER_WIDTHS+COUNTER_WIDTHS-1 downto 2*COUNTER_WIDTHS) => sREAD_ID_ERRORS_COUNT_OUT,
- LAST_VALUES_OUT(2) => last_read_error,
- LAST_VALUES_OUT(1) => last_write_error,
- LAST_VALUES_OUT(0) => last_data_changed
- );
-
-the_jtag_delay_expected_values: jtag_delay_expected_values
- generic map (
- ld_maxdelay => JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD
- )
- port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SAMPLE_PULSE1_IN => jtag_sample_pulse1,
- CHIPNUM_IN => jtag_meta_chipnum,
- REGNUM_IN => jtag_meta_regnum,
- IS_DR_BIT_IN => jtag_meta_is_dr_bit,
- IS_FIRSTBIT_IN => jtag_meta_is_firstbit,
- IS_LASTBIT_IN => jtag_meta_is_lastbit,
- TDO_EXPECTED_IN => jtag_meta_expected_tdo,
- OUT_CHIPNUM_OUT => jtag_delayed_chipnum,
- OUT_REGNUM_OUT => jtag_delayed_regnum,
- OUT_IS_DR_BIT_OUT => jtag_delayed_is_dr_bit,
- OUT_IS_FIRSTBIT_OUT => jtag_delayed_is_firstbit,
- OUT_IS_LASTBIT_OUT => jtag_delayed_is_lastbit,
- OUT_TDO_EXPECTED_OUT => jtag_delayed_tdo_expected,
- DELAY_IN => jtag_delay_expvalues
-);
-
-the_jtag_mux_buffer_tms_tdi_out_and_metainfo : jtag_mux_buffer_tms_tdi_out_and_metainfo
- generic map (
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_REGISTERS_LD => MAX_REGISTERS_LD
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- JTAG_SET_DATA_IN => jtag_set_data_pulse,
- -- read DEV_ID inputs
- RD_TMS_IN => jtag_read_tms,
- RD_TDI_IN => jtag_read_tdi,
- RD_IS_DR_BIT_IN => jtag_read_is_dr_bit,
- RD_IS_FIRSTBIT_IN => jtag_read_is_firstbit,
- RD_IS_LASTBIT_IN => jtag_read_is_lastbit,
- RD_CHIPNUM_IN => jtag_read_chipnum,
- RD_ENABLE_JTAG_CLOCK_IN => jtag_read_enable_jtag_clock,
- RD_LAST_TCK_CYCLE_IN => jtag_read_last_tck_cycle,
- RD_EXPECTED_TDO_OUT => jtag_read_expected_tdo,
- -- write registers inputs
- WR_TMS_IN => jtag_write_tms,
- WR_TDI_IN => jtag_write_tdi,
- WR_IS_DR_BIT_IN => jtag_write_is_dr_bit,
- WR_IS_FIRSTBIT_IN => jtag_write_is_firstbit,
- WR_IS_LASTBIT_IN => jtag_write_is_lastbit,
- WR_CHIPNUM_IN => jtag_write_chipnum,
- WR_REGNUM_IN => jtag_write_regnum,
- WR_ENABLE_JTAG_CLOCK_IN => jtag_write_enable_jtag_clock,
- WR_LAST_TCK_CYCLE_IN => jtag_write_last_tck_cycle,
- WR_EXPECTED_TDO_OUT => jtag_write_expected_tdo,
- -- test chain inputs
- TC_TMS_IN => jtag_bypassreg_tms,
- TC_TDI_IN => jtag_bypassreg_tdi,
- TC_ENABLE_JTAG_CLOCK_IN => jtag_bypassreg_enable_jtag_clock,
- TC_LAST_TCK_CYCLE_IN => jtag_bypassreg_last_tck_cycle,
-
- TMS_OUT => jtag_tms,
- TDI_OUT => jtag_tdi,
- IS_DR_BIT_OUT => jtag_meta_is_dr_bit,
- IS_FIRSTBIT_OUT => jtag_meta_is_firstbit,
- IS_LASTBIT_OUT => jtag_meta_is_lastbit,
- CHIPNUM_OUT => jtag_meta_chipnum,
- REGNUM_OUT => jtag_meta_regnum,
- ENABLE_JTAG_CLOCK_OUT => jtag_enable_clock,
- LAST_TCK_CYCLE_OUT => jtag_meta_last_tck_cycle,
- EXPECTED_TDO_OUT => jtag_meta_expected_tdo
- );
-
-the_jtag_tdo_sampler : jtag_tdo_sample port map(
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SAMPLE_PULSE1_IN => jtag_sample_pulse1,
- SAMPLE_PULSE2_IN => jtag_sample_pulse2,
- SAMPLE_PULSE3_IN => jtag_sample_pulse3,
- -- TDO signal, which is to be sampled
- TDO_IN => JTAG_TDO_IN,
- -- sampled value of TDO
- TDO_SAMPLED_OUT => jtag_tdo_sampled,
- -- sampling error
- SAMPLING_ERROR_OUT => jtag_tdo_sampling_error
- );
-
-the_jtag_write_m10: jtag_write_m10 generic map (
- RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
- MAX_NUMCHIPS => MAX_NUMCHIPS,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
- MAX_REGISTERS_LD => MAX_REGISTERS_LD,
- MAX_REGISTERS_PLUS_ONE_LD => MAX_REGISTERS_PLUS_ONE_LD,
- MAX_REGLEN_LD => MAX_REGLEN_LD,
- MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- RAM_JTAG_REGISTERS_A_OUT => jtag_write_ram1a_a,
- RAM_JTAG_REGISTERS_D_IN => jtag_write_ram1a_d,
- NEXT_NOT_REMOVED_IN => jtag_next_not_removed,
- BEGIN_JTAGBITCALC_IN => begin_jtag_bitcalc,
- TRIGGER_BEGIN_WRITE_IN => trigger_jtag_write,
- IS_DR_BIT_OUT => jtag_write_is_dr_bit,
- IS_FIRSTBIT_OUT => jtag_write_is_firstbit,
- IS_LASTBIT_OUT => jtag_write_is_lastbit,
- CHIPNUM_OUT => jtag_write_chipnum,
- REGNUM_OUT => jtag_write_regnum,
- ENABLE_JTAG_CLOCK_OUT => jtag_write_enable_jtag_clock,
- LAST_TCK_CYCLE_OUT => jtag_write_last_tck_cycle,
- TMS_OUT => jtag_write_tms,
- TDI_OUT => jtag_write_tdi,
- EXPECTED_TDO_OUT => jtag_write_expected_tdo,
- IDLE_OUT => jtag_write_idle,
- NUMREGS_CONFIGURED_OUT => jtag_write_numregs_configured,
- LAST_ERROR_CODE_OUT => jtag_write_last_error_code
- );
-
-the_jtag_tck_out: jtag_tck_out_component port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
-
- JTAG_CLOCK_PULSE1_IN => jtag_clock_pulse1,
- JTAG_CLOCK_PULSE2_IN => jtag_clock_pulse2,
- ENABLE_JTAG_TCK_IN => jtag_enable_clock,
-
- TCK_OUT => jtag_tck
- );
-
-the_jtag_pulses : jtag_pulses generic map (
- time_bits => 10
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => jtag_pulses_reset_complete,
- -- input times
- JTAG_CLOCK_TIME1_IN => std_logic_vector(jtag_clock_time1),
- JTAG_CLOCK_TIME2_IN => std_logic_vector(jtag_clock_time2),
- JTAG_SAMPLE_TIME1_IN => std_logic_vector(jtag_sample_time1),
- JTAG_SAMPLE_TIME2_IN => std_logic_vector(jtag_sample_time2),
- JTAG_SAMPLE_TIME3_IN => std_logic_vector(jtag_sample_time3),
- JTAG_SET_DATA_TIME_IN => std_logic_vector(jtag_set_data_time),
-
- JTAG_CLOCK_CYCLE_LENGTH_IN => std_logic_vector(jtag_clock_cycle_length),
-
- -- output pulses
- BEGIN_JTAGBITCALC_OUT => begin_jtag_bitcalc,
- JTAG_CLOCK_PULSE1_OUT => jtag_clock_pulse1,
- JTAG_CLOCK_PULSE2_OUT => jtag_clock_pulse2,
- JTAG_SAMPLE_PULSE1_OUT => jtag_sample_pulse1,
- JTAG_SAMPLE_PULSE2_OUT => jtag_sample_pulse2,
- JTAG_SAMPLE_PULSE3_OUT => jtag_sample_pulse3,
- JTAG_SET_DATA_PULSE_OUT => jtag_set_data_pulse
- );
-
-the_jtag_check_crc_ram1a: jtag_check_crc_ram1a
- generic map (
- RAM_JTAG_REGISTERS_DEPTH => RAM_JTAG_REGISTERS_DEPTH,
- MAX_NUMCHIPS => MAX_NUMCHIPS,
- MAX_NUMCHIPS_LD => MAX_NUMCHIPS_LD,
- MAX_NUMCHIPS_PLUS_ONE_LD => MAX_NUMCHIPS_PLUS_ONE_LD,
- MAX_REGLEN_PLUS_ONE_LD => MAX_REGLEN_PLUS_ONE_LD,
- MAX_REGISTERS_LD => MAX_REGISTERS_LD
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_CHECK_IN => trigger_check_crc_ram1a,
- -- RAM1a
- RAM1A_A_OUT => jtag_check_crc_ram1a_a,
- RAM1A_D_IN => jtag_check_crc_ram1a_d,
- NUMCHIPS_IN => std_logic_vector(numchips_configured),
- CRC_OK_OUT => jtag_check_crc_ram1a_crc_ok,
- IDLE_OUT => jtag_check_crc_ram1a_idle
- );
-
-
---BUS_DATA_OUT <= bus_data_out_buffer;
---BUS_DATAREADY_OUT <= bus_dataready;
---BUS_NO_MORE_DATA_OUT <= bus_no_more_data;
---BUS_WRITE_ACK_OUT <= bus_write_ack;
---BUS_UNKNOWN_ADDR_OUT <= bus_unknown_addr;
-MY_STATUS_OUT <= (others => '0'); --my_status;
-JTAG_TCK_OUT <= jtag_tck;
-JTAG_TMS_OUT <= jtag_tms;
-JTAG_TDI_OUT <= jtag_tdi;
-PROG_JTAG_FINISHED_OUT <= prog_jtag_finished;
-READ_ID_ERRORS_COUNT_OUT <= sREAD_ID_ERRORS_COUNT_OUT;
-WRITE_ERRORS_COUNT_OUT <= sWRITE_ERRORS_COUNT_OUT;
-DATA_CHANGED_COUNT_OUT <= sDATA_CHANGED_COUNT_OUT;
-
-
-jtag_pulses_reset_complete <= jtag_pulses_reset or RESET_IN;
-
-m26cs_stopped <= '1' when m26cs_state = M26CSS_STOPPED else '0';
-
-jtag_sample_pulse3_d1_next <= jtag_sample_pulse3;
-
-ram3b_a2 <= ram3b_a2_base_addr & ram3b_a2_rel_addr; -- hope this is the right order (base_addr should be the MSBs)
-
-SEQUENTIAL : process (CLK_IN)
-begin
- if (rising_edge(CLK_IN)) then
- if(RESET_IN = '1') then
- --bus_rw_state <= BUS_RW_STATE_IDLE;
- --status_register <= (others => '0');
- --status_register_read_error2 <= '0';
- data_register <= x"00000000";
- --cmd_register <= x"00000000";
- --bus_data_out_buffer <= x"00000000";
- --bus_dataready <= '0';
- --bus_no_more_data <= '0';
- --bus_write_ack <= '0';
- --bus_unknown_addr <= '0';
- --length_register <= x"00000001";
- jtag_refresh_active <= '0';
- jtag_check1_active <= '0';
- jtag_refresh_active_last <= '0';
- --trigger_counter <= (others => '0');
- idle_out_signal <= '0';
- --status_register_pos <= (others => '0');
- --status_register_read_running <= '0';
- --ram_base_addr <= (others => '0');
- crc_status_register <= (others => '0');
- --write_trigger <= '0';
- --write_idle_last <= '0';
- --write_status_register_or <= (others => '0');
- removed_chips <= (others => '0');
- --reactivate_sensor <= (others => '0');
- --reactivate_sensor_strobe <= (others => '0');
- --deactivate_sensor <= (others => '0');
- --deactivate_sensor_strobe <= (others => '0');
- --disable_write <= '0';
- --disable_writeerror_for_remove <= '0';
- --disable_remove <= '0';
- --debug_one_remove <= '0';
- --debug_one_remove_strobe <= '0';
- --removed_strobe <= '0';
- --read_trigger <= '0';
- numchips_configured <= (others => '0');
- --my_status <= (others => '0');
- --m26c_sensor_cand <= (others => '0');
- chip_counter_start <= '0';
- --m26c_firstrun <= '0';
- --m26c_secondrun <= '0';
- --mux_sel <= '0';
- --driver_speed <= x"0005";
- --already_written <= '0';
- --read_idle_last <= '0';
- --write_error_counter <= (others => (others => '0'));
- --write_error_over_threshold_counter <= (others => (others => '0'));
- --write_data_changed_counter <= (others => (others => '0'));
- --read_error_counter <= (others => (others => '0'));
- --read_error_over_threshold_counter <= (others => (others => '0'));
- debug_test <= (others =>'0');
- debug_m26cs_state <= (others => '0');
- bus2_ram_data_in <= (others => '0');
- bus2_ram_dataready_in <= '0';
- bus2_ram_write_ack_in <= '0';
- bus2_ram_no_more_data_in <= '0';
- bus2_ram_unknown_addr_in <= '0';
- buf_bus2_ram_read_enable_out <= '0';
- buf_buf_bus2_ram_read_enable_out <= '0';
- bus2_status_data_in <= (others =>'0');
- bus2_status_dataready_in <= '0';
- bus2_status_write_ack_in <= '0';
- bus2_status_no_more_data_in <= '0';
- bus2_status_unknown_addr_in <= '0';
- bus2_control_data_in <= (others =>'0');
- bus2_control_dataready_in <= '0';
- bus2_control_write_ack_in <= '0';
- bus2_control_no_more_data_in <= '0';
- bus2_control_unknown_addr_in <= '0';
- bus2_debug_data_in <= (others =>'0');
- bus2_debug_dataready_in <= '0';
- bus2_debug_write_ack_in <= '0';
- bus2_debug_no_more_data_in <= '0';
- bus2_debug_unknown_addr_in <= '0';
- bus2_status2_data_in <= (others =>'0');
- bus2_status2_dataready_in <= '0';
- bus2_status2_write_ack_in <= '0';
- bus2_status2_no_more_data_in <= '0';
- bus2_status2_unknown_addr_in <= '0';
- bus2_status2_read_ram3b <= '0';
- buf_bus2_status2_read_ram3b <= '0';
- prog_jtag_finished <= '0';
- --last_write_successful <= '0';
- -- NEW SIGNALS
- ram1a_a1_base_addr <= (others =>'0');
- ram1a_a1_rel_addr <= (others =>'0');
- ram1a_din1 <= (others =>'0');
- ram1a_wr1 <= '0';
- jtag_status2_copy_requested <= '0';
- jtag_status2_copy_request_strobe <= '0';
- cps2_state <= CPS2_IDLE;
- status2_run_counter <= (others =>'0');
- status2_chain_status <= (others =>'0');
- jtag_clock_cycle_length <= (others =>'0');
- jtag_clock_time1 <= (others =>'0');
- jtag_clock_time2 <= (others =>'0');
- jtag_sample_time1 <= (others =>'0');
- jtag_sample_time2 <= (others =>'0');
- jtag_sample_time3 <= (others =>'0');
- jtag_set_data_time <= (others => '0');
- jtag_pulses_reset <= '0';
- jtag_sample_pulse3_d1 <= '0';
- breakpoint_active <= (others => '0');
- ram1b_a2 <= (others => '0');
- ram3b_a2_rel_addr <= (others => '0');
- ram3b_a2_base_addr <= (others => '0');
-
- ram1b_copy_requested <= '0';
- ram1c_run_counter <= (others => '0');
- ram1c_chain_status <= (others => '0');
- cpr1bc_state <= CPR1BC_IDLE;
- trigger_copy_ram1b1c <= '0';
- ram1b1c_copy_trigger_active <= (others => '0');
- ram1c_a2 <= (others => '0');
- ram1b1c_copy_trigger_strobe <= (others => '0');
-
- m26csoptions <= (others => '0');
- jtag_delay_expvalues <= (others => '0');
-
- crc_error_on_last_check <= '0';
- last_run_successful <= '0';
- last_run_successful_tmp <= '0';
- else
- --bus_rw_state <= bus_rw_state_next;
- --status_register <= status_register_next;
- --status_register_read_error2 <= status_register_read_error2_next;
- data_register <= data_register_next;
- --cmd_register <= cmd_register_next;
- --bus_data_out_buffer <= bus_data_out_buffer_next;
- --bus_dataready <= bus_dataready_next;
- --bus_no_more_data <= bus_no_more_data_next;
- --bus_write_ack <= bus_write_ack_next;
- --bus_unknown_addr <= bus_unknown_addr_next;
- --length_register <= length_register_next;
- jtag_refresh_active <= jtag_refresh_active_next;
- jtag_check1_active <= jtag_check1_active_next;
- jtag_refresh_active_last <= jtag_refresh_active_last_next;
- --trigger_counter <= trigger_counter_next;
- idle_out_signal <= idle_out_signal_next;
- --status_register_pos <= status_register_pos_next;
- --status_register_read_running <= status_register_read_running_next;
- --ram_base_addr <= ram_base_addr_next;
- crc_status_register <= crc_status_register_next;
- --write_trigger <= write_trigger_next;
- --write_idle_last <= write_idle_last_next;
- --write_status_register_or <= write_status_register_or_next;
- removed_chips <= removed_chips_next;
- --reactivate_sensor <= reactivate_sensor_next;
- --reactivate_sensor_strobe <= reactivate_sensor_strobe_next;
- --deactivate_sensor <= deactivate_sensor_next;
- --deactivate_sensor_strobe <= deactivate_sensor_strobe_next;
- --disable_write <= disable_write_next;
- --disable_writeerror_for_remove <= disable_writeerror_for_remove_next;
- --disable_remove <= disable_remove_next;
- --debug_one_remove <= debug_one_remove_next;
- --debug_one_remove_strobe <= debug_one_remove_strobe_next;
- --removed_strobe <= removed_strobe_next;
- --read_trigger <= read_trigger_next;
- numchips_configured <= numchips_configured_next;
- --my_status <= my_status_next;
- --m26c_sensor_cand <= m26c_sensor_cand_next;
- chip_counter_start <= chip_counter_start_next;
- --m26c_firstrun <= m26c_firstrun_next;
- --m26c_secondrun <= m26c_secondrun_next;
- --mux_sel <= mux_sel_next;
- --driver_speed <= driver_speed_next;
- --already_written <= already_written_next;
- --read_idle_last <= read_idle_last_next;
- --write_error_counter <= write_error_counter_next;
- --write_error_over_threshold_counter <= write_error_over_threshold_counter_next;
- --write_data_changed_counter <= write_data_changed_counter_next;
- --read_error_counter <= read_error_counter_next;
- --read_error_over_threshold_counter <= read_error_over_threshold_counter_next;
- --m26c_state <= m26c_state_next;
- debug_test <= debug_test_next;
- debug_m26cs_state <= debug_m26cs_state_next;
- bus2_ram_data_in <= bus2_ram_data_in_next;
- bus2_ram_dataready_in <= bus2_ram_dataready_in_next;
- bus2_ram_write_ack_in <= bus2_ram_write_ack_in_next;
- bus2_ram_no_more_data_in <= bus2_ram_no_more_data_in_next;
- bus2_ram_unknown_addr_in <= bus2_ram_unknown_addr_in_next;
- buf_bus2_ram_read_enable_out <= buf_bus2_ram_read_enable_out_next;
- buf_buf_bus2_ram_read_enable_out <= buf_buf_bus2_ram_read_enable_out_next;
- bus2_status_data_in <= bus2_status_data_in_next;
- bus2_status_dataready_in <= bus2_status_dataready_in_next;
- bus2_status_write_ack_in <= bus2_status_write_ack_in_next;
- bus2_status_no_more_data_in <= bus2_status_no_more_data_in_next;
- bus2_status_unknown_addr_in <= bus2_status_unknown_addr_in_next;
- bus2_control_data_in <= bus2_control_data_in_next;
- bus2_control_dataready_in <= bus2_control_dataready_in_next;
- bus2_control_write_ack_in <= bus2_control_write_ack_in_next;
- bus2_control_no_more_data_in <= bus2_control_no_more_data_in_next;
- bus2_control_unknown_addr_in <= bus2_control_unknown_addr_in_next;
- bus2_debug_data_in <= bus2_debug_data_in_next;
- bus2_debug_dataready_in <= bus2_debug_dataready_in_next;
- bus2_debug_write_ack_in <= bus2_debug_write_ack_in_next;
- bus2_debug_no_more_data_in <= bus2_debug_no_more_data_in_next;
- bus2_debug_unknown_addr_in <= bus2_debug_unknown_addr_in_next;
- bus2_status2_data_in <= bus2_status2_data_in_next;
- bus2_status2_dataready_in <= bus2_status2_dataready_in_next;
- bus2_status2_write_ack_in <= bus2_status2_write_ack_in_next;
- bus2_status2_no_more_data_in <= bus2_status2_no_more_data_in_next;
- bus2_status2_unknown_addr_in <= bus2_status2_unknown_addr_in_next;
- bus2_status2_read_ram3b <= bus2_status2_read_ram3b_next;
- buf_bus2_status2_read_ram3b <= buf_bus2_status2_read_ram3b_next;
- prog_jtag_finished <= prog_jtag_finished_next;
- --last_write_successful <= last_write_successful_next;
- -- NEW SIGNALS
- ram1a_a1_base_addr <= ram1a_a1_base_addr_next;
- ram1a_a1_rel_addr <= ram1a_a1_rel_addr_next;
- ram1a_din1 <= ram1a_din1_next;
- ram1a_wr1 <= ram1a_wr1_next;
- jtag_status2_copy_requested <= jtag_status2_copy_requested_next;
- jtag_status2_copy_request_strobe <= jtag_status2_copy_request_strobe_next;
- cps2_state <= cps2_state_next;
- status2_run_counter <= status2_run_counter_next;
- status2_chain_status <= status2_chain_status_next;
- jtag_clock_cycle_length <= jtag_clock_cycle_length_next;
- jtag_clock_time1 <= jtag_clock_time1_next;
- jtag_clock_time2 <= jtag_clock_time2_next ;
- jtag_sample_time1 <= jtag_sample_time1_next;
- jtag_sample_time2 <= jtag_sample_time2_next;
- jtag_sample_time3 <= jtag_sample_time3_next;
- jtag_set_data_time <= jtag_set_data_time_next;
- jtag_pulses_reset <= jtag_pulses_reset_next;
- jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next;
- breakpoint_active <= breakpoint_active_next;
- ram1b_a2 <= ram1b_a2_next;
- ram3b_a2_rel_addr <= ram3b_a2_rel_addr_next;
- ram3b_a2_base_addr <= ram3b_a2_base_addr_next;
-
- ram1b_copy_requested <= ram1b_copy_requested_next;
- ram1c_run_counter <= ram1c_run_counter_next;
- ram1c_chain_status <= ram1c_chain_status_next;
- cpr1bc_state <= cpr1bc_state_next;
- trigger_copy_ram1b1c <= trigger_copy_ram1b1c_next;
- ram1b1c_copy_trigger_active <= ram1b1c_copy_trigger_active_next;
- ram1c_a2 <= ram1c_a2_next;
- ram1b1c_copy_trigger_strobe <= ram1b1c_copy_trigger_strobe_next;
-
- m26csoptions <= m26csoptions_next;
- jtag_delay_expvalues <= jtag_delay_expvalues_next;
- crc_error_on_last_check <= crc_error_on_last_check_next;
- last_run_successful <= last_run_successful_next;
- last_run_successful_tmp <= last_run_successful_tmp_next;
- end if;
- end if;
-end process;
-
-
-SYNCHRONOUS_CHIP_COUNTER : process (CLK_IN)
-begin
- if (rising_edge(CLK_IN)) then
- if(RESET_IN = '1') then
- cc_state <= CC_IDLE;
- numchips_active <= (others =>'0');
- numchips_active_acc <= (others =>'0');
- cc_chip_i <= (others =>'0');
- cc_nextnotremoved_i <= (others =>'0');
- last_not_removed <= (others =>'0');
- first_not_removed <= (others =>'0');
- jtag_next_not_removed <= (others =>'0');
- else
- cc_state <= cc_state_next;
- numchips_active <= numchips_active_next;
- numchips_active_acc <= numchips_active_acc_next;
- cc_chip_i <= cc_chip_i_next;
- cc_nextnotremoved_i <= cc_nextnotremoved_i_next;
- last_not_removed <= last_not_removed_next;
- first_not_removed <= first_not_removed_next;
- jtag_next_not_removed <= jtag_next_not_removed_next;
- end if;
- end if;
-end process;
-
-COMB_CHIP_COUNTER : process (cc_state, removed_chips, chip_counter_start, numchips_configured, cc_chip_i, cc_nextnotremoved_i, numchips_active, numchips_active_acc, last_not_removed, first_not_removed, jtag_next_not_removed)
-begin
- cc_state_next <= cc_state;
- numchips_active_next <= numchips_active;
- numchips_active_acc_next <= numchips_active_acc;
- -- index, running through chips
- cc_chip_i_next <= cc_chip_i;
- -- index, last not removed sensor
- cc_nextnotremoved_i_next <= cc_nextnotremoved_i;
- last_not_removed_next <= last_not_removed;
- first_not_removed_next <= first_not_removed;
-
- jtag_next_not_removed_next <= jtag_next_not_removed;
- case cc_state is
- when CC_IDLE =>
- if(chip_counter_start = '1') then
- -- determine number of chips connected in serial to jtag chain
- cc_chip_i_next <= (others => '0');
- cc_nextnotremoved_i_next <= (others => '0');
- -- with the following initialization no chip will be unremoved, because
- -- last_not_removed < first_not_removed
- -- and numchips_active will be set to 0 if really all chips are removed
- first_not_removed_next <= (others => '1');
- last_not_removed_next <= (others =>'0');
- jtag_next_not_removed_next <= (others =>'0');
- numchips_active_acc_next <= (others => '0');
- cc_state_next <= CC_COUNT_SENSOR;
- end if;
- when CC_COUNT_SENSOR =>
- if(removed_chips(to_integer(cc_chip_i)) = '0') then
- numchips_active_acc_next <= numchips_active_acc + 1;
- last_not_removed_next <= cc_chip_i;
- -- if first_not_removed unset
- if(std_logic_vector_all_components_equal_scalar(std_logic_vector(first_not_removed), '1') = '1') then
- first_not_removed_next <= cc_chip_i;
- end if;
- cc_nextnotremoved_i_next <= cc_chip_i + 1; -- next not removed chip after chip i is stored at location (i+1) in jtag_next_not_removed
- jtag_next_not_removed_next(to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto to_integer(cc_nextnotremoved_i)*MAX_NUMCHIPS_LD) <=
- std_logic_vector(cc_chip_i);
- end if;
- if(cc_chip_i = numchips_configured - 1) then
- jtag_next_not_removed_next((to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_PLUS_ONE_LD+MAX_NUMCHIPS_LD-1 downto (to_integer(cc_chip_i)+1)*MAX_NUMCHIPS_LD) <= (others => '1'); -- set next chip for last chip to invalid
- cc_state_next <= CC_SETNUMCHIPS; -- finished counting active chips
- else
- cc_chip_i_next <= cc_chip_i + 1;
- end if;
- when CC_SETNUMCHIPS =>
- numchips_active_next <= numchips_active_acc;
- cc_state_next <= CC_IDLE;
- end case;
-end process;
-
-
--- delay one clock cycle
-jtag_refresh_active_last_next <= jtag_refresh_active;
-
-
--- monitoring
---MON_FIFO_WRITE_OUT(0) <= read_mon_write_out;
---MON_FIFO_WRITE_OUT(1) <= read_mon_write_out;
---MON_FIFO_WRITE_OUT(2) <= read_mon_write_out;
--- monitoring debug test
---MON_FIFO_DATA_OUT(79 downto 64) <= JTAG_M26_DEV_ID(15 downto 0);
---MON_FIFO_DATA_OUT(111 downto 96) <= JTAG_M26_DEV_ID(31 downto 16);
---MON_FIFO_WRITE_OUT(2) <= '1';
---MON_FIFO_WRITE_OUT(3) <= '1';
-
-SYNCHRONOUS_M26_CONTROLLER_SIMPLE : process (CLK_IN)
-begin
- if (rising_edge(CLK_IN)) then
- if(RESET_IN = '1') then
- m26cs_state <= M26CSS_STOPPED;
- trigger_begin_bypassreg <= '0';
- trigger_jtag_read <= '0';
- trigger_jtag_write <= '0';
- trigger_copy_ram3 <= '0';
- trigger_juec_update_d_ch <= '0';
- trigger_juec_update_rd_err <= '0';
- trigger_juec_update_wr_err <= '0';
- trigger_juec_update_run_counter <= '0';
- trigger_check_crc_ram1a <= '0';
- trigger_init_ram1b <= '0';
- trigger_blank_ram3a <= '0';
- run_counter <= (others =>'0');
- m26cs_firstrun <= '0';
- jtag_chain_broken_counter <= (others =>'0');
- ram1a_select <= (others =>'0');
- ram1b_select <= '0';
- ram2_select <= '0';
- ram3a_select <= '0';
- ram3a_rd_select <= '0';
- chain_status <= (others =>'0');
- request_reset <= '0';
- reset_wait <= (others =>'0');
- run_requested <= '0';
- write_once_requested <= '0';
- write_once_count <= (others =>'0');
- -- INSERTLABEL: SYNCHRONOUS reset
- else
- m26cs_state <= m26cs_state_next;
- trigger_begin_bypassreg <= trigger_begin_bypassreg_next;
- trigger_jtag_read <= trigger_jtag_read_next;
- trigger_jtag_write <= trigger_jtag_write_next;
- trigger_copy_ram3 <= trigger_copy_ram3_next;
- trigger_juec_update_d_ch <= trigger_juec_update_d_ch_next;
- trigger_juec_update_rd_err <= trigger_juec_update_rd_err_next;
- trigger_juec_update_wr_err <= trigger_juec_update_wr_err_next;
- trigger_juec_update_run_counter <= trigger_juec_update_run_counter_next;
- trigger_check_crc_ram1a <= trigger_check_crc_ram1a_next;
- trigger_init_ram1b <= trigger_init_ram1b_next;
- trigger_blank_ram3a <= trigger_blank_ram3a_next;
- run_counter <= run_counter_next;
- m26cs_firstrun <= m26cs_firstrun_next;
- jtag_chain_broken_counter <= jtag_chain_broken_counter_next;
- ram1a_select <= ram1a_select_next;
- ram1b_select <= ram1b_select_next;
- ram2_select <= ram2_select_next;
- ram3a_select <= ram3a_select_next;
- ram3a_rd_select <= ram3a_rd_select_next;
- chain_status <= chain_status_next;
- request_reset <= request_reset_next;
- reset_wait <= reset_wait_next;
- run_requested <= run_requested_next;
- write_once_requested <= write_once_requested_next;
- write_once_count <= write_once_count_next;
- -- INSERTLABEL: SYNCHRONOUS update
- end if;
- end if;
-end process;
-
-COMB_M26_CONTROLLER_SIMPLE : process (RUN_REQUEST_IN, WRITE_ONCE_REQUEST_IN, m26cs_state, jtag_bypassreg_last_tck_cycle, jtag_bypassreg_idle, jtag_read_idle, jtag_write_last_tck_cycle, jtag_write_idle, juec_idle, cc_state, breakpoint_active, run_counter, m26cs_firstrun, jtag_status2_copy_requested, jtag_check1_active, jtag_refresh_active, jtag_chain_broken_counter, prog_jtag_finished, ram1a_select, jtag_check_crc_ram1a_idle, jtag_check_crc_ram1a_crc_ok, numchips_configured, ram1a_select, ram1b_select, ram2_select, ram3a_select, ram3a_rd_select, chain_status, jtag_init_ram1b_idle, jtag_bypassreg_chain_broken, jtag_bypassreg_length, crc_status_register, jtag_blank_ram3a_idle, ram1b_copy_requested, jtag_refresh_active_last, m26csoptions, crc_error_on_last_check, last_run_successful, last_run_successful_tmp, last_read_error, last_write_error, request_reset, reset_wait, run_requested, write_once_requested, write_once_count) -- INSERTLABEL: sensitivity list --jtag_read_last_tck_cycle,
-variable output : std_logic;
-variable i : integer;
-begin
- m26cs_state_next <= m26cs_state;
- trigger_begin_bypassreg_next <= '0';
- trigger_jtag_read_next <= '0';
- trigger_jtag_write_next <= '0';
- trigger_juec_update_d_ch_next <= '0';
- trigger_juec_update_rd_err_next <= '0';
- trigger_juec_update_wr_err_next <= '0';
- trigger_juec_update_run_counter_next <= '0';
- trigger_check_crc_ram1a_next <= '0';
- trigger_init_ram1b_next <= '0';
- trigger_blank_ram3a_next <= '0';
- run_counter_next <= run_counter;
- m26cs_firstrun_next <= m26cs_firstrun;
- idle_out_signal_next <= '0';
- jtag_chain_broken_counter_next <= jtag_chain_broken_counter;
- chip_counter_start_next <= '0';
- prog_jtag_finished_next <= prog_jtag_finished;
- chain_status_next <= chain_status;
- crc_status_register_next <= crc_status_register;
-
- -- ram multiplexers
- ram1a_select_next <= ram1a_select;
- ram1b_select_next <= ram1b_select;
- ram2_select_next <= ram2_select;
- ram3a_select_next <= ram3a_select;
- ram3a_rd_select_next <= ram3a_rd_select;
-
- crc_error_on_last_check_next <= crc_error_on_last_check;
- last_run_successful_next <= last_run_successful;
- last_run_successful_tmp_next <= last_run_successful_tmp;
- begin_count_read_errors <= '0'; -- added 201210
- begin_count_write_errors <= '0'; -- added 201210
- begin_count_data_changed <= '0'; -- added 201210
- end_count_read_errors <= '0'; -- added 201210
- end_count_write_errors <= '0'; -- added 201210
- end_count_data_changed <= '0'; -- added 201210
- request_reset_next <= request_reset;
- reset_wait_next <= reset_wait;
- run_requested_next <= run_requested;
- write_once_requested_next <= write_once_requested;
- write_once_count_next <= write_once_count;
- -- INSERTLABEL: COMB defaults
-
-
-
- case m26cs_state is
- when M26CSS_STOPPED =>
- -- if stopped, start again if jtag_refresh_active is set
- if(jtag_check1_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
- m26cs_state_next <= M26CSS_CHECK1_WAIT_FOR_HAVE_TIME;
- elsif(jtag_refresh_active = '1' and jtag_status2_copy_requested = '0' and ram1b_copy_requested = '0') then
- m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- -- if just started, reset all counters
- if(jtag_refresh_active_last = '0') then
- m26cs_firstrun_next <= '1';
- end if;
- end if;
- when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
- --if(have_time_for_check) then
- m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
- --end if;
-
- when M26CSS_WAIT_FOR_TRIGGER =>
- idle_out_signal_next <= '1';
- last_run_successful_next <= last_run_successful_tmp;
- -- if not stopped, test if we should stop
- if(jtag_refresh_active = '0' or jtag_status2_copy_requested = '1' or ram1b_copy_requested = '1') then
- ram3a_rd_select_next <= '0'; -- select jtag_copy_ram3_ram3a
- m26cs_state_next <= M26CSS_STOPPED;
- else
- -- if we should not stop, check for off_spill and if we have time for writing
- if(run_requested = '1') then
- -- increment run counter (exclusively done here)
- run_counter_next <= run_counter + 1;
- prog_jtag_finished_next <= '0';
- trigger_check_crc_ram1a_next <= '1';
- ram1a_select_next <= "11"; -- select check_crc_ram1a
- if(m26cs_firstrun = '1') then
- trigger_blank_ram3a_next <= '1';
- ram3a_select_next <= '1'; -- blank_ram3a (at same time)
- end if;
- last_run_successful_tmp_next <= '0';
- m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_BEGIN;
- elsif(write_once_requested = '1') then
- trigger_check_crc_ram1a_next <= '1';
- ram1a_select_next <= "11"; -- select check_crc_ram1a
- m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN;
- end if;
- end if;
- when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
- m26cs_state_next <= M26CSS_CHECK_CRC_RAM1A_WAIT;
- when M26CSS_CHECK_CRC_RAM1A_WAIT =>
- if(jtag_check_crc_ram1a_idle = '1') then
- crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
- output := '1';
- for i in MAX_NUMCHIPS-1 downto 0 loop
- if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
- output := '0';
- end if;
- end loop;
- --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
- if(output = '1') then
- -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
- crc_error_on_last_check_next <= '0';
- trigger_init_ram1b_next <= '1';
- ram1b_select_next <= '0'; -- select init ram1b
- ram1a_select_next <= "10"; -- select init ram1b
- m26cs_state_next <= M26CSS_INIT_RAM1B_BEGIN;
- else
- -- crc error in configured chips, don't continue
- crc_error_on_last_check_next <= '1';
- -- clear requests
- run_requested_next <= '0';
- write_once_requested_next <= '0';
- m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- end if;
- end if;
- when M26CSS_INIT_RAM1B_BEGIN =>
- m26cs_state_next <= M26CSS_INIT_RAM1B_WAIT;
- when M26CSS_INIT_RAM1B_WAIT =>
- if(jtag_init_ram1b_idle = '1') then
- if(m26cs_firstrun = '1') then
- -- skip data changed
- chip_counter_start_next <= '1';
- m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
- else
- trigger_jtag_write_next <= '1';
- ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- ram2_select_next <= '0'; -- tdo_compare_count
- begin_count_data_changed <= '1';-- added 201210
- m26cs_state_next <= M26CSS_DATA_CHANGED_BEGIN;
- end if;
- end if;
- when M26CSS_DATA_CHANGED_BEGIN =>
- m26cs_state_next <= M26CSS_DATA_CHANGED_WAIT;
- when M26CSS_DATA_CHANGED_WAIT =>
- if(jtag_write_last_tck_cycle = '1' or jtag_write_idle = '1') then
- end_count_data_changed <= '1'; -- added 201210
- m26cs_state_next <= M26CSS_BLANK_RAM3A_WAIT;
- end if;
- when M26CSS_BLANK_RAM3A_WAIT =>
- if(jtag_blank_ram3a_idle = '1') then
- if(breakpoint_active(0) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- trigger_juec_update_d_ch_next <= '1';
- ram2_select_next <= '1'; -- juec
- ram3a_select_next <= '0'; -- juec
- m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_BEGIN;
- end if;
- end if;
- when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
- m26cs_state_next <= M26CSS_JUEC_DATA_CHANGED_WAIT;
- when M26CSS_JUEC_DATA_CHANGED_WAIT =>
- if(juec_idle = '1') then
- if(breakpoint_active(1) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- chip_counter_start_next <= '1';
- m26cs_state_next <= M26CSS_COUNT_CHIPS_BEGIN;
- end if;
- end if;
-
- when M26CSS_COUNT_CHIPS_BEGIN =>
- m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- when M26CSS_COUNT_CHIPS_WAIT =>
- if(cc_state = CC_IDLE) then
- if(breakpoint_active(2) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
--- if(m26csoptions(0) = '1') then
- -- skip BYPASSREG CHAIN TEST
- -- and set CHAIN status to BROKEN
- chain_status_next(0) <= '1';
- chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0');
- -- next state:
- ram2_select_next <= '0'; -- tdo_compare_count
- ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
- begin_count_read_errors <= '1'; -- added 201210
- m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
--- else
--- trigger_begin_bypassreg_next <= '1';
--- m26cs_state_next <= M26CSS_BYPASSREG_BEGIN;
--- end if;
- end if;
- end if;
- when M26CSS_BYPASSREG_BEGIN =>
- m26cs_state_next <= M26CSS_BYPASSREG_WAIT;
- when M26CSS_BYPASSREG_WAIT =>
- if(jtag_bypassreg_last_tck_cycle = '1' or jtag_bypassreg_idle = '1') then
- if(breakpoint_active(3) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- chain_status_next(0) <= jtag_bypassreg_chain_broken; -- chain broken
- if(unsigned(jtag_bypassreg_length) < 2**MAX_NUMCHIPS_PLUS_ONE_LD) then
- chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= jtag_bypassreg_length(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0); -- chain length
- else
- chain_status_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 3) <= (others => '0'); -- chain length: set to zero because to long chain found
- end if;
- if(jtag_bypassreg_chain_broken = '1') then
- jtag_chain_broken_counter_next <= jtag_chain_broken_counter + 1;
-
- --m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- ram2_select_next <= '0'; -- tdo_compare_count
- ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- trigger_jtag_read_next <= '1';-- temporarily go on (for testing without mimosa26 emulator)
- begin_count_read_errors <= '1'; -- added 201210
- m26cs_state_next <= M26CSS_READ1_BEGIN; -- temporarily go on (for testing without mimosa26 emulator)
- else
- ram2_select_next <= '0'; -- tdo_compare_count
- ram1a_select_next <= "00"; -- select jtag_read_ram1a_a
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- trigger_jtag_read_next <= '1';
- begin_count_read_errors <= '1'; -- added 201210
- m26cs_state_next <= M26CSS_READ1_BEGIN;
- end if;
- end if;
- end if;
- when M26CSS_READ1_BEGIN =>
- m26cs_state_next <= M26CSS_READ1_WAIT;
- when M26CSS_READ1_WAIT =>
- if(jtag_read_idle = '1') then -- removed (jtag_read_last_tck_cycle = '1' or ) because writing to RAM needs time
- end_count_read_errors <= '1'; -- added 201210
- if(breakpoint_active(4) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- trigger_juec_update_rd_err_next <= '1';
- ram2_select_next <= '1'; -- juec
- ram3a_select_next <= '0'; -- juec
- m26cs_state_next <= M26CSS_JUEC_READ_BEGIN;
- end if;
- end if;
- when M26CSS_JUEC_READ_BEGIN =>
- m26cs_state_next <= M26CSS_JUEC_READ_WAIT;
- when M26CSS_JUEC_READ_WAIT =>
- if(juec_idle = '1') then
- if(breakpoint_active(5) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- elsif(jtag_check1_active = '1') then
- -- in case of check1 set, don't write registers
- -- in order to save time
- -- clear requests
- run_requested_next <= '0';
- write_once_requested_next <= '0';
- m26cs_state_next <= M26CSS_STOPPED;
- else
- -- do the following later!
- --trigger_jtag_write_next <= '1';
- --ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
- --ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- --ram2_select_next <= '0'; -- tdo_compare_count
- m26cs_state_next <= M26CSS_REQUEST_RESET_BEGIN;
- end if;
- end if;
- when M26CSS_REQUEST_RESET_BEGIN =>
- request_reset_next <= '1';
- m26cs_state_next <= M26CSS_REQUEST_RESET_WAIT;
- when M26CSS_REQUEST_RESET_WAIT =>
- reset_wait_next <= RESET_WAIT_DURATION;
- m26cs_state_next <= M26CSS_REQUESTED_RESET_WAIT;
- when M26CSS_REQUESTED_RESET_WAIT =>
- reset_wait_next <= reset_wait - 1;
- request_reset_next <= '0';
- if(reset_wait = reset_wait_zero) then
- trigger_jtag_write_next <= '1';
- ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
- if(ram1b_copy_requested = '0') then -- this is a hack, to only change ram1b if not yet data changed triggered copy request
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- else
- ram1b_select_next <= '0';
- end if;
- ram2_select_next <= '0'; -- tdo_compare_count
- m26cs_state_next <= M26CSS_WRITE1_BEGIN;
- end if;
- when M26CSS_WRITE1_BEGIN =>
- m26cs_state_next <= M26CSS_WRITE1_WAIT;
- when M26CSS_WRITE1_WAIT =>
- if(jtag_write_idle = '1') then
- if(breakpoint_active(6) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- trigger_jtag_write_next <= '1';
- begin_count_write_errors <= '1'; -- added 201210
- m26cs_state_next <= M26CSS_WRITE2_BEGIN;
- end if;
- end if;
- when M26CSS_WRITE2_BEGIN =>
- m26cs_state_next <= M26CSS_WRITE2_WAIT;
- when M26CSS_WRITE2_WAIT =>
- if(jtag_write_idle = '1') then
- end_count_write_errors <= '1'; -- added 201210
- if(breakpoint_active(7) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- prog_jtag_finished_next <= '1';
- trigger_juec_update_wr_err_next <= '1';
- ram2_select_next <= '1'; -- juec
- ram3a_select_next <= '0'; -- juec
- m26cs_state_next <= M26CSS_JUEC_WRITE_BEGIN;
- end if;
- end if;
- when M26CSS_JUEC_WRITE_BEGIN =>
- m26cs_state_next <= M26CSS_JUEC_WRITE_WAIT;
- when M26CSS_JUEC_WRITE_WAIT =>
- if(juec_idle = '1') then
- if(breakpoint_active(8) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- trigger_juec_update_run_counter_next <= '1';
- m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_BEGIN;
- end if;
- end if;
- when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
- m26cs_state_next <= M26CSS_JUEC_RUN_COUNTER_WAIT;
- when M26CSS_JUEC_RUN_COUNTER_WAIT =>
- if(juec_idle = '1') then
- if(breakpoint_active(9) = '1') then
- --stay in state
- --m26cs_state_next <= M26CSS_COUNT_CHIPS_WAIT;
- else
- m26cs_firstrun_next <= '0';
- last_run_successful_tmp_next <= not (last_read_error or last_write_error); -- added 201210
- -- clear requests
- run_requested_next <= '0';
- write_once_requested_next <= '0';
- m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- end if;
- end if;
-
-
- -- WRITE_ONCE states
- when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
- m26cs_state_next <= M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT;
- when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
- if(jtag_check_crc_ram1a_idle = '1') then
- crc_status_register_next <= jtag_check_crc_ram1a_crc_ok;
- output := '1';
- for i in MAX_NUMCHIPS-1 downto 0 loop
- if(jtag_check_crc_ram1a_crc_ok(i) /= '1' and i < to_integer(numchips_configured)) then
- output := '0';
- end if;
- end loop;
- --if(std_logic_vector_all_components_equal_scalar(jtag_check_crc_ram1a_crc_ok(to_integer(numchips_configured)-1 downto 0), '1') = '1') then
- if(output = '1') then
- -- if no crc errors for configured chips (consider changing this to checking the whole vector, and also let zeros be ok for crc check)
- crc_error_on_last_check_next <= '0';
- trigger_init_ram1b_next <= '1';
- ram1b_select_next <= '0'; -- select init ram1b
- ram1a_select_next <= "10"; -- select init ram1b
- m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_BEGIN;
- else
- -- crc error in configured chips, don't continue
- crc_error_on_last_check_next <= '1';
- run_requested_next <= '0';
- write_once_requested_next <= '0';
- m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- end if;
- end if;
- when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
- m26cs_state_next <= M26CSS_WRITEONCE_INIT_RAM1B_WAIT;
- when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
- if(jtag_init_ram1b_idle = '1') then
- chip_counter_start_next <= '1';
- m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN;
- end if;
- when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
- m26cs_state_next <= M26CSS_WRITEONCE_COUNT_CHIPS_WAIT;
- when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
- trigger_jtag_write_next <= '1';
- ram1a_select_next <= "01"; -- select jtag_write_ram1a_a
- ram1b_select_next <= '1'; -- select jtag_data_to_ram_ram1b
- ram2_select_next <= '0'; -- tdo_compare_count
- m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_BEGIN;
- when M26CSS_WRITEONCE_WRITE1_BEGIN =>
- m26cs_state_next <= M26CSS_WRITEONCE_WRITE1_WAIT;
- when M26CSS_WRITEONCE_WRITE1_WAIT =>
- if(jtag_write_idle = '1') then
- -- clear requests
- run_requested_next <= '0';
- write_once_requested_next <= '0';
- write_once_count_next <= write_once_count + 1;
- m26cs_state_next <= M26CSS_WAIT_FOR_TRIGGER;
- end if;
- end case;
- if(RUN_REQUEST_IN = '1') then
- run_requested_next <= '1';
- end if;
- if(WRITE_ONCE_REQUEST_IN = '1') then
- write_once_requested_next <= '1';
- end if;
-
-end process;
-
-
-status2_copy_finished <= not jtag_status2_copy_requested and not jtag_status2_copy_request_strobe;
-CP_STATUS2 : process(jtag_status2_copy_requested, jtag_status2_copy_request_strobe, status2_chain_status, status2_run_counter, cps2_state, m26cs_state, jtag_copy_ram3_idle, run_counter, chain_status)
-begin
- jtag_status2_copy_requested_next <= jtag_status2_copy_requested;
- -- these are all copies of the registers changed in M26CS
- status2_run_counter_next <= status2_run_counter;
- status2_chain_status_next <= status2_chain_status;
- cps2_state_next <= cps2_state;
- trigger_copy_ram3_next <= '0';
- case cps2_state is
- when CPS2_IDLE =>
- if(jtag_status2_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
- trigger_copy_ram3_next <= '1';
- cps2_state_next <= CPS2_COPY_BEGIN;
- end if;
- when CPS2_COPY_BEGIN =>
- status2_run_counter_next <= run_counter;
- status2_chain_status_next <= chain_status;
- cps2_state_next <= CPS2_COPY_WAIT;
- when CPS2_COPY_WAIT =>
- if(jtag_copy_ram3_idle = '1') then
- jtag_status2_copy_requested_next <= '0';
- cps2_state_next <= CPS2_IDLE;
- end if;
- end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
- if(jtag_status2_copy_request_strobe = '1') then
- jtag_status2_copy_requested_next <= '1';
- end if;
-end process;
-
-TRIGGER_CP_RAM1B1C : process(ram1b_copy_requested, ram1c_run_counter, ram1c_chain_status, ram1b1c_copy_trigger_active, ram1b1c_copy_trigger_strobe, copy_ram1b1c_idle, cpr1bc_state, m26cs_state, run_counter, chain_status, juec_read_errors, juec_write_errors, juec_data_changed)
-begin
- ram1b_copy_requested_next <= ram1b_copy_requested;
- -- these are all copies of the registers changed in M26CS
- ram1c_run_counter_next <= ram1c_run_counter;
- ram1c_chain_status_next <= ram1c_chain_status;
- cpr1bc_state_next <= cpr1bc_state;
- trigger_copy_ram1b1c_next <= '0';
- ram1b1c_copy_trigger_active_next <= ram1b1c_copy_trigger_active or ram1b1c_copy_trigger_strobe;
- case cpr1bc_state is
- when CPR1BC_IDLE =>
- if(ram1b_copy_requested = '1' and m26cs_state = M26CSS_STOPPED) then
- trigger_copy_ram1b1c_next <= '1';
- cpr1bc_state_next <= CPR1BC_COPY_BEGIN;
- end if;
- when CPR1BC_COPY_BEGIN =>
- ram1c_run_counter_next <= run_counter;
- ram1c_chain_status_next <= chain_status;
- cpr1bc_state_next <= CPR1BC_COPY_WAIT;
- when CPR1BC_COPY_WAIT =>
- if(copy_ram1b1c_idle = '1') then
- ram1b_copy_requested_next <= '0';
- cpr1bc_state_next <= CPR1BC_IDLE;
- end if;
- end case; --finishing needs 2 clock cycles, after 2 clock cycles the next jtag_status2_copy_request_strobe will be accepted. the copying itself needs much longer, so if the querying agent waits till after the copy has finished until the next is requested, the new request not be missed due to this delay
- if(juec_read_errors = '1' and ram1b1c_copy_trigger_active(0) = '1') or
- (juec_write_errors = '1' and ram1b1c_copy_trigger_active(1) = '1') or
- (juec_data_changed = '1' and ram1b1c_copy_trigger_active(2) = '1') or
- (ram1b1c_copy_trigger_active(3) = '1') then
- ram1b_copy_requested_next <= '1';
- -- deactivate triggers (copy is requested)
- ram1b1c_copy_trigger_active_next <= (others => '0');
- end if;
-end process;
-
-
-
--- -- OR the status bits of all registers separately for each sensor and (JTAG_ERROR, DATA_CHANGED, DATA CHANGED OVER THRESHOLD)
--- WRITE_STATUS_REG_OR : process(write_status_register)
--- variable write_status_reg_acc : std_logic_vector(3*MAX_NUMCHIPS-1 downto 0);
--- begin
--- write_status_reg_acc := (others => '0');
--- for i in 0 to MAX_REGISTERS - 1 loop
--- write_status_reg_acc := write_status_reg_acc or
--- write_status_register( i*3*MAX_NUMCHIPS + 3*MAX_NUMCHIPS - 1 downto
--- i*3*MAX_NUMCHIPS);
--- end loop;
--- write_status_register_or_next <= write_status_reg_acc;
--- end process;
-
-
--- READ_STATUS_REG_OR : process(status_register)
--- variable read_error2_acc : std_logic;
--- begin
--- read_error2_acc := '0';
--- for i in 0 to MAX_NUMCHIPS-1 loop
--- read_error2_acc := read_error2_acc or status_register(STATUS_READ_ERROR2 + i);
--- end loop;
--- status_register_read_error2_next <= read_error2_acc;
--- end process;
-
---numchips_configured_next <= std_logic_vector(to_unsigned(3,MAX_NUMCHIPS_LD+1));
---ram_m26c_a1_next(M26C_RAM_DEPTH-1 downto 8) <= ram_base_addr;
--- put together ram1a address
-ram1a_a1 <= ram1a_a1_base_addr & ram1a_a1_rel_addr;
-buf_bus2_ram_read_enable_out_next <= bus2_ram_read_enable_out;
-buf_buf_bus2_ram_read_enable_out_next <= buf_bus2_ram_read_enable_out;
-BUS2_RAM_RW : process (bus2_ram_addr_out, bus2_ram_data_out, bus2_ram_read_enable_out, bus2_ram_write_enable_out, buf_buf_bus2_ram_read_enable_out, ram1a_dout1, ram1a_din1, ram1a_a1_rel_addr, bus2_ram_data_in, m26cs_stopped)
-begin
- ram1a_wr1_next <= '0';
- ram1a_din1_next <= ram1a_din1;
- ram1a_a1_rel_addr_next <= ram1a_a1_rel_addr;
- bus2_ram_data_in_next <= bus2_ram_data_in;
- bus2_ram_dataready_in_next <= '0';
- bus2_ram_write_ack_in_next <= '0';
- bus2_ram_no_more_data_in_next <= '0';
- bus2_ram_unknown_addr_in_next <= '0';
- if(bus2_ram_write_enable_out='1') then
- ram1a_din1_next <= bus2_ram_data_out;
- ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
- -- only allow ram1a to be changed if stopped!
- if(m26cs_stopped = '1') then
- ram1a_wr1_next <= '1';
- bus2_ram_write_ack_in_next <= '1';
- else
- bus2_ram_unknown_addr_in_next <= '1';
- end if;
- elsif(bus2_ram_read_enable_out='1') then
- ram1a_a1_rel_addr_next <= bus2_ram_addr_out(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0);
-
- elsif(buf_buf_bus2_ram_read_enable_out='1') then
- bus2_ram_data_in_next <= ram1a_dout1;
- bus2_ram_dataready_in_next <= '1';
- end if;
-end process;
-
-BUS2_STATUS_R : process (bus2_status_addr_out, crc_status_register, bus2_status_read_enable_out, bus2_status_write_enable_out, bus2_status_data_in)
-variable bus_addr_int : integer range 0 to 31;
-begin
- bus2_status_data_in_next <= bus2_status_data_in;
- bus2_status_dataready_in_next <= '0';
- bus2_status_write_ack_in_next <= '0';
- bus2_status_no_more_data_in_next <= '0';
- bus2_status_unknown_addr_in_next <= '0';
- if(bus2_status_read_enable_out='1') then
- -- STATUS register layout: 8 bits/chip
- -- first 32 bits : CRC status
- -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
- -- 5: DATA_CHANGED, 6: reserved, 7: reserved
- bus_addr_int := to_integer(unsigned(bus2_status_addr_out(4 downto 0)));
- if(bus_addr_int = 0) then
- bus2_status_data_in_next(31 downto MAX_REGISTERS) <= (others => '0');
- bus2_status_data_in_next(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0);
- bus2_status_dataready_in_next <= '1';
--- elsif(4*(bus_addr_int-1) < MAX_NUMCHIPS) then
--- -- for i in 0 to MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3) loop
--- -- bus2_status_data_in_next(8*i+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+i);
--- -- bus2_status_data_in_next(8*i+7 downto 8*i+6) <= (others => '0');
--- -- end loop;
--- -- bus2_status_data_in_next(31 downto 8*(MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3)+1)) <= (others => '0');
---
--- bus2_status_data_in_next <= (others => '0');
--- bus2_status_data_in_next(8*0+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+6) <= removed_chips(4*(bus_addr_int-1)+0);
--- bus2_status_data_in_next(8*0+7 downto 8*0+7) <= (others => '0');
--- if(4*(bus_addr_int-1)+1 < MAX_NUMCHIPS) then
--- bus2_status_data_in_next(8*1+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+6) <= removed_chips(4*(bus_addr_int-1)+1);
--- bus2_status_data_in_next(8*1+7 downto 8*1+7) <= (others => '0');
--- end if;
--- if(4*(bus_addr_int-1)+2 < MAX_NUMCHIPS) then
--- bus2_status_data_in_next(8*2+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+6) <= removed_chips(4*(bus_addr_int-1)+2);
--- bus2_status_data_in_next(8*2+7 downto 8*2+7) <= (others => '0');
--- end if;
--- if(4*(bus_addr_int-1)+3 < MAX_NUMCHIPS) then
--- bus2_status_data_in_next(8*3+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+3); bus2_status_data_in_next(8*3+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+6) <= removed_chips(4*(bus_addr_int-1)+3);
--- bus2_status_data_in_next(8*3+7 downto 8*3+7) <= (others => '0');
--- end if;
--- bus2_status_dataready_in_next <= '1';
- else
- bus2_status_unknown_addr_in_next <= '1';
- end if;
- end if;
- if(bus2_status_write_enable_out='1') then
- bus2_status_unknown_addr_in_next <= '1';
- end if;
-end process;
-
-BUS2_CONTROL_RW : process (bus2_control_addr_out, bus2_control_data_out, bus2_control_read_enable_out, bus2_control_write_enable_out, bus2_control_data_in, jtag_refresh_active, ram1a_a1_base_addr, data_register, jtag_check1_active, numchips_configured, removed_chips, jtag_clock_cycle_length, jtag_clock_time1, jtag_clock_time2,
-jtag_sample_time1, jtag_sample_time2, jtag_sample_time3, jtag_set_data_time, breakpoint_active, run_counter, debug_trigger_counter, last_not_removed, m26cs_stopped, numchips_active, m26csoptions, jtag_delay_expvalues
-)
-begin
- bus2_control_data_in_next <= bus2_control_data_in;
- bus2_control_dataready_in_next <= '0';
- bus2_control_write_ack_in_next <= '0';
- bus2_control_no_more_data_in_next <= '0';
- bus2_control_unknown_addr_in_next <= '0';
- jtag_refresh_active_next <= jtag_refresh_active;
- ram1a_a1_base_addr_next <= ram1a_a1_base_addr;
- data_register_next <= data_register;
- jtag_status2_copy_request_strobe_next <= '0';
- jtag_check1_active_next <= jtag_check1_active;
- numchips_configured_next <= numchips_configured;
- removed_chips_next <= removed_chips;
- jtag_clock_cycle_length_next <= jtag_clock_cycle_length;
- jtag_clock_time1_next <= jtag_clock_time1;
- jtag_clock_time2_next <= jtag_clock_time2;
- jtag_sample_time1_next <= jtag_sample_time1;
- jtag_sample_time2_next <= jtag_sample_time2;
- jtag_sample_time3_next <= jtag_sample_time3;
- jtag_set_data_time_next <= jtag_set_data_time;
- jtag_pulses_reset_next <= '0';
- breakpoint_active_next <= breakpoint_active;
- ram1b1c_copy_trigger_strobe_next <= (others => '0');
- m26csoptions_next <= m26csoptions;
- jtag_delay_expvalues_next <= jtag_delay_expvalues;
-
- --driver_speed_next <= driver_speed;
- --deactivate_sensor_strobe_next <= (others => '0');
- --reactivate_sensor_strobe_next <= (others => '0');
- --disable_write_next <= disable_write;
- --disable_writeerror_for_remove_next <= disable_writeerror_for_remove;
- --disable_remove_next <= disable_remove;
- --debug_one_remove_strobe_next <= '0';
- if(bus2_control_write_enable_out='1') then
- -- CONTROL registers layout:
- -- ADDR_CONTROL_CMD
- -- ADDR_CONTROL_RAM_BASEADDR
- -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
- -- 5: DATA_CHANGED, 6: reserved, 7: reserved
- if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
- bus2_control_write_ack_in_next <= '1';
- if(bus2_control_data_out(7 downto 0) = M26C_CMD_START) then
- jtag_refresh_active_next <= '1';
- elsif(bus2_control_data_out(7 downto 0) =M26C_CMD_START_CHECK1) then
- jtag_check1_active_next <= '1';
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_STOP) then
- jtag_refresh_active_next <= '0';
- jtag_check1_active_next <= '0';
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REMOVE_SENSOR ) then
- -- only signal ack if really written
- bus2_control_write_ack_in_next <= '0';
- bus2_control_no_more_data_in_next <= '1';
- -- only allowed to change removed chips when not writing to JTAG interface!
- if(m26cs_stopped = '1') then
- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
- removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
- bus2_control_write_ack_in_next <= '1';
- bus2_control_no_more_data_in_next <= '0';
- end if;
- end if;
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_INSERT_SENSOR ) then
- -- only signal ack if really written
- bus2_control_write_ack_in_next <= '0';
- bus2_control_no_more_data_in_next <= '1';
- -- only allowed to change removed chips when not writing to JTAG interface!
- if(jtag_refresh_active = '0' and jtag_check1_active = '0') then
- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
- removed_chips_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '0';
- bus2_control_write_ack_in_next <= '1';
- bus2_control_no_more_data_in_next <= '0';
- end if;
- end if;
- --elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_SPEED) then
- --driver_speed_next <= data_register(15 downto 0);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_SPEED) then
--- data_register_next(31 downto 16) <= (others => '0');
--- data_register_next(15 downto 0) <= driver_speed;
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REACTIVATE_SENSOR) then
--- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
--- reactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
--- end if;
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_DEACTIVATE_SENSOR) then
--- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))<MAX_NUMCHIPS) then
--- deactivate_sensor_strobe_next(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))) <= '1';
--- end if;
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_CONFIGURED) then
- data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
- data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_ACTIVE) then
- data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
- data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_TRIGGER_COUNT) then
- data_register_next <= std_logic_vector(debug_trigger_counter);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DISABLE_WRITE) then
--- data_register_next(31 downto 1) <= (others => '0');
--- data_register_next(0) <= disable_write;
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DISABLE_WRITE) then
--- disable_write_next <= data_register(0);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_LAST_NOT_REMOVED) then
- data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0');
- data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED) then
- data_register_next(31 downto 1) <= (others => '0');
- data_register_next(0) <= removed_chips(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0))));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED32) then
- data_register_next(31 downto MYMIN(MAX_NUMCHIPS-1, 31)) <= (others => '0');
- data_register_next(MYMIN(MAX_NUMCHIPS-1, 31) downto 0) <= removed_chips(MYMIN(MAX_NUMCHIPS-1, 31) downto 0);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REACTIVATE_SENSOR32) then
--- data_register_next(31 downto 0) <= reactivate_sensor(31 downto 0);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DEACTIVATE_SENSOR32) then
--- data_register_next(31 downto 0) <= deactivate_sensor(31 downto 0);
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_M26_DEV_ID) then
--- data_register_next <= JTAG_M26_DEV_ID;
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_NUMCHIPS_CONFIGURED) then
- numchips_configured_next <= unsigned(data_register(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0));
--- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS) then
--- data_register_next(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= std_logic_vector(numchips_configured);
--- data_register_next(31 downto MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_BREAKPOINTS) then
- breakpoint_active_next <= data_register(9 downto 0);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_BREAKPOINTS) then
- data_register_next(9 downto 0) <= breakpoint_active;
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH) then
- jtag_clock_cycle_length_next <= unsigned(data_register(9 downto 0));
- jtag_pulses_reset_next <= '1'; -- reset counter (because maximum value of counter could be exceeded)
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME1) then
- jtag_clock_time1_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME1) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time1);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME2) then
- jtag_clock_time2_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME2) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time2);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME1) then
- jtag_sample_time1_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME1) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time1);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME2) then
- jtag_sample_time2_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME2) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time2);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME3) then
- jtag_sample_time3_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME3) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time3);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SET_DATA_TIME) then
- jtag_set_data_time_next <= unsigned(data_register(9 downto 0));
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SET_DATA_TIME) then
- data_register_next(9 downto 0) <= std_logic_vector(jtag_set_data_time);
- data_register_next(31 downto 10) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_RUN_COUNT) then
- data_register_next(31 downto 0) <= std_logic_vector(run_counter);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_TO_STATUS2) then
- jtag_status2_copy_request_strobe_next <= '1';
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER) then
- ram1b1c_copy_trigger_strobe_next(3 downto 0) <= data_register(3 downto 0); -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR) then
- ram1b1c_copy_trigger_strobe_next(0) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR) then
- ram1b1c_copy_trigger_strobe_next(1) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED) then
- ram1b1c_copy_trigger_strobe_next(2) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW) then
- ram1b1c_copy_trigger_strobe_next(3) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_CSOPTIONS) then
- m26csoptions_next(0 downto 0) <= data_register(0 downto 0); -- bit 0 => skip bypassreg chaintest
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_CSOPTIONS) then
- data_register_next(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest
- data_register_next(31 downto 0+1) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DELAY_EXPECTED_VALUES) then
- jtag_delay_expvalues_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= data_register(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DELAY_EXPECTED_VALUES) then
- data_register_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0);
- data_register_next(31 downto JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD) <= (others => '0');
- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_ACTIVITY) then
- data_register_next(0) <= jtag_refresh_active;
- data_register_next(1) <= jtag_check1_active;
- data_register_next(31 downto 2) <= (others => '0');
- else
- -- revoke write_ack, which was set preliminary before "if"
- bus2_control_write_ack_in_next <= '0';
- bus2_control_unknown_addr_in_next <= '1';
- end if;
- elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
- ram1a_a1_base_addr_next <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0);
- bus2_control_write_ack_in_next <= '1';
- elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
- data_register_next <= bus2_control_data_out;
- bus2_control_write_ack_in_next <= '1';
- else
- bus2_control_unknown_addr_in_next <= '1';
- end if;
- elsif(bus2_control_read_enable_out='1') then
- if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then
- bus2_control_data_in_next <= (others => '0');
- bus2_control_dataready_in_next <= '1';
- elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then
- bus2_control_data_in_next(31 downto RAM_JTAG_REGISTERS_DEPTH-8) <= (others => '0');
- bus2_control_data_in_next(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr;
- bus2_control_dataready_in_next <= '1';
- elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then
- bus2_control_data_in_next <= data_register;
- bus2_control_dataready_in_next <= '1';
- else
- bus2_control_unknown_addr_in_next <= '1';
- end if;
- end if;
-end process;
-
-BUS2_DEBUG_R : process (bus2_debug_addr_out, bus2_debug_read_enable_out, bus2_debug_write_enable_out, bus2_debug_data_in, debug_m26cs_state, debug_trigger_counter, debug_test, ram1b_a2, ram1b_dout2, bus2_debug_data_out, ram1c_a2, ram1c_dout2, ram1c_chain_status, ram1c_run_counter, debugtdo_timeout, debugtdo_underflow, debugtdo_overflow, debugtdo_full, debugtdo_empty, debugtdo_dout, write_once_count)
-begin
- bus2_debug_data_in_next <= bus2_debug_data_in;
- bus2_debug_dataready_in_next <= '0';
- bus2_debug_write_ack_in_next <= '0';
- bus2_debug_no_more_data_in_next <= '0';
- bus2_debug_unknown_addr_in_next <= '0';
- debug_test_next <= debug_test;
- ram1b_a2_next <= ram1b_a2;
- ram1c_a2_next <= ram1c_a2;
- debugtdo_activate_strobe <= '0';
- debugtdo_timeout_next <= debugtdo_timeout;
- debugtdo_rd_en <= '0';
- resetdebugtdo_strobe <= '0';
- if(bus2_debug_write_enable_out='1') then
- if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
- debug_test_next <= bus2_debug_data_out;
- bus2_debug_write_ack_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1BADDR) then
- ram1b_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- bus2_debug_write_ack_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1CADDR) then
- ram1c_a2_next <= bus2_debug_data_out(RAM_JTAG_REGISTERS_DEPTH-1 downto 0);
- bus2_debug_write_ack_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
- debugtdo_timeout_next <= bus2_debug_data_out(31 downto 0);
- bus2_debug_write_ack_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_ACTIVATE) then
- if( bus2_debug_data_out(0) = '1') then
- debugtdo_activate_strobe <= '1';
- bus2_debug_write_ack_in_next <= '1';
- end if;
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_CONTROLFIFO) then
- if( bus2_debug_data_out(0) = '1') then
- debugtdo_rd_en <= '1';
- bus2_debug_write_ack_in_next <= '1';
- elsif( bus2_debug_data_out(4) = '1') then
- resetdebugtdo_strobe <= '1';
- bus2_debug_write_ack_in_next <= '1';
- end if;
- else
- bus2_debug_unknown_addr_in_next <= '1';
- end if;
- elsif(bus2_debug_read_enable_out='1') then
- if(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TEST) then
- bus2_debug_data_in_next <= debug_test;
- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26CS_STATE) then
- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
- bus2_debug_data_in_next(7 downto 0) <= debug_m26cs_state;
- bus2_debug_dataready_in_next <= '1';
--- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_READ_STATE) then
--- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
--- bus2_debug_data_in_next(7 downto 0) <= read_state_out;
--- bus2_debug_dataready_in_next <= '1';
--- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_M26C_WRITE_STATE) then
--- bus2_debug_data_in_next(31 downto 8) <= (others => '0');
--- bus2_debug_data_in_next(7 downto 0) <= write_state_out;
--- bus2_debug_dataready_in_next <= '1';
--- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_JTAG_DRIVER_STATE) then
--- bus2_debug_data_in_next(31 downto 9) <= (others => '0');
--- bus2_debug_data_in_next(8 downto 0) <= driver_state_out;
--- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_TRIGGER_COUNT) then
- bus2_debug_data_in_next <= std_logic_vector(debug_trigger_counter);
- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_VERSION) then
- bus2_debug_data_in_next <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32));
- bus2_debug_dataready_in_next <= '1';
- bus2_debug_unknown_addr_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1B_DATA) then
- bus2_debug_data_in_next <= ram1b_dout2;
- bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_DATA) then
- bus2_debug_data_in_next <= ram1c_dout2;
- bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_RUN_COUNTER) then
- bus2_debug_data_in_next <= std_logic_vector(ram1c_run_counter);
- bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_RAM1C_CHAIN_STATUS) then
- bus2_debug_data_in_next(31 downto 3+MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0');
- bus2_debug_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= ram1c_chain_status;
- bus2_debug_dataready_in_next <= '1'; -- this isn't safe, but it's for debugging only, would need to wait for RAM after setting the address
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_SAMPLES) then
- bus2_debug_data_in_next(31 downto 0) <= debugtdo_dout;
- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_GETFIFOSTATUS) then
- bus2_debug_data_in_next(0) <= debugtdo_full;
- bus2_debug_data_in_next(1) <= debugtdo_empty;
- bus2_debug_data_in_next(2) <= debugtdo_overflow;
- bus2_debug_data_in_next(3) <= debugtdo_underflow;
- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_DEBUGTDO_TIMEOUT) then
- bus2_debug_data_in_next(31 downto 0) <= debugtdo_timeout_next;
- bus2_debug_dataready_in_next <= '1';
- elsif(bus2_debug_addr_out(4 downto 0) = ADDR_DEBUG_WRONCE_COUNT) then
- bus2_debug_data_in_next(31 downto COUNTER_WIDTHS) <= (others => '0');
- bus2_debug_data_in_next(COUNTER_WIDTHS-1 downto 0) <= std_logic_vector(write_once_count);
- bus2_debug_dataready_in_next <= '1';
- end if;
- end if;
-end process;
-
-buf_bus2_status2_read_ram3b_next <= bus2_status2_read_ram3b;
-BUS2_STATUS2_R : process (bus2_status2_addr_out, bus2_status2_data_out, bus2_status2_read_enable_out, bus2_status2_write_enable_out, bus2_status2_data_in, status2_copy_finished, status2_chain_status, status2_run_counter, bus2_status_addr_out, buf_bus2_status2_read_ram3b, jtag_refresh_active, ram3b_dout2, ram3b_a2_rel_addr, ram3b_a2_base_addr)
-variable bus_addr_int : integer range 0 to 31;
-begin
- bus2_status2_data_in_next <= bus2_status2_data_in;
- bus2_status2_dataready_in_next <= '0';
- bus2_status2_write_ack_in_next <= '0';
- bus2_status2_no_more_data_in_next <= '0';
- bus2_status2_unknown_addr_in_next <= '0';
- bus2_status2_read_ram3b_next <= '0';
- ram3b_a2_base_addr_next <= ram3b_a2_base_addr;
- ram3b_a2_rel_addr_next <= ram3b_a2_rel_addr;
- if(buf_bus2_status2_read_ram3b = '1') then
- bus2_status2_data_in_next <= ram3b_dout2;
- bus2_status2_dataready_in_next <= '1';
- end if;
- if(bus2_status2_read_enable_out='1') then
- -- STATUS register layout: 8 bits/chip
- -- first 32 bits : CRC status
- -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2,
- -- 5: DATA_CHANGED, 6: reserved, 7: reserved
- if(bus2_status2_addr_out(4) = '1') then -- ram3b
- ram3b_a2_rel_addr_next <= bus2_status_addr_out(3 downto 0);
- bus2_status2_read_ram3b_next <= '1';
- -- dataready delayed
- elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_TRIGGERCOUNTER_COPY) then
- bus2_status2_data_in_next <= std_logic_vector(status2_run_counter);
- bus2_status2_dataready_in_next <= '1';
- elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_CHAIN_STATUS_COPY) then
- bus2_status2_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status;
- bus2_status2_data_in_next(31 downto 8) <= (others => '0');
- bus2_status2_dataready_in_next <= '1';
- elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_UPDATING) then
- bus2_status2_data_in_next(0) <= not status2_copy_finished;
- bus2_status2_data_in_next(31 downto 1) <= (others => '0');
- bus2_status2_dataready_in_next <= '1';
- elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
- bus2_status2_data_in_next(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0) <= ram3b_a2_base_addr;
- bus2_status2_data_in_next(31 downto RAM_ERROR_COUNTS_DEPTH-4 ) <= (others => '0');
- bus2_status2_dataready_in_next <= '1';
- elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_STARTED) then
- bus2_status2_data_in_next(0) <= jtag_refresh_active;
- bus2_status2_data_in_next(31 downto 1) <= (others => '0');
- bus2_status2_dataready_in_next <= '1';
- else
- bus2_status2_unknown_addr_in_next <= '1';
- end if;
- end if;
- if(bus2_status2_write_enable_out='1') then
- if(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then
- ram3b_a2_base_addr_next <= bus2_status2_data_out(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0);
- bus2_status2_write_ack_in_next <= '1';
- else
- bus2_status2_unknown_addr_in_next <= '1';
- end if;
- end if;
-end process;
-
---trigger_process : process (trigger_counter)
---begin
- --trigger_counter_next <= trigger_counter + 1;
- --jtag_refresh_start_next <= '0';
- --if(trigger_counter = "00000000000") then
- -- jtag_refresh_start_next <= '1';
- --end if;
---end process;
-
--- reactivate_sensor_wait : process (reactivate_sensor, reactivate_sensor_strobe, removed_chips)
--- begin
--- reactivate_sensor_next <= reactivate_sensor;
--- for i in 0 to MAX_NUMCHIPS-1 loop
--- if(reactivate_sensor_strobe(i) = '1') then
--- reactivate_sensor_next(i) <= '1';
--- elsif(removed_chips(i) = '0') then
--- reactivate_sensor_next(i) <= '0';
--- end if;
--- end loop;
--- end process;
--- deactivate_sensor_wait : process (deactivate_sensor, deactivate_sensor_strobe, removed_chips)
--- begin
--- deactivate_sensor_next <= deactivate_sensor;
--- for i in 0 to MAX_NUMCHIPS-1 loop
--- if(deactivate_sensor_strobe(i) = '1') then
--- deactivate_sensor_next(i) <= '1';
--- elsif(removed_chips(i) = '1') then
--- deactivate_sensor_next(i) <= '0';
--- end if;
--- end loop;
--- end process;
---
--- one_remove_wait : process (debug_one_remove_strobe, removed_strobe)
--- begin
--- debug_one_remove_next <= debug_one_remove;
--- if(removed_strobe = '1') then
--- debug_one_remove_next <= '0';
--- elsif(debug_one_remove_strobe = '1') then
--- debug_one_remove_next <= '1';
--- end if;
--- end process;
-
-debug_m26cs_state_process : process (m26cs_state)
-begin
- case m26cs_state is
- when M26CSS_WAIT_FOR_TRIGGER =>
- debug_m26cs_state_next <= x"00";
- when M26CSS_CHECK_CRC_RAM1A_BEGIN =>
- debug_m26cs_state_next <= x"20";
- when M26CSS_CHECK_CRC_RAM1A_WAIT =>
- debug_m26cs_state_next <= x"21";
- when M26CSS_INIT_RAM1B_BEGIN =>
- debug_m26cs_state_next <= x"22";
- when M26CSS_INIT_RAM1B_WAIT =>
- debug_m26cs_state_next <= x"23";
- when M26CSS_DATA_CHANGED_BEGIN =>
- debug_m26cs_state_next <= x"01";
- when M26CSS_DATA_CHANGED_WAIT =>
- debug_m26cs_state_next <= x"02";
- when M26CSS_BLANK_RAM3A_WAIT =>
- debug_m26cs_state_next <= x"24";
- when M26CSS_JUEC_DATA_CHANGED_BEGIN =>
- debug_m26cs_state_next <= x"03";
- when M26CSS_JUEC_DATA_CHANGED_WAIT =>
- debug_m26cs_state_next <= x"04";
- when M26CSS_COUNT_CHIPS_BEGIN =>
- debug_m26cs_state_next <= x"05";
- when M26CSS_COUNT_CHIPS_WAIT =>
- debug_m26cs_state_next <= x"06";
- when M26CSS_BYPASSREG_BEGIN =>
- debug_m26cs_state_next <= x"07";
- when M26CSS_BYPASSREG_WAIT =>
- debug_m26cs_state_next <= x"08";
- when M26CSS_READ1_BEGIN =>
- debug_m26cs_state_next <= x"09";
- when M26CSS_READ1_WAIT =>
- debug_m26cs_state_next <= x"0a";
- when M26CSS_JUEC_READ_BEGIN =>
- debug_m26cs_state_next <= x"0b";
- when M26CSS_JUEC_READ_WAIT =>
- debug_m26cs_state_next <= x"0c";
- when M26CSS_WRITE1_BEGIN =>
- debug_m26cs_state_next <= x"0d";
- when M26CSS_WRITE1_WAIT =>
- debug_m26cs_state_next <= x"0e";
- when M26CSS_WRITE2_BEGIN =>
- debug_m26cs_state_next <= x"0f";
- when M26CSS_WRITE2_WAIT =>
- debug_m26cs_state_next <= x"10";
- when M26CSS_JUEC_WRITE_BEGIN =>
- debug_m26cs_state_next <= x"11";
- when M26CSS_JUEC_WRITE_WAIT =>
- debug_m26cs_state_next <= x"12";
- when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME =>
- debug_m26cs_state_next <= x"13";
- when M26CSS_STOPPED =>
- debug_m26cs_state_next <= x"14";
- when M26CSS_JUEC_RUN_COUNTER_BEGIN =>
- debug_m26cs_state_next <= x"15";
- when M26CSS_JUEC_RUN_COUNTER_WAIT =>
- debug_m26cs_state_next <= x"16";
- when M26CSS_REQUEST_RESET_BEGIN =>
- debug_m26cs_state_next <= x"17";
- when M26CSS_REQUEST_RESET_WAIT =>
- debug_m26cs_state_next <= x"18";
- when M26CSS_REQUESTED_RESET_WAIT =>
- debug_m26cs_state_next <= x"19";
- when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN =>
- debug_m26cs_state_next <= x"1a";
- when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT =>
- debug_m26cs_state_next <= x"1b";
- when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN =>
- debug_m26cs_state_next <= x"1c";
- when M26CSS_WRITEONCE_INIT_RAM1B_WAIT =>
- debug_m26cs_state_next <= x"1d";
- when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN =>
- debug_m26cs_state_next <= x"1e";
- when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT =>
- debug_m26cs_state_next <= x"1f";
- when M26CSS_WRITEONCE_WRITE1_BEGIN =>
- debug_m26cs_state_next <= x"25";
- when M26CSS_WRITEONCE_WRITE1_WAIT =>
- debug_m26cs_state_next <= x"26";
-
- end case;
-end process;
-
-
-IDLE_OUT <= idle_out_signal;
---write_idle_last_next <= write_idle;
---read_idle_last_next <= read_idle;
---SEQ_have_time_COUNTER : process(CLK_IN)
---begin
--- if(rising_edge(CLK_IN)) then
--- if(RESET_IN ='1') then
--- htcounter <= (others => '0');
--- have_time_for_write <= '0';
--- debug_trigger_counter <= (others => '0');
--- else
--- htcounter <= htcounter_next;
--- have_time_for_write <= have_time_for_write_next;
--- debug_trigger_counter <= debug_trigger_counter_next;
--- end if;
--- end if;
---end process;
-
----- process for counter and to decide when it's still ok to start a jtag write
---COMB_have_time_COUNTER : process(htcounter, OFF_SPILL_IN, debug_trigger_counter)
---begin
--- htcounter_next <= htcounter + 1;
--- debug_trigger_counter_next <= debug_trigger_counter;
--- if(OFF_SPILL_IN = '1') then
--- htcounter_next <= (others => '0');
--- debug_trigger_counter_next <= debug_trigger_counter + 1;
--- end if;
--- if(to_integer(unsigned(htcounter)) >= 8388608) then -- (about 8/100 seconds = 80ms)
--- have_time_for_write_next <= '0';
--- else
--- have_time_for_write_next <= '1';
--- end if;
---end process;
-
-ALL_debugtdo : process( CLK_IN)
-begin
- if(rising_edge(CLK_IN)) then
- debugtdo_timeout <= debugtdo_timeout_next;
- -- COUNTER
- debugtdo_counter <= std_logic_vector(unsigned(debugtdo_counter) + 1);
- -- reset counter in idle/stopped states => counter times the elapsed time since start of m26cs state machine
- -- also clear debugtdo_active
- if(m26cs_state = M26CSS_WAIT_FOR_TRIGGER or m26cs_state = M26CSS_STOPPED) then
- debugtdo_counter <= (others => '0');
- if(debugtdo_ran = '1') then
- debugtdo_active <= '0';
- end if;
- debugtdo_ran <= '0';
- else
- debugtdo_ran <= '1';
- end if;
- if(debugtdo_activate_strobe = '1') then
- debugtdo_active <= '1';
- end if;
-
- -- RESET
- if(RESET_IN= '1') then
- debugtdo_counter <= (others => '0');
- debugtdo_active <= '0';
- debugtdo_ran <= '0';
- end if;
- end if;
-end process;
-end architecture;
jspc29 / jtag_mvd.git / commitdiff