--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M20E
+PartName=LFE2M20E-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=4.4
+ModuleName=lattice_ecp2m_fifo_16bit_dualport
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2008
+Time=18:06:47
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=18
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
entity trb_net16_addresses is
generic(
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := x"1000_2000_3654_4876_5bcd_6ef1"
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"
);
port(
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
API_DATAREADY_IN : in std_logic;
API_READ_OUT : out std_logic;
RAM_DATA_IN : in std_logic_vector(15 downto 0);
end entity;
architecture trb_net16_addresses_arch of trb_net16_addresses is
- component trb_net_ram_16x8_dp is
+ component trb_net_ram_16x16_dp is
generic(
INIT0 : std_logic_vector(15 downto 0) := x"0000";
INIT1 : std_logic_vector(15 downto 0) := x"0000";
INIT4 : std_logic_vector(15 downto 0) := x"0000";
INIT5 : std_logic_vector(15 downto 0) := x"0000";
INIT6 : std_logic_vector(15 downto 0) := x"0000";
- INIT7 : std_logic_vector(15 downto 0) := x"0000"
+ INIT7 : std_logic_vector(15 downto 0) := x"0000";
+ INIT8 : std_logic_vector(15 downto 0) := x"12A0";
+ INIT9 : std_logic_vector(15 downto 0) := x"23b1";
+ INITA : std_logic_vector(15 downto 0) := x"34c2";
+ INITB : std_logic_vector(15 downto 0) := x"49d3";
+ INITC : std_logic_vector(15 downto 0) := x"56e5";
+ INITD : std_logic_vector(15 downto 0) := x"67d5";
+ INITE : std_logic_vector(15 downto 0) := x"7818";
+ INITF : std_logic_vector(15 downto 0) := x"8927"
);
port(
CLK : in std_logic;
wr1 : in std_logic;
- a1 : in std_logic_vector(2 downto 0);
+ a1 : in std_logic_vector(3 downto 0);
dout1 : out std_logic_vector(15 downto 0);
din1 : in std_logic_vector(15 downto 0);
- a2 : in std_logic_vector(2 downto 0);
+ a2 : in std_logic_vector(3 downto 0);
dout2 : out std_logic_vector(15 downto 0)
);
end component;
-signal write_ADDRESS : std_logic;
-signal ram_read_addr : std_logic_vector(2 downto 0);
+signal ram_read_addr : std_logic_vector(3 downto 0);
signal ram_read_dout : std_logic_vector(15 downto 0);
signal matching_counter : std_logic_vector(2 downto 0);
-signal ram_read_addr1 : std_logic_vector(2 downto 0);
-signal ram_read_addr2 : std_logic_vector(2 downto 0);
+signal ram_read_addr1 : std_logic_vector(3 downto 0);
+signal ram_read_addr2 : std_logic_vector(3 downto 0);
+signal last_ram_read_addr2 : std_logic_vector(3 downto 0);
+signal buf_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal buf_API_READ_OUT : std_logic;
+signal buf_API_SEND_OUT : std_logic;
signal read_UNIQUE_ID : std_logic;
+signal recv_set_address : std_logic;
-type state_t is (IDLE, SEND1, SEND2, SEND3);
-signal next_state, state : state_t;
+signal next_state, state : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-signal next_read_uid_1, read_uid_1 : std_logic;
-signal next_read_uid_2, read_uid_2 : std_logic;
+type sending_state_t is (sending_idle, send_uid_1, send_uid_2, send_ack_address);
+signal sending_state : sending_state_t;
+signal buf_ADDRESS_OUT : std_logic_vector(15 downto 0);
begin
begin
if rising_edge(CLK) then
if RESET = '1' then
- ADDRESS_OUT <= INIT_ADDRESS;
+ buf_ADDRESS_OUT <= INIT_ADDRESS;
ram_read_addr1 <= (others => '0');
matching_counter <= (others => '0');
- else
+ sending_state <= sending_idle;
+ elsif CLK_EN = '1' then
buf_API_READ_OUT <= '1';
- write_ADDRESS <= '0';
ADDRESS_REJECTED <= '0';
read_UNIQUE_ID <= '0';
+ recv_set_address <= '0';
+
+ --control sending state
+ if buf_API_SEND_OUT = '0' then
+ sending_state <= sending_idle;
+ end if;
+ if API_READ_IN = '1' and sending_state = send_uid_1 and buf_API_PACKET_NUM_OUT = c_F3 then
+ sending_state <= send_uid_2;
+ end if;
+
+ --read incoming data
if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' then
buf_API_READ_OUT <= '0';
- ram_read_addr1 <= ram_read_addr1 + 1;
- if API_DATA_IN = READ_ID then
- read_UNIQUE_ID <= '1';
+ if API_PACKET_NUM_IN = c_F0 and read_UNIQUE_ID = '0' and recv_set_address = '0' then
+ case API_DATA_IN is
+ when READ_ID =>
+ sending_state <= send_uid_1;
+ ram_read_addr1 <= "0000";
+ when SET_ADDRESS => recv_set_address <= '1';
+ when others => null;
+ end case;
end if;
- if API_DATA_IN = ram_read_dout then
- matching_counter <= matching_counter + 1;
- end if;
- if ram_read_addr1 = "101" then
- matching_counter <= "000";
- ram_read_addr1 <= "000";
- if matching_counter = "101" then
- ADDRESS_OUT <= API_DATA_IN;
- write_ADDRESS <= '1';
- else
- ADDRESS_REJECTED <= '1';
+ if recv_set_address = '1' then
+ ram_read_addr1 <= ram_read_addr1 + 1;
+ if API_DATA_IN = ram_read_dout then
+ matching_counter <= matching_counter + 1;
+ end if;
+ if ram_read_addr1 = "0101" then
+ matching_counter <= "000";
+ ram_read_addr1 <= "0000";
+ recv_set_address <= '0';
+ if matching_counter = "100" then
+ buf_ADDRESS_OUT <= API_DATA_IN;
+ sending_state <= send_ack_address;
+ else
+ ADDRESS_REJECTED <= '1';
+ end if;
end if;
end if;
end if;
- if (read_uid_1 or read_uid_2 or read_UNIQUE_ID) = '1' then
- ram_read_addr1 <= "000";
+ if sending_state /= sending_idle then
+ ram_read_addr1 <= "0000";
end if;
end if;
end if;
end process;
- send_ack : process(write_ADDRESS, state, API_READ_IN, ram_read_dout, read_uid_1, read_uid_2, read_UNIQUE_ID)
+ send_ack : process(state, API_READ_IN, ram_read_dout, read_UNIQUE_ID, last_ram_read_addr2, sending_state)
begin
next_state <= state;
- API_DATAREADY_OUT <= '0';
- API_PACKET_NUM_OUT <= c_F0;
API_DATA_OUT <= ram_read_dout;
- ram_read_addr2 <= "000";
- next_read_uid_1 <= read_uid_1;
- next_read_uid_2 <= read_uid_2;
+ ram_read_addr2 <= last_ram_read_addr2;
+ if state = c_H0 then
+ API_DATAREADY_OUT <= '0';
+ else
+ API_DATAREADY_OUT <= '1';
+ end if;
+ if sending_state /= sending_idle then
+ buf_API_SEND_OUT <= '1';
+ else
+ buf_API_SEND_OUT <= '0';
+ end if;
+ buf_API_PACKET_NUM_OUT <= state;
+
case state is
- when IDLE =>
- API_SEND_OUT <= '0';
- if write_ADDRESS = '1' then
- ram_read_addr2 <= "111";
- next_state <= SEND1;
- elsif read_UNIQUE_ID = '1' then
- ram_read_addr2 <= "001";
- next_read_uid_1 <= '1';
- next_state <= SEND1;
+ when c_H0 => --idle
+ if sending_state = send_ack_address then
+ ram_read_addr2 <= "0101";
+ next_state <= c_F0;
+ elsif sending_state = send_uid_1 then
+ ram_read_addr2 <= "0000";
+ next_state <= c_F0;
end if;
- when SEND1 =>
- API_SEND_OUT <= '1';
- API_DATAREADY_OUT <= '1';
- API_PACKET_NUM_OUT <= c_F0;
- if read_uid_1 = '1' then
- ram_read_addr2 <= "001";
- elsif read_uid_2 = '1' then
- ram_read_addr2 <= "100";
- else
- ram_read_addr2 <= "111";
- end if;
-
+ when c_F0 =>
if API_READ_IN = '1' then
- if read_uid_1 = '1' then
- ram_read_addr2 <= "010";
- else
- ram_read_addr2 <= "101";
- end if;
- next_state <= SEND2;
+ case sending_state is
+ when send_uid_1 => ram_read_addr2 <= "0001";
+ when send_uid_2 => ram_read_addr2 <= "0110";
+ when send_ack_address => ram_read_addr2 <= "0110";
+ when sending_idle => null;
+ end case;
+ next_state <= c_F1;
end if;
- when SEND2 =>
- API_SEND_OUT <= '1';
- API_DATAREADY_OUT <= '1';
- API_PACKET_NUM_OUT <= c_F1;
- if read_uid_1 = '1' then
- ram_read_addr2 <= "010";
- else
- ram_read_addr2 <= "101";
+ when c_F1 =>
+ if API_READ_IN = '1' then
+ case sending_state is
+ when send_uid_1 => ram_read_addr2 <= "0010";
+ when send_uid_2 => ram_read_addr2 <= "0111";
+ when send_ack_address => ram_read_addr2 <= "0111";
+ when sending_idle => null;
+ end case;
+ next_state <= c_F2;
end if;
+ when c_F2 =>
if API_READ_IN = '1' then
- if read_uid_1 = '1' then
- ram_read_addr2 <= "011";
- else
- ram_read_addr2 <= "110";
- end if;
- next_state <= SEND3;
+ case sending_state is
+ when send_uid_1 => ram_read_addr2 <= "0011";
+ when send_uid_2 => ram_read_addr2 <= "1111";
+ when send_ack_address => ram_read_addr2 <= "1111";
+ when sending_idle => null;
+ end case;
+ next_state <= c_F3;
end if;
- when SEND3 =>
- API_SEND_OUT <= '1';
- API_DATAREADY_OUT <= '1';
- API_PACKET_NUM_OUT <= c_F2;
- if read_uid_1 = '1' then
- ram_read_addr2 <= "011";
- else
- ram_read_addr2 <= "110";
- end if;
+ when c_F3 =>
if API_READ_IN = '1' then
- if read_uid_1 = '1' then
- next_state <= SEND1;
- ram_read_addr2 <= "100";
- next_read_uid_1 <= '0';
- next_read_uid_2 <= '1';
- else
- next_state <= IDLE;
- ram_read_addr2 <= "000";
- next_read_uid_2 <= '0';
- end if;
+ case sending_state is
+ when send_uid_1 =>
+ ram_read_addr2 <= "0100";
+ next_state <= c_F0;
+ when send_uid_2 =>
+ ram_read_addr2 <= "1111";
+ buf_API_SEND_OUT <= '0';
+ next_state <= c_H0;
+ when send_ack_address =>
+ ram_read_addr2 <= "1111";
+ buf_API_SEND_OUT <= '0';
+ next_state <= c_H0;
+ when sending_idle => null;
+ end case;
end if;
+ when others => null;
end case;
end process;
begin
if rising_edge(CLK) then
if RESET = '1' then
- read_uid_1 <= '0';
- read_uid_2 <= '0';
- else
+ state <= c_H0;
+ last_ram_read_addr2 <= "0000";
+ elsif CLK_EN = '1' then
state <= next_state;
- read_uid_1 <= next_read_uid_1;
- read_uid_2 <= next_read_uid_2;
+ last_ram_read_addr2 <= ram_read_addr2;
end if;
- -- buf_API_READ_OUT <= next_API_READ_OUT;
end if;
end process;
- STAT_RAM : trb_net_ram_16x8_dp
+ STAT_RAM : trb_net_ram_16x16_dp
generic map(
- INIT0 => SET_ADDRESS & INIT_UNIQUE_ID(71 downto 64),
- INIT1 => INIT_UNIQUE_ID(15 downto 0),
- INIT2 => INIT_UNIQUE_ID(31 downto 16),
- INIT3 => INIT_UNIQUE_ID(47 downto 32),
- INIT4 => INIT_UNIQUE_ID(63 downto 48),
- INIT5 => INIT_UNIQUE_ID(79 downto 64),
- INIT6 => INIT_UNIQUE_ID(95 downto 80),
- INIT7 => ACK_ADDRESS
+ INIT0 => INIT_UNIQUE_ID(15 downto 0),
+ INIT1 => INIT_UNIQUE_ID(31 downto 16),
+ INIT2 => INIT_UNIQUE_ID(47 downto 32),
+ INIT3 => INIT_UNIQUE_ID(63 downto 48),
+ INIT4 => INIT_ENDPOINT_ID,
+ INIT5 => ACK_ADDRESS,
+ INIT6 => INIT_BOARD_INFO(15 downto 0),
+ INIT7 => INIT_BOARD_INFO(31 downto 16),
+ INIT8 => SET_ADDRESS,
+ INIT9 => x"0000",
+ INITA => x"0000",
+ INITB => x"0000",
+ INITC => x"0000",
+ INITD => x"0000",
+ INITE => x"0000",
+ INITF => x"0000" --F fixed to 0!
)
port map(
CLK => CLK,
wr1 => RAM_WR_IN,
- a1 => RAM_ADDR_IN,
+ a1(2 downto 0) => RAM_ADDR_IN,
+ a1(3) => '0',
din1 => RAM_DATA_IN,
dout1 => RAM_DATA_OUT,
a2 => ram_read_addr,
);
API_READ_OUT <= buf_API_READ_OUT;
+API_SEND_OUT <= buf_API_SEND_OUT;
+API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
+ADDRESS_OUT <= buf_ADDRESS_OUT;
end architecture;
\ No newline at end of file
RESET : in std_logic;
CLK_EN : in std_logic;
API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
API_DATAREADY_IN : in std_logic;
API_READ_OUT : out std_logic;
RAM_DATA_IN : in std_logic_vector(15 downto 0);
signal buf_API_READ_OUT : std_logic;
signal buf_API_SEND_OUT, next_API_SEND_OUT : std_logic;
- signal buf_API_PACKET_NUM_OUT, next_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_API_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal buf_API_DATA_OUT, next_API_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal buf_API_SHORT_TRANSFER_OUT, next_API_SHORT_TRANSFER_OUT : std_logic;
signal buf_API_DATAREADY_OUT, next_API_DATAREADY_OUT : std_logic;
signal rom_read_dout : std_logic_vector(15 downto 0);
signal length, next_length : std_logic_vector(15 downto 0);
signal dont_understand, next_dont_understand : std_logic;
+ signal packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal next_packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
begin
RESET => RESET,
CLK_EN => CLK_EN,
API_DATA_IN => API_DATA_IN,
+ API_PACKET_NUM_IN => API_PACKET_NUM_IN,
API_DATAREADY_IN => ADR_DATAREADY_IN,
API_READ_OUT => ADR_READ_OUT,
API_DATA_OUT => ADR_DATA_OUT,
fsm : process(current_state,
API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN, API_RUN_IN,
HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation,
- buf_API_SEND_OUT, buf_API_PACKET_NUM_OUT, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
+ buf_API_SEND_OUT, next_packet_counter, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT,
REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN,
buf_DAT_DATA_OUT, buf_DAT_ADDR_OUT, DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED,
ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT, length, dont_understand,
buf_API_READ_OUT <= '1';
next_API_SEND_OUT <= buf_API_SEND_OUT;
next_API_DATAREADY_OUT <= '0';
- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT;
next_API_DATA_OUT <= buf_API_DATA_OUT;
next_API_SHORT_TRANSFER_OUT <= buf_API_SHORT_TRANSFER_OUT;
next_operation <= saved_operation;
when HEADER_RECV => --read and save HDR
if API_DATAREADY_IN = '1' then
- if API_PACKET_NUM_IN = c_F0 then
- next_HDR_F0 <= API_DATA_IN;
- end if;
- if API_PACKET_NUM_IN = c_F1 then
- next_HDR_F1 <= API_DATA_IN;
- end if;
- if API_PACKET_NUM_IN = c_F2 then
- next_HDR_F2 <= API_DATA_IN;
- end if;
- if API_PACKET_NUM_IN = c_F3 then
- next_HDR_F3 <= API_DATA_IN;
- next_API_PACKET_NUM_OUT <= "011";
- case API_DATA_IN(3 downto 0) is
- when c_read_register_type => next_state <= ONE_READ;
- when c_write_register_type => next_state <= ONE_WRITE;
- when c_read_multiple_type => next_state <= MEM_START_READ;
- when c_write_multiple_type => next_state <= MEM_START_WRITE;
- when c_network_control_type => next_state <= ADDRESS_RECV;
- when others =>
- next_state <= SEND_REPLY_SHORT_TRANSFER;
- next_dont_understand <= '1';
- end case;
- next_operation <= API_DATA_IN(3 downto 0);
- end if;
+ case API_PACKET_NUM_IN is
+ when c_F0 =>
+ next_HDR_F0 <= API_DATA_IN;
+ when c_F1 =>
+ next_HDR_F1 <= API_DATA_IN;
+ when c_F2 =>
+ next_HDR_F2 <= API_DATA_IN;
+ when c_F3 =>
+ next_HDR_F3 <= API_DATA_IN;
+ case API_DATA_IN(3 downto 0) is
+ when c_read_register_type => next_state <= ONE_READ;
+ when c_write_register_type => next_state <= ONE_WRITE;
+ when c_read_multiple_type => next_state <= MEM_START_READ;
+ when c_write_multiple_type => next_state <= MEM_START_WRITE;
+ when c_network_control_type => next_state <= ADDRESS_RECV;
+ when others =>
+ next_state <= SEND_REPLY_SHORT_TRANSFER;
+ next_dont_understand <= '1';
+ end case;
+ next_operation <= API_DATA_IN(3 downto 0);
+ when others => null;
+ end case;
end if;
when ADDRESS_RECV =>
ADR_READ_IN <= '0';
if ADR_REJECTED = '1' then
next_state <= SEND_REPLY_SHORT_TRANSFER;
- end if;
- if ADR_DATAREADY_OUT = '1' then
+ elsif ADR_DATAREADY_OUT = '1' then
next_state <= ADDRESS_ACK;
end if;
when ADDRESS_ACK =>
ADR_READ_IN <= API_READ_IN;
- next_API_SEND_OUT <= '1';
+ next_API_SEND_OUT <= ADR_SEND_OUT;
next_API_DATAREADY_OUT <= ADR_DATAREADY_OUT;
next_API_DATA_OUT <= ADR_DATA_OUT;
- next_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
- if ADR_SEND_OUT = '0' and API_READ_IN = '1' then
+ if ADR_SEND_OUT = '0' then
next_state <= SEND_REPLY_DATA_finish;
end if;
next_state <= SEND_REPLY_DATA_finish;
when REG_WRITE =>
- case API_PACKET_NUM_IN is
- when c_F1 =>
- next_Reg_high <= API_DATA_IN;
- when c_F2 =>
- next_Reg_low <= API_DATA_IN;
- if or_all(address(15 downto 8)) = '0' then
- if address(7 downto 6) = "11" then
- next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
+ if API_DATAREADY_IN = '1' then
+ case API_PACKET_NUM_IN is
+ when c_F1 =>
+ next_Reg_high <= API_DATA_IN;
+ when c_F2 =>
+ next_Reg_low <= API_DATA_IN;
+ if or_all(address(15 downto 8)) = '0' then
+ if address(7 downto 6) = "11" then
+ next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
+ else
+ next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
+ end if;
+ next_state <= REG_READ;
else
- next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
+ next_DAT_WRITE_ENABLE_OUT <= '1';
+ next_state <= DAT_START_READ;
end if;
- next_state <= REG_READ;
- else
- next_DAT_WRITE_ENABLE_OUT <= '1';
- next_state <= DAT_START_READ;
- end if;
- when others => null;
- end case;
+ when others => null;
+ end case;
+ end if;
when REG_READ =>
next_API_SEND_OUT <= '1';
- if API_READ_IN = '0' then
- next_API_DATAREADY_OUT <= '0';
- else
- next_API_DATAREADY_OUT <= '1';
- if buf_API_PACKET_NUM_OUT = c_F3 then
- next_API_PACKET_NUM_OUT <= c_F0;
+ next_API_DATAREADY_OUT <= '1';
+ case next_packet_counter is
+ when c_F0 =>
next_API_DATA_OUT <= address;
- elsif buf_API_PACKET_NUM_OUT = c_F0 then
- next_API_PACKET_NUM_OUT <= c_F1;
+ when c_F1 =>
if address(7 downto 6) = "01" then
next_API_DATA_OUT <= rom_read_dout;
rom_read_addr <= address(1 downto 0) & '0';
else --if address(5) = '1' then
next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REGISTER_WIDTH+31 downto regnum_cCTRL*c_REGIO_REGISTER_WIDTH+16);
end if;
- elsif buf_API_PACKET_NUM_OUT = c_F1 then
- next_API_PACKET_NUM_OUT <= c_F2;
+ when c_F2 =>
if address(7 downto 6) = "01" then
next_API_DATA_OUT <= rom_read_dout;
elsif address(7 downto 6) = "10" then
else --if address(5) = '1' then
next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REGISTER_WIDTH+15 downto regnum_cCTRL*c_REGIO_REGISTER_WIDTH);
end if;
- elsif buf_API_PACKET_NUM_OUT = c_F2 then
- next_API_PACKET_NUM_OUT <= c_F3;
+ when c_F3 =>
next_API_DATA_OUT <= (others => '0');
- next_state <= SEND_REPLY_DATA_finish;
- end if;
- end if;
+ if API_READ_IN = '1' then
+ next_state <= SEND_REPLY_DATA_finish;
+ end if;
+ when others =>
+ next_API_DATAREADY_OUT <= '0';
+ end case;
+
when MEM_START_READ =>
if USE_DAT_PORT = c_NO then
next_state <= SEND_REPLY_SHORT_TRANSFER;
else
if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F1 and API_DATAREADY_IN = '1' then
next_length <= API_DATA_IN;
+ next_DAT_READ_ENABLE_OUT <= '1';
next_state <= MEM_READ;
elsif API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then
next_address <= API_DATA_IN;
end if;
end if;
end if;
- when MEM_READ => --needs a review
- next_state <= SEND_REPLY_DATA_finish;
--- if buf_API_PACKET_NUM_OUT = c_F3 and API_READ_IN = '1' then
--- if length = 0 or DAT_NO_MORE_DATA_IN = '1' then
--- next_state <= SEND_REPLY_DATA_finish;
--- else
--- next_DAT_READ_ENABLE_OUT <= '1';
--- next_API_SEND_OUT <= '1';
--- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
--- end if;
--- elsif buf_API_PACKET_NUM_OUT = c_F0_next then
--- if DAT_DATAREADY_IN = '1' then
--- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
--- next_API_DATA_OUT <= address;
--- next_API_DATAREADY_OUT <= '1';
--- end if;
--- elsif buf_API_PACKET_NUM_OUT = c_F1_next and API_READ_IN = '1' then
--- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
--- next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
--- next_API_DATAREADY_OUT <= '1';
--- elsif buf_API_PACKET_NUM_OUT = c_F2_next and API_READ_IN = '1' then
--- next_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT+1;
--- next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
--- next_API_DATAREADY_OUT <= '1';
--- next_length <= length-1;
--- end if;
+ when MEM_READ =>
+ next_API_DATAREADY_OUT <= '1';
+ case next_packet_counter is
+ when c_F0 =>
+ if length = 0 or DAT_NO_MORE_DATA_IN = '1' then
+ next_state <= SEND_REPLY_DATA_finish;
+ next_API_DATAREADY_OUT <= '0';
+ else
+ next_API_SEND_OUT <= '1';
+ next_API_DATA_OUT <= address;
+ end if;
+ when c_F1 =>
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
+ when c_F2 =>
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
+ when c_F3 =>
+ next_length <= length-1;
+ next_API_DATA_OUT <= (others => '0');
+ if length > 1 and API_READ_IN = '1' then
+ next_DAT_READ_ENABLE_OUT <= '1';
+ end if;
+ when others => null;
+ end case;
when MEM_START_WRITE =>
if API_PACKET_NUM_IN = c_F0 and API_TYP_IN = TYPE_DAT and API_DATAREADY_IN = '1' then
next_dont_understand <= '1';
elsif API_DATAREADY_IN = '1' then
case API_PACKET_NUM_IN is
- when c_F1 => next_Reg_high <= API_DATA_IN;
+ when c_F1 =>
+ next_Reg_high <= API_DATA_IN;
when c_F2 =>
next_Reg_low <= API_DATA_IN;
next_DAT_WRITE_ENABLE_OUT <= '1';
end if;
when DAT_START_READ =>
- next_DAT_READ_ENABLE_OUT <= '1';
- next_state <= DAT_READ;
+ if DAT_DATAREADY_IN = '1' then
+ next_state <= DAT_READ;
+ end if;
when DAT_READ =>
- if DAT_DATAREADY_IN = '1' and API_READ_IN = '1' then
- next_API_PACKET_NUM_OUT <= c_F0;
- next_API_DATA_OUT <= address;
- next_API_SEND_OUT <= '1';
- next_API_DATAREADY_OUT <= '1';
- end if;
- if buf_API_PACKET_NUM_OUT = c_F0 and API_READ_IN = '1' then
- next_API_PACKET_NUM_OUT <= c_F1;
- next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
- next_API_DATAREADY_OUT <= '1';
- elsif buf_API_PACKET_NUM_OUT = c_F1 and API_READ_IN = '1' then
- next_API_PACKET_NUM_OUT <= c_F0;
- next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
- next_API_DATAREADY_OUT <= '1';
- next_state <= SEND_REPLY_DATA_finish;
- end if;
+ next_API_DATAREADY_OUT <= '1';
+ case next_packet_counter is
+ when c_F0 => next_API_DATA_OUT <= address;
+ when c_F1 => next_API_DATA_OUT <= buf_DAT_DATA_IN(31 downto 16);
+ when c_F2 =>
+ next_API_DATA_OUT <= buf_DAT_DATA_IN(15 downto 0);
+ when c_F3 =>
+ next_API_DATA_OUT <= (others => '0');
+ if API_READ_IN = '1' then
+ next_state <= SEND_REPLY_DATA_finish;
+ end if;
+ when others => null;
+ end case;
when others =>
next_state <= IDLE;
if RESET = '1' then
current_state <= IDLE;
buf_API_SEND_OUT <= '0';
- buf_API_DATAREADY_OUT <= '0';
- buf_API_PACKET_NUM_OUT <= "011";
buf_DAT_READ_ENABLE_OUT <= '0';
buf_DAT_WRITE_ENABLE_OUT <= '0';
- buf_API_DATA_OUT <= (others => '0');
- buf_API_PACKET_NUM_OUT <= (others => '0');
saved_operation <= "0000";
saved_Reg_high <= (others => '0');
saved_Reg_low <= (others => '0');
HDR_F2 <= next_HDR_F2;
HDR_F3 <= next_HDR_F3;
buf_API_SEND_OUT <= next_API_SEND_OUT;
- buf_API_DATAREADY_OUT <= next_API_DATAREADY_OUT;
- buf_API_PACKET_NUM_OUT <= next_API_PACKET_NUM_OUT;
- buf_API_DATA_OUT <= next_API_DATA_OUT;
buf_API_SHORT_TRANSFER_OUT <= next_API_SHORT_TRANSFER_OUT;
address <= next_address;
saved_Reg_high <= next_Reg_high;
end if;
end process;
+
+ reg_packet_counter : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ packet_counter <= c_F0;
+ else
+ packet_counter <= next_packet_counter;
+ end if;
+ end if;
+ end process;
+
+
+ next_packet_counter_proc : process(API_READ_IN, buf_API_DATAREADY_OUT, packet_counter)
+ begin
+ if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then
+ if packet_counter = "011" then
+ next_packet_counter <= "000";
+ else
+ next_packet_counter <= packet_counter + 1;
+ end if;
+ else
+ next_packet_counter <= packet_counter;
+ end if;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ buf_API_DATAREADY_OUT <= next_API_DATAREADY_OUT;
+ if current_state = ADDRESS_ACK then
+ buf_API_PACKET_NUM_OUT <= ADR_PACKET_NUM_OUT;
+ else
+ buf_API_PACKET_NUM_OUT <= next_packet_counter;
+ end if;
+ buf_API_DATA_OUT <= next_API_DATA_OUT;
+ end if;
+ end process;
+
+
gen_regout : for i in 0 to 2**(NUM_CTRL_REGS)-1 generate
gen_regoutff1 : for j in i*c_REGIO_REGISTER_WIDTH to (i+1)*c_REGIO_REGISTER_WIDTH-1 generate
gen_regoutff : if USED_CTRL_REGS(i) = '1' and USED_CTRL_BITMASK(j) = '1' generate
COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
STAT(3 downto 0) <= state_bits;
- STAT(6 downto 4) <= next_API_PACKET_NUM_OUT;
+ STAT(6 downto 4) <= b_API_PACKET_NUM_OUT;
STAT(7) <= next_API_DATAREADY_OUT;
STAT(15 downto 8) <= next_API_DATA_OUT(7 downto 0);
STAT(31 downto 16) <= (others => '0');
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_ram_16x16_dp is
+ generic(
+ INIT0 : std_logic_vector(15 downto 0) := x"0000";
+ INIT1 : std_logic_vector(15 downto 0) := x"0000";
+ INIT2 : std_logic_vector(15 downto 0) := x"0000";
+ INIT3 : std_logic_vector(15 downto 0) := x"0000";
+ INIT4 : std_logic_vector(15 downto 0) := x"0000";
+ INIT5 : std_logic_vector(15 downto 0) := x"0000";
+ INIT6 : std_logic_vector(15 downto 0) := x"0000";
+ INIT7 : std_logic_vector(15 downto 0) := x"0000";
+ INIT8 : std_logic_vector(15 downto 0) := x"12A0";
+ INIT9 : std_logic_vector(15 downto 0) := x"23b1";
+ INITA : std_logic_vector(15 downto 0) := x"34c2";
+ INITB : std_logic_vector(15 downto 0) := x"49d3";
+ INITC : std_logic_vector(15 downto 0) := x"56e5";
+ INITD : std_logic_vector(15 downto 0) := x"67d5";
+ INITE : std_logic_vector(15 downto 0) := x"7818";
+ INITF : std_logic_vector(15 downto 0) := x"8927"
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(3 downto 0);
+ dout1 : out std_logic_vector(15 downto 0);
+ din1 : in std_logic_vector(15 downto 0);
+ a2 : in std_logic_vector(3 downto 0);
+ dout2 : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture trb_net_ram_16x16_dp_arch of trb_net_ram_16x16_dp is
+ type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
+ SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7,
+ INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF);
+begin
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if wr1 = '1' then
+ ram((conv_integer(a1))) <= din1;
+ end if;
+ dout1 <= ram(conv_integer(a1));
+ dout2 <= ram(conv_integer(a2));
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_rom_16x16 is
+ generic(
+ INIT0 : std_logic_vector(15 downto 0) := x"12A0";
+ INIT1 : std_logic_vector(15 downto 0) := x"23b1";
+ INIT2 : std_logic_vector(15 downto 0) := x"34c2";
+ INIT3 : std_logic_vector(15 downto 0) := x"49d3";
+ INIT4 : std_logic_vector(15 downto 0) := x"56e5";
+ INIT5 : std_logic_vector(15 downto 0) := x"67d5";
+ INIT6 : std_logic_vector(15 downto 0) := x"7818";
+ INIT7 : std_logic_vector(15 downto 0) := x"8927";
+ INIT8 : std_logic_vector(15 downto 0) := x"12A0";
+ INIT9 : std_logic_vector(15 downto 0) := x"23b1";
+ INITA : std_logic_vector(15 downto 0) := x"34c2";
+ INITB : std_logic_vector(15 downto 0) := x"49d3";
+ INITC : std_logic_vector(15 downto 0) := x"56e5";
+ INITD : std_logic_vector(15 downto 0) := x"67d5";
+ INITE : std_logic_vector(15 downto 0) := x"7818";
+ INITF : std_logic_vector(15 downto 0) := x"8927"
+ );
+ port(
+ CLK : in std_logic;
+ a : in std_logic_vector(3 downto 0);
+ dout : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture trb_net_rom_16x16_arch of trb_net_rom_16x16 is
+ type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
+ SIGNAL rom : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7, INIT8, INIT9, INITA, INITB, INITC, INITD, INITE, INITF);
+begin
+ rom(0) <= INIT0;
+ rom(1) <= INIT1;
+ rom(2) <= INIT2;
+ rom(3) <= INIT3;
+ rom(4) <= INIT4;
+ rom(5) <= INIT5;
+ rom(6) <= INIT6;
+ rom(7) <= INIT7;
+ rom(8) <= INIT8;
+ rom(9) <= INIT9;
+ rom(10) <= INITA;
+ rom(11) <= INITB;
+ rom(12) <= INITC;
+ rom(13) <= INITD;
+ rom(14) <= INITE;
+ rom(15) <= INITF;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ dout <= rom(conv_integer(a));
+ end if;
+ end process;
+
+end architecture;
\ No newline at end of file
--command definitions
constant LINK_STARTUP_WORD : std_logic_vector(15 downto 0) := x"e110";
- constant SET_ADDRESS : std_logic_vector( 7 downto 0) := x"AD";
- constant ACK_ADDRESS : std_logic_vector(15 downto 0) := x"AADD";
- constant READ_ID : std_logic_vector(15 downto 0) := x"5B1D";
+ constant SET_ADDRESS : std_logic_vector(15 downto 0) := x"5EAD";
+ constant ACK_ADDRESS : std_logic_vector(15 downto 0) := x"ACAD";
+ constant READ_ID : std_logic_vector(15 downto 0) := x"5E1D";
--common registers
--maximum: 4, because of regio implementation
jspc29 / trbnet.git / commitdiff