-- RT(16 downto 1) <= (others => '0');
+ TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+ begin
+ TX_DIS(synch_fsm_state+1) <= '0';
+ end generate LOK_STATUS_DIOD_EN;
+
+ TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
+ begin
+ WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
+ TX_DIS(16-not_connected) <= '1';
+ end generate WHEN_NOT_ALL_EN;
+ end generate LOK_STATUS_DIOD_DIS;
+
+---------------------------------------------------------------------------
+-- setting LED
+---------------------------------------------------------------------------
LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
begin
LOK(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
- TX_DIS(synch_fsm_state+1) <= '0';
end generate LOK_STATUS_DIOD_EN;
- LOK_STATUS_DIOD_DIS : for not_conected in 0 to 16-HOW_MANY_CHANNELS-1 generate
+
+ LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
begin
WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
- LOK(16-not_conected) <= '1';
- TX_DIS(16-not_conected) <= '1';
+ LOK(16-not_connected) <= '1';
end generate WHEN_NOT_ALL_EN;
end generate LOK_STATUS_DIOD_DIS;
+
IPLL <= '0';
OPLL <= '0';
DBAD <= ADO_TTL(11);
DGOOD <= '1';
DINT <= '0';
DWAIT <= ADO_TTL(0);
+
CV_COUNTERaaa: process (LVDS_CLK_200P, ADO_TTL(0))
begin
if rising_edge(LVDS_CLK_200P) then -- rising clock edge