removed unnecessary register stages

diff --git a/gbe_trb/base/gbe_med_interface_single_5G.vhd b/gbe_trb/base/gbe_med_interface_single_5G.vhd
index 1a1726e43f2a41740b62f000e4890dc52b8525f5..931aee66a16a199e526b187a9a056061804c2889 100644 (file)
--- a/gbe_trb/base/gbe_med_interface_single_5G.vhd
+++ b/gbe_trb/base/gbe_med_interface_single_5G.vhd
@@ -204,15 +204,16 @@ architecture RTL of gbe_med_interface_single_5G is
 
   signal sd_rx_clk                                : std_logic;
   signal sd_tx_clk                                : std_logic;
-  signal sd_tx_kcntl_q, sd_tx_kcntl               : std_logic_vector(0 downto 0);
-  signal sd_tx_data_q, sd_tx_data                 : std_logic_vector(7 downto 0);
+  signal sd_tx_kcntl                              : std_logic_vector(0 downto 0);
+  signal sd_tx_data                               : std_logic_vector(7 downto 0);
   signal xmit                                     : std_logic_vector(0 downto 0);
-  signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(0 downto 0);
-  signal sd_rx_data, sd_rx_data_q                 : std_logic_vector(7 downto 0);
-  signal sd_rx_kcntl, sd_rx_kcntl_q               : std_logic_vector(0 downto 0);
-  signal sd_rx_disp_error, sd_rx_disp_error_q     : std_logic_vector(0 downto 0);
-  signal sd_rx_cv_error, sd_rx_cv_error_q         : std_logic_vector(0 downto 0); 
-  signal los, lsm_status                          : std_logic;
+  signal sd_tx_correct_disp                       : std_logic_vector(0 downto 0);
+  signal sd_rx_data                               : std_logic_vector(7 downto 0);
+  signal sd_rx_kcntl                              : std_logic_vector(0 downto 0);
+  signal sd_rx_disp_error                         : std_logic_vector(0 downto 0);
+  signal sd_rx_cv_error                           : std_logic_vector(0 downto 0); 
+--  signal los                                      : std_logic;
+  signal lsm_status                               : std_logic;
   signal rx_clk_en                                : std_logic;
   signal tx_clk_en                                : std_logic;
   signal operational_rate                         : std_logic_vector(1 downto 0);
@@ -237,7 +238,7 @@ architecture RTL of gbe_med_interface_single_5G is
   signal tsm_hdata                                : std_logic_vector(7 downto 0);
   signal tsm_haddr                                : std_logic_vector(7 downto 0);
   
-  signal synced_rst, ff : std_logic;
+  signal synced_rst, ff                           : std_logic;
   
   signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic;
 
@@ -270,12 +271,16 @@ begin
   --------------------------------------------------------------------
 --  debug(255 downto 0) <= (others => '0');
   DEBUG_OUT <= debug;
+  
+  -- debug(19..0) are on INTCOM
+  -- debug(33..20) are on GPIO
+  -- 33 = CLK2 (white/green)
+  -- 32 = CLK1 (white/blue)
   --------------------------------------------------------------------
   --------------------------------------------------------------------
 
   rst_dual <= not GSR_N;
   
-  -- was _SYS_
 --  reset_sync : process(GSR_N, CLK_125_IN)
 --  begin
 --    if (GSR_N = '0') then
@@ -343,7 +348,7 @@ begin
     serdes_rst_dual_c => '0',
     tx_serdes_rst_c   => '0'
   );
-  
+    
   THE_MAIN_TX_RST: main_tx_reset_RS
   port map (
     CLEAR                => rst_dual,
@@ -386,39 +391,29 @@ begin
     D_OUT(1) => rx_serdes_rst_q
   );
 
-  debug(0)  <= rst_dual;
-  debug(1)  <= pll_lol;
-  debug(2)  <= rx_cdr_lol;
-  debug(3)  <= rx_los_low;
-  debug(4)  <= sd_rx_cv_error(0);
-  debug(5)  <= lsm_status;
-  debug(6)  <= tx_pcs_rst;
-  debug(7)  <= rx_serdes_rst;
-  debug(8)  <= rx_pcs_rst;
-  debug(9)  <= link_rx_ready;
-  debug(10) <= link_tx_ready;
-  
-  -- one register between SGMII and SerDes
-  SYNC_TX_PROC : process(CLK_125_IN)
-  begin
-    if rising_edge(CLK_125_IN) then
-      sd_tx_data_q         <= sd_tx_data;
-      sd_tx_kcntl_q        <= sd_tx_kcntl;
-      sd_tx_correct_disp_q <= sd_tx_correct_disp;
-    end if;
-  end process SYNC_TX_PROC;
+  -- "Good" debugging pins
+  debug(7 downto 0)  <= sd_tx_data;
+  debug(15 downto 8) <= sd_rx_data;
+  debug(16)          <= sd_rx_kcntl(0);
+  debug(17)          <= sd_tx_kcntl(0);
+  debug(18)          <= '0';
+  debug(19)          <= '0';
+  -- "Bad" debugging pins
+  debug(20) <= pll_lol;
+  debug(21) <= rx_cdr_lol;
+  debug(22) <= rx_los_low;
+  debug(23) <= sd_rx_cv_error(0);
+  debug(24) <= lsm_status;
+  debug(25) <= '0';
+  debug(26) <= '0';
+  debug(27) <= '0';
+  debug(28) <= '0';
+  debug(29) <= '0';
+  debug(30) <= '0';
+  debug(31) <= '0';
+  debug(32) <= link_rx_ready;
+  debug(33) <= link_tx_ready;
 
-  -- one register between SerDes and SGMII
-  SYNC_RX_PROC : process(sd_rx_clk)
-  begin
-    if rising_edge(sd_rx_clk) then
-      sd_rx_data_q       <= sd_rx_data;
-      sd_rx_kcntl_q      <= sd_rx_kcntl;
-      sd_rx_disp_error_q <= sd_rx_disp_error;
-      sd_rx_cv_error_q   <= sd_rx_cv_error;
-    end if;
-  end process SYNC_RX_PROC;    
-  
   -- SGMII core
   SGMII_GBE_PCS : sgmii_gbe_core
   port map(
@@ -460,8 +455,8 @@ begin
     rx_kcntl                => sd_rx_kcntl(0), -- RX komma control from SerDes
     rx_err_decode_mode      => '0', -- receive error control mode fixed to normal
     rx_even                 => '0', -- unused (receive error control mode = normal, tie to GND)
-    rx_disp_err             => sd_rx_disp_error_q(0), -- RX disparity error from SerDes
-    rx_cv_err               => sd_rx_cv_error_q(0), -- RX code violation error from SerDes
+    rx_disp_err             => sd_rx_disp_error(0), -- RX disparity error from SerDes
+    rx_cv_err               => sd_rx_cv_error(0), -- RX code violation error from SerDes
     -- Autonegotiation stuff
     mr_an_complete          => an_complete,
     mr_page_rx              => mr_page_rx,
@@ -474,18 +469,6 @@ begin
           
   MAC_AN_READY_OUT <= an_complete;
   
-  debug(11)           <= sd_rx_kcntl(0);
-  debug(19 downto 12) <= sd_rx_data;
-
-  debug(20)           <= sd_tx_kcntl(0);
-  debug(28 downto 21) <= sd_tx_data;
-
-  debug(29) <= xmit(0);
-  debug(30) <= mr_main_reset;
-  debug(31) <= mr_restart_an;
-  debug(32) <= mr_page_rx;
-  debug(33) <= an_complete;
-
 --- SIMPLE ---
   operational_rate <= b"10";
 --- /SIMPLE ---