FREQUENCY PORT CLK_OSC 200 MHz;
FREQUENCY PORT CLK_EXT 200 MHz;
-FREQUENCY PORT CLK_CM_* 125 MHz;
-
-#################################################################
-# Reset Nets
-#################################################################
-GSR_NET NET "GSR_N";
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-REGION "MEDIA_UPLINK" "R105C109D" 10 22;
-REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-
-MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
-
-#REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-#REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
-#REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
-
-#LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-
-#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+#FREQUENCY PORT CLK_CM_* 125 MHz;
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;
+#MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ;
#################################################################
# Clock I/O
LOCATE COMP "CLK_EXT" SITE "C14"; #external
DEFINE PORT GROUP "CLK_group"
"CLK_CM_*"
-#"CLK_EXT"
"CLK_OSC";
+# "CLK_EXT"
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
IOBUF PORT "CLK_EXT" IO_TYPE=LVDS25;