Commit before pull origin of Jan Michel's updates

diff --git a/code/Cu_trb3_periph_soda_client.vhd b/code/Cu_trb3_periph_soda_client.vhd
index df8634cc6071960f2cd7054dc507a25996c80b23..fa43d4fc130bfa0afeef9d20a1859b3a7f827e72 100644 (file)
--- a/code/Cu_trb3_periph_soda_client.vhd
+++ b/code/Cu_trb3_periph_soda_client.vhd
@@ -31,156 +31,149 @@ entity Cu_trb3_periph_soda_client is
                CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
 
                --serdes I/O - connect as you like, no real use
-               SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-               SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
+               CU_SERDES_TX            : out std_logic_vector(3 downto 0);
+               CU_SERDES_RX            : in  std_logic_vector(3 downto 0);
+               SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
+               SERDES_ADDON_RX : in  std_logic_vector(15 downto 0);
                --Inter-FPGA Communication
                FPGA5_COMM : inout std_logic_vector(11 downto 0);
                                                                                                                                                --Bit 0/1 input, serial link RX active
                                                                                                                                                --Bit 2/3 output, serial link TX active
                                                                                                                                                --others yet undefined
                --Connection to AddOn
-               LED_LINKOK : out std_logic_vector(6 downto 1);
-               LED_RX     : out std_logic_vector(6 downto 1); 
-               LED_TX     : out std_logic_vector(6 downto 1);
-               SFP_MOD0   : in  std_logic_vector(6 downto 1);
-               SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-               SFP_LOS    : in  std_logic_vector(6 downto 1);
-               --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
-               --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
-               --SFP_RATESEL : out std_logic_vector(6 downto 1);
-               --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
+               LED_LINKOK                      : out std_logic_vector(6 downto 1);
+               LED_RX                          : out std_logic_vector(6 downto 1); 
+               LED_TX                          : out std_logic_vector(6 downto 1);
+               SFP_MOD0                                : in  std_logic_vector(6 downto 1);
+               SFP_TXDIS                       : out std_logic_vector(6 downto 1); 
+               SFP_LOS                         : in  std_logic_vector(6 downto 1);
                --Flash ROM & Reboot
-               FLASH_CLK  : out   std_logic;
-               FLASH_CS   : out   std_logic;
-               FLASH_DIN  : out   std_logic;
-               FLASH_DOUT : in    std_logic;
-               PROGRAMN   : out   std_logic;                     --reboot FPGA
-
+               FLASH_CLK                       : out   std_logic;
+               FLASH_CS                                : out   std_logic;
+               FLASH_DIN                       : out   std_logic;
+               FLASH_DOUT                      : in    std_logic;
+               PROGRAMN                                : out   std_logic;                     --reboot FPGA
                --Misc
-               TEMPSENS   : inout std_logic;       --Temperature Sensor
-               CODE_LINE  : in    std_logic_vector(1 downto 0);
-               LED_GREEN  : out   std_logic;
-               LED_ORANGE : out   std_logic;
-               LED_RED    : out   std_logic;
-               LED_YELLOW : out   std_logic;
-               SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
+               TEMPSENS        : inout std_logic;       --Temperature Sensor
+               CODE_LINE                       : in    std_logic_vector(1 downto 0);
+               LED_GREEN                       : out   std_logic;
+               LED_ORANGE                      : out   std_logic;
+               LED_RED                         : out   std_logic;
+               LED_YELLOW                      : out   std_logic;
+               SUPPL                                   : in    std_logic;       --terminated diff pair, PCLK, Pads
                --Test Connectors
-               TEST_LINE : out std_logic_vector(15 downto 0)
+               TEST_LINE                       : out std_logic_vector(15 downto 0)
        );\r
 end Cu_trb3_periph_soda_client;\r
 \r
 architecture Cu_trb3_periph_soda_client_arch of Cu_trb3_periph_soda_client is\r
        -- Constants
-       constant REGIO_NUM_STAT_REGS : integer := 0;
-       constant REGIO_NUM_CTRL_REGS : integer := 2;
-
+       constant REGIO_NUM_STAT_REGS    : integer := 0;
+       constant REGIO_NUM_CTRL_REGS    : integer := 2;
 
-       constant USE_200_MHZ : integer := 1 - USE_125_MHZ;      -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
+       constant USE_200_MHZ                            : integer := 1 - USE_125_MHZ;   -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
 
        --Clock / Reset
-       signal pll_lock                                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-       signal clear_i                                          : std_logic;
-       signal reset_i                                          : std_logic;
-       signal GSR_N                                            : std_logic;
-
-       signal clk_100_osc              : std_logic;
-       signal clk_200_osc                 : std_logic;
-       signal time_counter                             : unsigned(31 downto 0);
+       signal pll_lock                                         : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+       signal clear_i                                                  : std_logic;
+       signal reset_i                                                  : std_logic;
+       signal GSR_N                                                    : std_logic;
+
+       signal clk_100_osc                      : std_logic;
+       signal clk_200_osc                 : std_logic;
+       signal time_counter                                     : unsigned(31 downto 0);
 \r
        --Media Interface
-       signal med_stat_op                              : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-       signal med_ctrl_op                              : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-       signal med_stat_debug                   : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-       signal med_ctrl_debug                   : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-       signal med_data_out                             : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-       signal med_packet_num_out               : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-       signal med_dataready_out                : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-       signal med_read_out                             : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-       signal med_data_in                              : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-       signal med_packet_num_in                : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-       signal med_dataready_in                 : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-       signal med_read_in                              : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+       signal med_stat_op                                      : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+       signal med_ctrl_op                                      : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+       signal med_stat_debug                           : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+       signal med_ctrl_debug                           : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
+       signal med_data_out                                     : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+       signal med_packet_num_out                       : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+       signal med_dataready_out                        : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+       signal med_read_out                                     : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+       signal med_data_in                                      : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
+       signal med_packet_num_in                        : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
+       signal med_dataready_in                         : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
+       signal med_read_in                                      : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
 
        --Slow Control channel
-       signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-       signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-       signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-       signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-       signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-       signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-       signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-       signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+       signal common_stat_reg                          : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+       signal common_ctrl_reg                          : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+       signal stat_reg                                         : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+       signal ctrl_reg                                         : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+       signal common_stat_reg_strobe           : std_logic_vector(std_COMSTATREG-1 downto 0);
+       signal common_ctrl_reg_strobe           : std_logic_vector(std_COMCTRLREG-1 downto 0);
+       signal stat_reg_strobe                          : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+       signal ctrl_reg_strobe                          : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
 \r
        --RegIO
-       signal my_address             : std_logic_vector (15 downto 0);
-       signal regio_addr_out         : std_logic_vector (15 downto 0);
-       signal regio_read_enable_out  : std_logic;
-       signal regio_write_enable_out : std_logic;
-       signal regio_data_out         : std_logic_vector (31 downto 0);
-       signal regio_data_in          : std_logic_vector (31 downto 0);
-       signal regio_dataready_in     : std_logic;
-       signal regio_no_more_data_in  : std_logic;
-       signal regio_write_ack_in     : std_logic;
-       signal regio_unknown_addr_in  : std_logic;
-       signal regio_timeout_out      : std_logic;
+       signal my_address                                               : std_logic_vector (15 downto 0);
+       signal regio_addr_out                           : std_logic_vector (15 downto 0);
+       signal regio_read_enable_out            : std_logic;
+       signal regio_write_enable_out           : std_logic;
+       signal regio_data_out                           : std_logic_vector (31 downto 0);
+       signal regio_data_in                                    : std_logic_vector (31 downto 0);
+       signal regio_dataready_in                       : std_logic;
+       signal regio_no_more_data_in            : std_logic;
+       signal regio_write_ack_in                       : std_logic;
+       signal regio_unknown_addr_in            : std_logic;
+       signal regio_timeout_out                        : std_logic;
 \r
        --Timer
-       signal global_time         : std_logic_vector(31 downto 0);
-       signal local_time          : std_logic_vector(7 downto 0);
-       signal time_since_last_trg : std_logic_vector(31 downto 0);
-       signal timer_ticks         : std_logic_vector(1 downto 0);
+       signal global_time                                      : std_logic_vector(31 downto 0);
+       signal local_time                                               : std_logic_vector(7 downto 0);
+       signal time_since_last_trg                      : std_logic_vector(31 downto 0);
+       signal timer_ticks                                      : std_logic_vector(1 downto 0);
 \r
        --Flash
-       signal spimem_read_en          : std_logic;
-       signal spimem_write_en         : std_logic;
-       signal spimem_data_in          : std_logic_vector(31 downto 0);
-       signal spimem_addr             : std_logic_vector(8 downto 0);
-       signal spimem_data_out         : std_logic_vector(31 downto 0);
-       signal spimem_dataready_out    : std_logic;
-       signal spimem_no_more_data_out : std_logic;
-       signal spimem_unknown_addr_out : std_logic;
-       signal spimem_write_ack_out     : std_logic;
+       signal spimem_read_en                           : std_logic;
+       signal spimem_write_en                          : std_logic;
+       signal spimem_data_in                           : std_logic_vector(31 downto 0);
+       signal spimem_addr                                      : std_logic_vector(8 downto 0);
+       signal spimem_data_out                          : std_logic_vector(31 downto 0);
+       signal spimem_dataready_out             : std_logic;
+       signal spimem_no_more_data_out  : std_logic;
+       signal spimem_unknown_addr_out  : std_logic;
+       signal spimem_write_ack_out             : std_logic;
 \r
        --Cu media interface
-       signal sci1_ack                                 : std_logic;
-       signal sci1_write                                       : std_logic;
-       signal sci1_read                                        : std_logic;
-       signal sci1_data_in                             : std_logic_vector(7 downto 0);
-       signal sci1_data_out                            : std_logic_vector(7 downto 0);
-       signal sci1_addr                                        : std_logic_vector(8 downto 0);  
-       signal sfp_txdis_S                              : std_logic_vector(6 downto 1)  := (others => '1'); 
+       signal sci1_ack                                         : std_logic;
+       signal sci1_write                                               : std_logic;
+       signal sci1_read                                                : std_logic;
+       signal sci1_data_in                                     : std_logic_vector(7 downto 0);
+       signal sci1_data_out                                    : std_logic_vector(7 downto 0);
+       signal sci1_addr                                                : std_logic_vector(8 downto 0);  
+       signal sfp_txdis_S                                      : std_logic_vector(6 downto 1)  := (others => '1'); 
 
 
        --SODA
-       signal soda_rx_full_clk                 : std_logic;
-       signal soda_rx_half_clk                 : std_logic;
-       signal soda_tx_full_clk                 : std_logic;
-       signal soda_tx_half_clk                 : std_logic;
-
-       signal soda_tx_dlm_S                            : std_logic;
-       signal soda_tx_dlm_word_S               : std_logic_vector(7 downto 0);
-       signal soda_rx_dlm_S                            : std_logic;
-       signal soda_rx_dlm_word_S               : std_logic_vector(7 downto 0);
---     signal make_reset                                       : std_logic;
-       signal soda_tx_dlm_preview_S    : std_logic;    --PL!
-       signal link_phase_S                             : std_logic;    --PL!
---     signal rx_cdr_lol_S                             : std_logic;
---     signal link_locked_S                            : std_logic;    --PL!
+       signal soda_rx_full_clk                         : std_logic;
+       signal soda_rx_half_clk                         : std_logic;
+       signal soda_tx_full_clk                         : std_logic;
+       signal soda_tx_half_clk                         : std_logic;
+
+       signal soda_tx_dlm_S                                    : std_logic;
+       signal soda_tx_dlm_word_S                       : std_logic_vector(7 downto 0);
+       signal soda_rx_dlm_S                                    : std_logic;
+       signal soda_rx_dlm_word_S                       : std_logic_vector(7 downto 0);
+--     signal make_reset                                               : std_logic;
+       signal soda_tx_dlm_preview_S            : std_logic;    --PL!
+       signal link_phase_S                                     : std_logic;    --PL!
+--     signal rx_cdr_lol_S                                     : std_logic;
+--     signal link_locked_S                                    : std_logic;    --PL!
 
        -- SODA slow controll
-       signal soda_ack                                 : std_logic;
-       signal soda_write                                       : std_logic;
-       signal soda_read                                        : std_logic;
-       signal soda_data_in                             : std_logic_vector(31 downto 0);
-       signal soda_data_out                            : std_logic_vector(31 downto 0);
-       signal soda_addr                                        : std_logic_vector(3 downto 0);  
-       signal soda_leds                                        : std_logic_vector(3 downto 0);  
-
-       signal link_debug_in_S                  : std_logic_vector(31 downto 0);
-       signal general_reset_i                  : std_logic := '1';
+       signal soda_ack                                         : std_logic;
+       signal soda_write                                               : std_logic;
+       signal soda_read                                                : std_logic;
+       signal soda_data_in                                     : std_logic_vector(31 downto 0);
+       signal soda_data_out                                    : std_logic_vector(31 downto 0);
+       signal soda_addr                                                : std_logic_vector(3 downto 0);  
+       signal soda_leds                                                : std_logic_vector(3 downto 0);  
+
+       signal link_debug_in_S                          : std_logic_vector(31 downto 0);
+       signal general_reset_i                          : std_logic := '1';
 \r
 begin\r
 ---------------------------------------------------------------------------
@@ -241,10 +234,10 @@ THE_MAIN_PLL : pll_in200_out100
                        MED_READ_IN                                     => med_read_out(0),
 
                        --Copper SFP Connection
-                       CU_RXD_P_IN                                     => SERDES_ADDON_RX(2),
-                       CU_RXD_N_IN                                     => SERDES_ADDON_RX(3),
-                       CU_TXD_P_OUT                            => SERDES_ADDON_TX(2),
-                       CU_TXD_N_OUT                            => SERDES_ADDON_TX(3),
+                       CU_RXD_P_IN                                     => CU_SERDES_RX(0),
+                       CU_RXD_N_IN                                     => CU_SERDES_RX(1),
+                       CU_TXD_P_OUT                            => CU_SERDES_TX(0),
+                       CU_TXD_N_OUT                            => CU_SERDES_TX(1),
                        CU_PRSNT_N_IN                           => FPGA5_COMM(0),
                        CU_LOS_IN                                       => FPGA5_COMM(0),
                        CU_TXDIS_OUT                            => FPGA5_COMM(2),

diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd
index e72c1b5a9a0ff8fa05863bcdb7840bc9fa7fc227..9a24e7139d97f50e7c3a4760503f25112ba2ce67 100644 (file)
--- a/code/med_ecp3_sfp_4_sync_down.vhd
+++ b/code/med_ecp3_sfp_4_sync_down.vhd
@@ -18,7 +18,7 @@ entity med_ecp3_sfp_4_sync_down is
                OSC_CLK                                 : in  std_logic; -- 200 MHz reference clock
                TX_DATACLK                              : in  std_logic; -- 200 MHz data clock
                SYSCLK                                  : in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
-               RESET                                           : in  std_logic; -- synchronous reset
+               RESET                                           : in  std_logic; -- synchronous reet
                CLEAR                                           : in  std_logic; -- asynchronous reset
                ---------------------------------------------------------------------------------------------------------------------------------------------------------
                LINK_DISABLE_IN         : in  std_logic;        -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
@@ -162,6 +162,34 @@ signal debug_reg                                                   : std_logic_vector(63 downto 0);
 type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
 signal sci_state                                                       : sci_ctrl;
 signal sci_timer                                                       : t_HUB_TIMER13 := (others => (others => '0')); --unsigned(12 downto 0)                         := (others => '0');
+\r
+-- fix signal names for constraining
+attribute syn_preserve         : boolean;
+attribute syn_keep                     : boolean;
+attribute syn_useioff          : boolean;
+
+attribute syn_useioff  of sd_los_i                             : signal is false;              -- do not use an IOFF for this signal
+\r
+attribute syn_preserve of sci_ch_i                             : signal is true;
+attribute syn_keep             of sci_ch_i                             : signal is true;
+attribute syn_preserve of sci_qd_i                             : signal is true;
+attribute syn_keep             of sci_qd_i                             : signal is true;
+attribute syn_preserve of sci_reg_i                    : signal is true;
+attribute syn_keep             of sci_reg_i                    : signal is true;
+attribute syn_preserve of sci_addr_i                   : signal is true;
+attribute syn_keep             of sci_addr_i                   : signal is true;
+attribute syn_preserve of sci_data_in_i                : signal is true;
+attribute syn_keep             of sci_data_in_i                : signal is true;
+attribute syn_preserve of sci_data_out_i               : signal is true;
+attribute syn_keep             of sci_data_out_i               : signal is true;
+attribute syn_preserve of sci_read_i                   : signal is true;
+attribute syn_keep             of sci_read_i                   : signal is true;
+attribute syn_preserve of sci_write_i                  : signal is true;
+attribute syn_keep             of sci_write_i                  : signal is true;
+attribute syn_preserve of sci_write_shift_i    : signal is true;
+attribute syn_keep             of sci_write_shift_i    : signal is true;
+attribute syn_preserve of      sci_read_shift_i        : signal is true;
+attribute syn_keep             of sci_read_shift_i     : signal is true;
 
 begin
 
@@ -505,9 +533,8 @@ generated_logic     : for i in 0 to 3 generate
        );   
 
        internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
---     sd_los_i(i)                                                             <= SD_LOS_IN(i)                 when rising_edge(SYSCLK); --PL! 200115
-       sd_los_i(i)                                                             <= SD_LOS_IN(i)                 when rising_edge(clk_200_txdata);
-
+       sd_los_i(i)                                                             <= SD_LOS_IN(i)                 when rising_edge(SYSCLK); --PL! 200115
+       
 end generate;    
     
 -------------------------------------------------      

diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd
index 42f06544db1cefbc4eaab15f857c5cb877067bb0..8ef454ef8b28fbc3eb594829309133e435c9b0e9 100644 (file)
--- a/code/med_ecp3_sfp_sync_up.vhd
+++ b/code/med_ecp3_sfp_sync_up.vhd
@@ -134,8 +134,12 @@ signal sci_write_shift_i : std_logic_vector(2 downto 0);
 signal sci_read_shift_i  : std_logic_vector(2 downto 0);
 
 -- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
+attribute syn_preserve         : boolean;
+attribute syn_keep                     : boolean;
+attribute syn_useioff          : boolean;\r
+\r
+attribute syn_useioff  of sd_los_i                             : signal is false;              -- do not use an IOFF for this signal
+\r
 attribute syn_preserve of sci_ch_i                             : signal is true;
 attribute syn_keep             of sci_ch_i                             : signal is true;
 attribute syn_preserve of sci_qd_i                             : signal is true;
@@ -157,20 +161,20 @@ attribute syn_keep                of sci_write_shift_i    : signal is true;
 attribute syn_preserve of      sci_read_shift_i        : signal is true;
 attribute syn_keep             of sci_read_shift_i     : signal is true;
 
-signal wa_position        : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx     : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow           : std_logic;
-signal rx_allow           : std_logic;
-signal tx_allow_q         : std_logic;
-signal rx_allow_q         : std_logic;
-signal link_phase_S                    : std_logic;    --PL!
-signal request_retr_i     : std_logic;
-signal start_retr_i       : std_logic;
-signal request_retr_position_i  : std_logic_vector(7 downto 0);
-signal start_retr_position_i    : std_logic_vector(7 downto 0);
-signal send_link_reset_i  : std_logic;
-signal make_link_reset_i  : std_logic;
-signal got_link_ready_i   : std_logic;
+signal wa_position                                             : std_logic_vector(15 downto 0) := x"FFFF";
+signal wa_position_rx                                  : std_logic_vector(15 downto 0) := x"FFFF";
+signal tx_allow                                                        : std_logic;
+signal rx_allow                                                        : std_logic;
+signal tx_allow_q                                                      : std_logic;
+signal rx_allow_q                                                      : std_logic;
+signal link_phase_S                                            : std_logic;    --PL!
+signal request_retr_i                                  : std_logic;
+signal start_retr_i                                            : std_logic;
+signal request_retr_position_i         : std_logic_vector(7 downto 0);
+signal start_retr_position_i                   : std_logic_vector(7 downto 0);
+signal send_link_reset_i                               : std_logic;
+signal make_link_reset_i                               : std_logic;
+signal got_link_ready_i                                        : std_logic;
 signal internal_make_link_reset_out : std_logic;
 
 attribute syn_preserve of      wa_position                     : signal is true;
@@ -536,8 +540,7 @@ debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
 STAT_DEBUG <= debug_reg;
 
 internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
---sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);      -- PL!
-sd_los_i <= SD_LOS_IN when rising_edge(rx_full_clk);   -- PL! 200115
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);        -- PL!
 
 STAT_OP(15)            <= send_link_reset_i when rising_edge(SYSCLK);
 STAT_OP(14)            <= '0';

diff --git a/code/soda_components.vhd b/code/soda_components.vhd
index a92658986af47e21eb3d33ca73c03e6a8733ca59..5cb3cc56669531cf4dfa2d0aec980cf558ef0e49 100644 (file)
--- a/code/soda_components.vhd
+++ b/code/soda_components.vhd
@@ -30,7 +30,7 @@ package soda_components is
 
        constant c_QUAD_DATA_WIDTH                              : integer := 4*c_DATA_WIDTH;
        constant c_QUAD_NUM_WIDTH                               : integer := 4*c_NUM_WIDTH;
-       constant c_QUAD_MUX_WIDTH                               : integer := 3; --!!!
+       constant c_QUAD_MUX_WIDTH                               : integer := 3;
 
        subtype t_HUB_BIT                               is std_logic_vector(c_HUB_CHILDREN-1 downto 0);
        type            t_HUB_NUM                               is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0);
@@ -470,7 +470,7 @@ package soda_components is
                );
        end component;
 
-       component med_ecp3_sfp_4_sync_down_EP is
+       component soda_only_ecp3_sfp_4_sync_down is
                generic(        SERDES_NUM : integer range 0 to 3 := 0;
                                        IS_SYNC_SLAVE : integer := c_NO); --select slave mode
                port(
@@ -482,6 +482,7 @@ package soda_components is
                        ---------------------------------------------------------------------------------------------------------------------------------------------------------
                        LINK_DISABLE_IN         : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
                        ---------------------------------------------------------------------------------------------------------------------------------------------------------
+                       --Internal Connection TX
                        RX_HALF_CLK_OUT         : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
                        RX_FULL_CLK_OUT         : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
                        TX_HALF_CLK_OUT         : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
@@ -512,14 +513,60 @@ package soda_components is
                        SCI_READ                                        : in std_logic := '0';
                        SCI_WRITE                               : in std_logic := '0';
                        SCI_ACK                                 : out std_logic := '0';
-                       SCI_NACK                                        : out std_logic := '0';
-                       -- Status and control port
---                     STAT_OP                                 : out   t_HUB_WORD;     --std_logic_vector (15 downto 0);
---                     CTRL_OP                                 : in    t_HUB_WORD;     --std_logic_vector (15 downto 0) := (others => '0');
-                       STAT_DEBUG                              : out std_logic_vector (63 downto 0);
-                       CTRL_DEBUG                              : in std_logic_vector (63 downto 0) := (others => '0')
+                       SCI_NACK                                        : out std_logic := '0'
                );
        end component;
+\r
+--component med_ecp3_sfp_4_sync_down_EP is
+               --generic(      SERDES_NUM : integer range 0 to 3 := 0;
+                                       --IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+               --port(
+                       --OSC_CLK                                       : in std_logic; -- 200 MHz reference clock
+                       --TX_DATACLK                            : in std_logic; -- 200 MHz data clock
+                       --SYSCLK                                        : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock
+                       --RESET                                         : in std_logic; -- synchronous reset
+                       --CLEAR                                         : in std_logic; -- asynchronous reset
+                       -----------------------------------------------------------------------------------------------------------------------------------------------------------
+                       --LINK_DISABLE_IN               : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+                       -----------------------------------------------------------------------------------------------------------------------------------------------------------
+                       --RX_HALF_CLK_OUT               : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+                       --RX_FULL_CLK_OUT               : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+                       --TX_HALF_CLK_OUT               : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz
+                       --TX_FULL_CLK_OUT               : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz
+
+                       ----Sync operation
+                       --RX_DLM                                        : out t_HUB_BIT;        --std_logic_vector(3 downto 0)                  := (others => '0');
+                       --RX_DLM_WORD                           : out   t_HUB_BYTE;     --std_logic_vector(4*8 - 1 downto 0)    := (others => '0');
+                       --TX_DLM                                        : in t_HUB_BIT; --std_logic_vector(3 downto 0)                  := (others => '0');
+                       --TX_DLM_WORD                           : in    t_HUB_BYTE;     --std_logic_vector(4*8 - 1 downto 0)    := (others => '0');
+                       --TX_DLM_PREVIEW_IN             : in    t_HUB_BIT;      --std_logic_vector(3 downto 0)                  := (others => '0');     --PL!
+                       --LINK_PHASE_OUT                        : out   t_HUB_BIT;      --std_logic_vector(3 downto 0)                  := (others => '0');     --PL!
+
+                       ----SFP Connection
+                       --SD_RXD_P_IN                           : in    t_HUB_BIT;      --std_logic;
+                       --SD_RXD_N_IN                           : in    t_HUB_BIT;      --std_logic;
+                       --SD_TXD_P_OUT                  : out   t_HUB_BIT;      --std_logic;
+                       --SD_TXD_N_OUT                  : out   t_HUB_BIT;      --std_logic;
+                       --SD_REFCLK_P_IN                        : in    t_HUB_BIT;      --std_logic; --not used
+                       --SD_REFCLK_N_IN                        : in    t_HUB_BIT;      --std_logic; --not used
+                       --SD_PRSNT_N_IN                 : in    t_HUB_BIT;      --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+                       --SD_LOS_IN                             : in    t_HUB_BIT;      --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+                       --SD_TXDIS_OUT                  : out   t_HUB_BIT;      --std_logic := '0'; -- SFP disable
+                       ----Control Interface
+                       --SCI_DATA_IN                           : in std_logic_vector(7 downto 0) := (others => '0');
+                       --SCI_DATA_OUT                  : out std_logic_vector(7 downto 0) := (others => '0');
+                       --SCI_ADDR                                      : in std_logic_vector(8 downto 0) := (others => '0');
+                       --SCI_READ                                      : in std_logic := '0';
+                       --SCI_WRITE                             : in std_logic := '0';
+                       --SCI_ACK                                       : out std_logic := '0';
+                       --SCI_NACK                                      : out std_logic := '0';
+                       ---- Status and control port
+----                   STAT_OP                                 : out   t_HUB_WORD;     --std_logic_vector (15 downto 0);
+----                   CTRL_OP                                 : in    t_HUB_WORD;     --std_logic_vector (15 downto 0) := (others => '0');
+                       --STAT_DEBUG                            : out std_logic_vector (63 downto 0);
+                       --CTRL_DEBUG                            : in std_logic_vector (63 downto 0) := (others => '0')
+               --);
+       --end component;
 
        component med_ecp3_sfp_sync_up is
                generic(
@@ -780,7 +827,7 @@ package soda_components is
                        );
        end component;
 \r
-       component soda_clockscaler is
+       component soda_clockscaler
                port(
                        CLK                                             : in    std_logic; -- fabric clock
                        RESET                                           : in    std_logic; -- synchronous reset
@@ -789,13 +836,7 @@ package soda_components is
                        );
        end component;\r
 \r
-       component DCS
-               -- synthesis translate_off
-               generic
-                       (
-                               DCSMODE : string :=“POS”
-                       );
-               -- synthesis translate_on
+component DCS\r         generic(DCSMODE : string :="POS");
                port (
                        CLK0                                            : in std_logic ;
                        CLK1                                            : in std_logic ;

diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd
index 00f8069df4e976d9c9e5dc9a0181eefe6e12684c..4253f5b3759cba055a6e3233c9b0a0f5859d3da3 100644 (file)
--- a/code/soda_hub.vhd
+++ b/code/soda_hub.vhd
@@ -432,11 +432,11 @@ end process TRANSFORM;
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
                                buf_bus_data_out        <= calib_register_S(0);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
-                               buf_bus_data_out        <= calib_register_S(0);
+                               buf_bus_data_out        <= calib_register_S(1);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
-                               buf_bus_data_out        <= calib_register_S(0);
+                               buf_bus_data_out        <= calib_register_S(2);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then
-                               buf_bus_data_out        <= calib_register_S(0);
+                               buf_bus_data_out        <= calib_register_S(3);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
                                buf_bus_data_out                <= CTRL_STATUS_register_S(0);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then

diff --git a/code/trb_net16_soda_sync_ecp3_sfp.vhd b/code/trb_net16_soda_sync_ecp3_sfp.vhd
index 8000fb5adc9d9a0c8ee14f7f68830392187eec7b..b9331287f507a788bcc469c717be9d16eeb96fc0 100644 (file)
--- a/code/trb_net16_soda_sync_ecp3_sfp.vhd
+++ b/code/trb_net16_soda_sync_ecp3_sfp.vhd
@@ -258,6 +258,8 @@ architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3
        signal trb_rx_pcs_rst                                   : std_logic;
        signal trb_tx_pcs_rst                                   : std_logic;
        signal rst_qd                                                           : std_logic;
+       signal rst_qd1                                                          : std_logic;
+       signal rst_qd3                                                          : std_logic;
        signal link_OK_S                                                        : std_logic;
        signal trb_rx_fsm_state                                 : std_logic_vector(3 downto 0);
        signal trb_tx_fsm_state                                 : std_logic_vector(3 downto 0);
@@ -609,7 +611,7 @@ ffc_lane_rx_rst      <= lane_rst;
                TX_SERDES_RST_C     => CLEAR,
                TX_PLL_LOL_QD_S     => link_error(5), 
                TX_SYNC_QD_C                    => '0',
-               RST_QD_C                                        => '0',
+               RST_QD_C                                        => rst_qd,
                REFCLK2FPGA                             => open,
                SERDES_RST_QD_C     => ffc_quad_rst
        );
@@ -845,7 +847,7 @@ THE_TX_FSM1: tx_reset_fsm
                RST_N           => reset_n,
                TX_REFCLK       => OSCCLK,
                TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-               RST_QD_C        => rst_qd,
+               RST_QD_C        => rst_qd1,
                TX_PCS_RST_CH_C => trb_tx_pcs_rst,
                STATE_OUT       => trb_tx_fsm_state     --open
        );
@@ -875,12 +877,15 @@ THE_TX_FSM3 : tx_reset_fsm
     RST_N           => reset_n,
     TX_REFCLK       => OSCCLK,
     TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => open, --??
+    RST_QD_C        => rst_qd3,
     TX_PCS_RST_CH_C => sync_tx_pcs_rst,
     STATE_OUT       => sync_tx_fsm_state
     );
 \r
-TX_READY_CH3 <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';  
+--rst_qd                       <= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
+rst_qd                 <= RESET;
+\r
+TX_READY_CH3   <= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';  
 \r
 -----------------------------------------------------------------------------------------------------
 -- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us

diff --git a/ctsc.lpf b/ctsc.lpf
index 082431148beb9b16bcc9ce9857e73a22313893c5..abf8239b6771287534dc79e09391f5aeee5e1e56 100644 (file)
--- a/ctsc.lpf
+++ b/ctsc.lpf
@@ -1,4 +1,4 @@
-rvl_alias "soda_rx_full_clk" "soda_rx_full_clk";
+rvl_alias "soda_rx_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out";
 BLOCK RESETPATHS;
 BLOCK ASYNCPATHS;
 BLOCK RD_DURING_WR_PATHS ;
@@ -153,6 +153,4 @@ FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
 FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
 
 FREQUENCY NET "soda_rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rx_half_clk" 100.000000 MHz ;
-#FREQUENCY NET "soda_tx_full_clk" 200.000000 MHz ;
-#FREQUENCY NET "soda_tx_half_clk" 100.000000 MHz ;
\ No newline at end of file
+FREQUENCY NET "soda_rx_half_clk" 100.000000 MHz ;
\ No newline at end of file