-
-
-
-
-
-
--
-- function count_ones( input:std_logic_vector ) return integer is
-- variable temp:std_logic_vector(input'range);
signal temp_save2 : std_logic;
signal ext : std_logic;
signal finalout : std_logic;
--- signal temp_save2 : std_logic;
signal temp_out : std_logic;
signal reset_pulse_i : std_logic;
signal reset_hitcounter : std_logic;
begin
integration_time_int <= unsigned(int_time(31 downto 0));
--- max_hitcount <= unsigned(max_count(31 downto 0))+1; --Sehr ungalante methode den anfangsfehler zu umgehen, evtl wieder loeschen
max_hitcount <= unsigned(max_count(31 downto 0));
current_hits_vctr <= std_logic_vector(hitteller);
--- hitsaver <= hitcounter;
reset_pulse <= reset_pulse_i;
PROC_SAFETYOFF: process begin -- stops the entity from sending signals before there are values recieved from the bussystem
POC_OUTPUT: process begin
wait until rising_edge(clk_in);
-
-if reset_pulse_i='1' then
- hitteller <= hitsaver;
- if temp_out = '1' then
--- temp_out<='0';
- ext<='1';
- elsif ext='1' then
- ext<='0';
--- temp_out<='0';
- else
--- temp_out<='0';
- ext<='0';
+ if reset_pulse_i='1' then
+ hitteller <= hitsaver;
+ if temp_out = '1' then
+ ext<='1';
+ elsif ext='1' then
+ ext<='0';
+ else
+ ext<='0';
+ end if;
end if;
-end if;
end process;
---
--- PROC_OUTPUT: process (reset_pulse)
--- begin
--- hitteller <= hitcounter;
--- -- hitcounter <= x"00000000";
--- if temp_out = '1' then
--- temp_out<='0';
--- ext<='1';
--- elsif ext='1' then
--- ext<='0';
--- temp_out<='0';
--- else
--- temp_out<='0';
--- ext<='0';
--- end if;
---
--- end process;
---
PROC_MSPUSER: process begin -- generate a pulse every 0.1 ms
wait until rising_edge (clk_in);
- if ms_timer=x"2710" then -- eqals 10.000 rising edges
- ms_pulse<='1';
- ms_timer<=x"0000" ;
+ if ms_timer = x"2710" then -- eqals 10.000 rising edges
+ ms_pulse <= '1';
+ ms_timer <= x"0000" ;
else
ms_timer <= ms_timer+1;
ms_pulse<='0';
TIMERESETPULSE: process begin -- generates a pulse every time the integration window is closed
wait until rising_edge(clk_in);
-
- if timecounter >= integration_time_int then -- changed from = so it doesnt softlock in between < and >
+ if timecounter >= integration_time_int then
reset_pulse_i <= '1';
timecounter <= x"00000000";
elsif timecounter < integration_time_int and ms_pulse='1' then
-- Registers with values
type Array32bit is array(INPUTS-1 downto 0) of std_logic_vector (31 downto 0); -- Register-Type for individuals is 24 times 32 bit deep
-
-
signal stretch_time : Array32bit:=(others => (others => '0')); -- Register Entries INPUT
signal max_count : Array32bit:=(others => (others => '0')); -- or individual entity INPUT
signal reg_compare_1: std_logic_vector(31 downto 0):=(others => '0'); -- Register to set max value of simultanious peaks
signal disableReg_compare: std_logic_vector(31 downto 0):=(others => '0'); -- Disable Register for single channels
-
-- registers for READOUT
signal current_count: Array32bit:=(others => (others => '0'));
-- OUTPUT from indiv to bussystem to log the live values of every channel
signal fifo_writesignal: std_logic_vector(INPUTS-1 downto 0);
signal man_readFlag: std_logic_vector(31 downto 0);
signal read_mem_Flag: std_logic_vector(INPUTS-1 downto 0);
+-- signal fifoEmpty: std_logic;
+signal fifoEmpty: std_logic_vector(INPUTS-1 downto 0);
-- signal store_values : Array32bit:=(others => (others => '0'));
signal plot_values : Array32bit:=(others => (others => '0'));
individual_alerts(INPUTS-1 downto 0) <= indiv_2_comp;
in_2_indiv <= INPUT;
--- OUTPUT(0) <= shutdown_signal;
signal_register(0) <= shutdown_signal;
--- comp_2_out(1) <= not comp_2_out(0);
-
-
+
--- PROC_OFFSWITCH : process begin -- Version 1, in sync
--- wait until rising_edge(CLK);
--- if register_onoff(0) = '1' then
--- OUTPUT <= comp_2_out;
--- else
--- OUTPUT <= (others => '0');
--- end if;
--- end process;
-PROC_OFFSWITCH : process (comp_2_out) --Version 2 out of sync
+PROC_OFFSWITCH : process (comp_2_out)
begin
if register_onoff(0) = '1' then
shutdown_signal <= comp_2_out(0);
--- shutdown_signal <= comp_2_out;
else
- shutdown_signal <= '0';
--- shutdown_signal <= (others => '0');
-
+ shutdown_signal <= '0';
end if;
end process;
BUS_TX.data <= signal_register;
elsif BUS_RX.addr(11 downto 8) = x"8" then
--- intersting stuff happening here
- -- read Enable of FiFo set to '1'
-
--- read_mem_Flag <= x"FFFFF"; -- do i need a whole vector, is 1 bit enugh ?
- -- end of interesting stuff
+
if address_i < INPUTS then
- BUS_TX.data <= plot_values(address_i);
- read_mem_Flag(address_i) <= '1';
+ if fifoEmpty(address_i) = '1' then
+ BUS_TX.nack <= '1';
+ BUS_TX.ack <= '0';
+ else
+ BUS_TX.data <= plot_values(address_i);
+ read_mem_Flag(address_i) <= '1';
+ end if;
+
else
BUS_TX.ack <= '0'; BUS_TX.unknown <= '1' ;
end if;
elsif BUS_RX.addr(11 downto 8) = x"9" then
- -- to set manually in order to stop all loading of the fifos
- BUS_TX.data <= man_readFlag; -- 1 bit def. enough here
+ BUS_TX.data <= man_readFlag;
else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end if;
- elsif BUS_RX.write = '1' then --WRITE
+ elsif BUS_RX.write = '1' then --WRITE
BUS_TX.ack <= '1';
if BUS_RX.addr(11 downto 8) = x"0" then
if address_i < INPUTS then
reg_compare_1 <= BUS_RX.data;
elsif BUS_RX.addr(11 downto 8) = x"3" then
disableReg_compare <= BUS_RX.data;
- elsif BUS_RX.addr(11 downto 8) = x"6" then -- write the preset Value of ON/OFF in the boards register
+ elsif BUS_RX.addr(11 downto 8) = x"6" then -- write the preset Value of ON/OFF in the boards register
register_onoff <= BUS_RX.data;
elsif BUS_RX.addr(11 downto 8) = x"9" then
port map(
clk_in => CLK,
--- disable_reg => disableReg_monitor,
reset => RESET,
hitvalue => current_count(i),
writeFlag => fifo_writesignal(i),
read_cmd => read_mem_Flag(i), -- automatic Read Flag
- read_global => man_readFlag(i), -- manuell Read Flag
- output_val => plot_values(i)
-
+ read_global => man_readFlag(i), -- manuell Read Flag
+ output_val => plot_values(i),
+ emptyFlag => fifoEmpty(i)
);
end generate;
writeFlag : in std_logic;
read_cmd : in std_logic; --coming from BUS_RX.read '1'
read_global : in std_logic; --coming from register/manually
- output_val : out std_logic_vector (31 downto 0)
- );
+ output_val : out std_logic_vector (31 downto 0);
+ emptyFlag : out std_logic);
end shutdown_mon;
architecture behave of shutdown_mon is
signal amFull: std_logic;
signal last_amFull: std_logic;
signal allow_write: std_logic;
-signal waiter: std_logic;
signal in_2_fifo: std_logic_vector (35 downto 0):= x"000000000";
signal timer: unsigned(15 downto 0):= x"0000";
--- signal reset_i: std_logic:='0';
signal output_val_handler: std_logic_vector (35 downto 0);
+-- signal helper: std_logic;
begin
data_2_fifo <= hitvalue;
output_val <= output_val_handler(31 downto 0);
in_2_fifo(31 downto 0) <= hitvalue;
-
-
-PROC_FIFOREAD: process is
--- stop everything if readflag is high
-begin
- wait until rising_edge(clk_in);
-
- if read_global='1' then
- allow_write <= '0'; -- need to change
-
- else
- allow_write <= '1';
-
-end if;
-end process;
+-- allow_write <= not read_global;
PROC_FIFOWRTITE: process is
-- only write if the write flag is active
begin
- wait until rising_edge(clk_in);
-
- if allow_write = '1' then
- if writeFlag='1' then
- writesignal <= '1';
--- in_2_fifo(31 downto 0) <= hitvalue;
--- in_2_fifo(35 downto 32) <= x"0";
- else
- writesignal <= '0';
- end if;
-
-
+wait until rising_edge(clk_in);
+
+ if read_global = '0' and writeFlag = '1' then
+ writesignal <= '1';
+ else
+ writesignal <= '0';
end if;
+
+
end process;
PROC_COMBINEDREAD: process is
begin
- wait until rising_edge(clk_in);
+wait until rising_edge(clk_in);
last_amFull <= amFull;
if allow_write = '0' then
if read_cmd ='1' then
end if;
end process;
-
-
-
-
--- PROC_FIFOCLEAN: process is
--- -- wenn Almost full is TRUE--> start to read once and then wait for a couple cycles
--- begin
--- wait until rising_edge(clk_in);
--- if alertflag = '1' and waiter ='0' then
--- readsignal <= '1';
--- waiter <='1';
--- else
--- readsignal <= '0';
--- end if;
---
--- end process;
---
---
--- PROC_RESET: process is
--- begin
--- wait until rising_edge(clk_in);
--- if waiter = '1' and timer = x"0100" then
--- waiter <= '0';
--- timer <= x"0000";
--- elsif waiter ='1' and timer < x"0500" then
--- timer <= timer + 1;
--- end if;
---
--- end process;
AmFullThresh=> threshValue, -- AmFullThresh: in std_logic_vector(9 downto 0);
Q => output_val_handler, -- Q: out std_logic_vector(35 downto 0);
-- WCNT => -- WCNT: out std_logic_vector(10 downto 0);
--- Empty =>-- Empty: out std_logic;
+ Empty => emptyFlag,
-- Full =>-- Full: out std_logic;
AlmostFull => amFull -- AlmostFull: out std_logic);
);
jspc29 / trb3sc.git / commitdiff