cleanup of some code issues

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj
index 46ac233b7d427b59bf0e0e7478a0fee89cee34f6..79cb1dbb40e193f0c631fc980c1fd4034c8a9e13 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.prj
+++ b/32PinAddOn/trb3_periph_32PinAddOn.prj
@@ -113,7 +113,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+#add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
@@ -174,7 +174,7 @@ add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
 add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
+#add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
 add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"

diff --git a/base/code/input_to_trigger_logic.vhd b/base/code/input_to_trigger_logic.vhd
index 24eae34d7edaff7215a797313ccade730596848c..0284bec44d1f706a4f55bad05746f56c35083ce8 100644 (file)
--- a/base/code/input_to_trigger_logic.vhd
+++ b/base/code/input_to_trigger_logic.vhd
@@ -70,6 +70,7 @@ begin
         when "100"   =>  invert      <= DATA_IN(INPUTS-1 downto 0);
         when "101"   =>  coincidence1<= DATA_IN(INPUTS-1 downto 0);
         when "110"   =>  coincidence2<= DATA_IN(INPUTS-1 downto 0);
+        when others  =>  null;
       end case;
     else
       NACK_OUT <= '1'; 
@@ -126,4 +127,4 @@ out_reg <= output_i when rising_edge(CLK);
 
 OUTPUT  <= output_i;
 
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/base/code/sedcheck.vhd b/base/code/sedcheck.vhd
index c3754959ab53f3237ae524c50a45b5926888070e..51622163f8a9817c8910e02d90ee76c5a233da04 100644 (file)
--- a/base/code/sedcheck.vhd
+++ b/base/code/sedcheck.vhd
@@ -192,8 +192,8 @@ status_i(8)          <= sed_inprogress_q;
 status_i(9)          <= sed_error_q;
 status_i(10)         <= sed_edge;
 status_i(15 downto 11) <= (others => '0');
-status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0);
-status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0);
+status_i(23 downto 16) <= std_logic_vector(run_counter);
+status_i(31 downto 24) <= std_logic_vector(error_counter);
               
 ERROR_OUT <= sed_error;              
 DEBUG     <= status_i when rising_edge(CLK);