use work.trb_net_gbe_protocols.all;
entity gbe_logic_wrapper is
- generic(
- DO_SIMULATION : integer range 0 to 1;
- INCLUDE_DEBUG : integer range 0 to 1;
- USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1;
- RX_PATH_ENABLE : integer range 0 to 1;
- INCLUDE_READOUT : std_logic := '0';
- INCLUDE_SLOWCTRL : std_logic := '0';
- INCLUDE_DHCP : std_logic := '0';
- INCLUDE_ARP : std_logic := '0';
- INCLUDE_PING : std_logic := '0';
- INCLUDE_FWD : std_logic := '0';
- FRAME_BUFFER_SIZE : integer range 1 to 4 := 1;
- READOUT_BUFFER_SIZE : integer range 1 to 4 := 1;
- SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1;
- FIXED_SIZE_MODE : integer range 0 to 1 := 1;
- INCREMENTAL_MODE : integer range 0 to 1 := 0;
- FIXED_SIZE : integer range 0 to 65535 := 10;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- UP_DOWN_MODE : integer range 0 to 1 := 0;
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
- FIXED_DELAY : integer range 0 to 16777215 := 16777215
- );
- port(
- CLK_SYS_IN : in std_logic;
- CLK_125_IN : in std_logic;
- CLK_RX_125_IN : in std_logic;
- RESET : in std_logic;
- GSR_N : in std_logic;
- MY_MAC_IN : in std_logic_vector(47 downto 0);
- DHCP_DONE_OUT : out std_logic;
- MY_IP_OUT : out std_logic_vector(31 downto 0);
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
- ISSUE_REBOOT_OUT : out std_logic;
-
- -- connection to MAC
- MAC_READY_CONF_IN : in std_logic;
- MAC_RECONF_OUT : out std_logic;
- MAC_AN_READY_IN : in std_logic;
- MAC_FIFOAVAIL_OUT : out std_logic;
- MAC_FIFOEOF_OUT : out std_logic;
- MAC_FIFOEMPTY_OUT : out std_logic;
- MAC_RX_FIFOFULL_OUT : out std_logic;
- MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0);
- MAC_TX_READ_IN : in std_logic;
- MAC_TX_DISCRFRM_IN : in std_logic;
- MAC_TX_STAT_EN_IN : in std_logic;
- MAC_TX_STATS_IN : in std_logic_vector(30 downto 0);
- MAC_TX_DONE_IN : in std_logic;
- MAC_RX_FIFO_ERR_IN : in std_logic;
- MAC_RX_STATS_IN : in std_logic_vector(31 downto 0);
- MAC_RX_DATA_IN : in std_logic_vector(7 downto 0);
- MAC_RX_WRITE_IN : in std_logic;
- MAC_RX_STAT_EN_IN : in std_logic;
- MAC_RX_EOF_IN : in std_logic;
- MAC_RX_ERROR_IN : in std_logic;
-
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
- CTS_CODE_IN : in std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- SlowControl
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- -- IP configuration
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- -- configuration of gbe core
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_MAX_FRAME_IN : in std_logic_vector(15 downto 0);
- CFG_ALLOW_RX_IN : in std_logic;
- CFG_SOFT_RESET_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_ADDITIONAL_HDR_IN : in std_logic;
- CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
- CFG_AUTO_THROTTLE_IN : in std_logic;
- CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+ generic(
+ DO_SIMULATION : integer range 0 to 1;
+ INCLUDE_DEBUG : integer range 0 to 1;
+ USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1;
+ RX_PATH_ENABLE : integer range 0 to 1;
+ INCLUDE_READOUT : std_logic := '0';
+ INCLUDE_SLOWCTRL : std_logic := '0';
+ INCLUDE_DHCP : std_logic := '0';
+ INCLUDE_ARP : std_logic := '0';
+ INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
+ FRAME_BUFFER_SIZE : integer range 1 to 4 := 1;
+ READOUT_BUFFER_SIZE : integer range 1 to 4 := 1;
+ SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1;
+ FIXED_SIZE_MODE : integer range 0 to 1 := 1;
+ INCREMENTAL_MODE : integer range 0 to 1 := 0;
+ FIXED_SIZE : integer range 0 to 65535 := 10;
+ FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+ UP_DOWN_MODE : integer range 0 to 1 := 0;
+ UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
+ FIXED_DELAY : integer range 0 to 16777215 := 16777215
+ );
+ port(
+ CLK_SYS_IN : in std_logic;
+ CLK_125_IN : in std_logic;
+ CLK_RX_125_IN : in std_logic;
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ MY_MAC_IN : in std_logic_vector(47 downto 0);
+ DHCP_DONE_OUT : out std_logic;
+ MY_IP_OUT : out std_logic_vector(31 downto 0);
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+
+ -- connection to MAC
+ MAC_READY_CONF_IN : in std_logic;
+ MAC_RECONF_OUT : out std_logic;
+ MAC_AN_READY_IN : in std_logic;
+ MAC_FIFOAVAIL_OUT : out std_logic;
+ MAC_FIFOEOF_OUT : out std_logic;
+ MAC_FIFOEMPTY_OUT : out std_logic;
+ MAC_RX_FIFOFULL_OUT : out std_logic;
+ MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0);
+ MAC_TX_READ_IN : in std_logic;
+ MAC_TX_DISCRFRM_IN : in std_logic;
+ MAC_TX_STAT_EN_IN : in std_logic;
+ MAC_TX_STATS_IN : in std_logic_vector(30 downto 0);
+ MAC_TX_DONE_IN : in std_logic;
+ MAC_RX_FIFO_ERR_IN : in std_logic;
+ MAC_RX_STATS_IN : in std_logic_vector(31 downto 0);
+ MAC_RX_DATA_IN : in std_logic_vector(7 downto 0);
+ MAC_RX_WRITE_IN : in std_logic;
+ MAC_RX_STAT_EN_IN : in std_logic;
+ MAC_RX_EOF_IN : in std_logic;
+ MAC_RX_ERROR_IN : in std_logic;
+
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ -- SlowControl
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- IP configuration
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- configuration of gbe core
+ CFG_GBE_ENABLE_IN : in std_logic;
+ CFG_IPU_ENABLE_IN : in std_logic;
+ CFG_MULT_ENABLE_IN : in std_logic;
+ CFG_MAX_FRAME_IN : in std_logic_vector(15 downto 0);
+ CFG_ALLOW_RX_IN : in std_logic;
+ CFG_SOFT_RESET_IN : in std_logic;
+ CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
+ CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
+ CFG_READOUT_CTR_VALID_IN : in std_logic;
+ CFG_INSERT_TTYPE_IN : in std_logic;
+ CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_ADDITIONAL_HDR_IN : in std_logic;
+ CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
+ CFG_AUTO_THROTTLE_IN : in std_logic;
+ CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
-- Forwarder
- FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
- FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
- FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
- FWD_DATA_IN : in std_logic_vector(7 downto 0);
- FWD_DATA_VALID_IN : in std_logic;
- FWD_SOP_IN : in std_logic;
- FWD_EOP_IN : in std_logic;
- FWD_READY_OUT : out std_logic;
- FWD_FULL_OUT : out std_logic;
-
- MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0);
- MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0);
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);
- MONITOR_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MAKE_RESET_OUT : out std_logic
- );
+ FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
+ FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
+ FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
+ FWD_DATA_IN : in std_logic_vector(7 downto 0);
+ FWD_DATA_VALID_IN : in std_logic;
+ FWD_SOP_IN : in std_logic;
+ FWD_EOP_IN : in std_logic;
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+
+ MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);
+ MONITOR_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MAKE_RESET_OUT : out std_logic
+ );
end entity gbe_logic_wrapper;
architecture RTL of gbe_logic_wrapper is
- signal fr_q : std_logic_vector(8 downto 0);
- signal fr_rd_en : std_logic;
- signal fr_frame_valid : std_logic;
- signal rc_rd_en : std_logic;
- signal rc_q : std_logic_vector(8 downto 0);
- signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
- signal mc_data : std_logic_vector(8 downto 0);
- signal mc_wr_en : std_logic;
- signal fc_wr_en : std_logic;
- signal fc_data : std_logic_vector(7 downto 0);
- signal fc_ip_size : std_logic_vector(15 downto 0);
- signal fc_udp_size : std_logic_vector(15 downto 0);
- signal fc_ident : std_logic_vector(15 downto 0);
- signal fc_flags_offset : std_logic_vector(15 downto 0);
- signal fc_sod : std_logic;
- signal fc_eod : std_logic;
- signal fc_h_ready : std_logic;
- signal fc_ready : std_logic;
- signal rc_frame_ready : std_logic;
- signal fr_frame_size : std_logic_vector(15 downto 0);
- signal rc_frame_size : std_logic_vector(15 downto 0);
- signal mc_frame_size : std_logic_vector(15 downto 0);
- signal rc_bytes_rec : std_logic_vector(31 downto 0);
- signal rc_debug : std_logic_vector(63 downto 0);
- signal mc_transmit_ctrl : std_logic;
- signal rc_loading_done : std_logic;
- signal fr_get_frame : std_logic;
- signal mc_transmit_done : std_logic;
-
- signal fr_frame_proto : std_logic_vector(15 downto 0);
- signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- signal mc_type : std_logic_vector(15 downto 0);
- signal fr_src_mac : std_logic_vector(47 downto 0);
- signal fr_dest_mac : std_logic_vector(47 downto 0);
- signal fr_src_ip : std_logic_vector(31 downto 0);
- signal fr_dest_ip : std_logic_vector(31 downto 0);
- signal fr_src_udp : std_logic_vector(15 downto 0);
- signal fr_dest_udp : std_logic_vector(15 downto 0);
- signal rc_src_mac : std_logic_vector(47 downto 0);
- signal rc_dest_mac : std_logic_vector(47 downto 0);
- signal rc_src_ip : std_logic_vector(31 downto 0);
- signal rc_dest_ip : std_logic_vector(31 downto 0);
- signal rc_src_udp : std_logic_vector(15 downto 0);
- signal rc_dest_udp : std_logic_vector(15 downto 0);
-
- signal mc_dest_mac : std_logic_vector(47 downto 0);
- signal mc_dest_ip : std_logic_vector(31 downto 0);
- signal mc_dest_udp : std_logic_vector(15 downto 0);
- signal mc_src_mac : std_logic_vector(47 downto 0);
- signal mc_src_ip : std_logic_vector(31 downto 0);
- signal mc_src_udp : std_logic_vector(15 downto 0);
-
- signal fc_dest_mac : std_logic_vector(47 downto 0);
- signal fc_dest_ip : std_logic_vector(31 downto 0);
- signal fc_dest_udp : std_logic_vector(15 downto 0);
- signal fc_src_mac : std_logic_vector(47 downto 0);
- signal fc_src_ip : std_logic_vector(31 downto 0);
- signal fc_src_udp : std_logic_vector(15 downto 0);
- signal fc_type : std_logic_vector(15 downto 0);
- signal fc_ihl_version : std_logic_vector(7 downto 0);
- signal fc_tos : std_logic_vector(7 downto 0);
- signal fc_ttl : std_logic_vector(7 downto 0);
- signal fc_protocol : std_logic_vector(7 downto 0);
-
- signal ft_data : std_logic_vector(8 downto 0);
- signal ft_tx_empty : std_logic;
- signal ft_start_of_packet : std_logic;
- signal ft_bsm_init : std_logic_vector(3 downto 0);
- signal ft_bsm_mac : std_logic_vector(3 downto 0);
- signal ft_bsm_trans : std_logic_vector(3 downto 0);
-
- signal gbe_cts_number : std_logic_vector(15 downto 0);
- signal gbe_cts_code : std_logic_vector(7 downto 0);
- signal gbe_cts_information : std_logic_vector(7 downto 0);
- signal gbe_cts_start_readout : std_logic;
- signal gbe_cts_readout_type : std_logic_vector(3 downto 0);
- signal gbe_cts_readout_finished : std_logic;
- signal gbe_cts_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_data : std_logic_vector(15 downto 0);
- signal gbe_fee_dataready : std_logic;
- signal gbe_fee_read : std_logic;
- signal gbe_fee_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_busy : std_logic;
-
- signal fr_ip_proto : std_logic_vector(7 downto 0);
- signal mc_ip_proto : std_logic_vector(7 downto 0);
- signal mc_ident : std_logic_vector(15 downto 0);
-
- signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal dbg_select_gen : std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- signal global_reset, rst_n, ff : std_logic;
- signal link_ok, dhcp_done : std_logic;
-
- signal dum_busy, dum_read, dum_dataready : std_logic;
- signal dum_data : std_logic_vector(15 downto 0);
-
- signal monitor_tx_packets : std_logic_vector(31 downto 0);
- signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
-
- signal dbg_hist, dbg_hist2 : hist_array;
- signal monitor_dropped : std_logic_vector(31 downto 0);
- signal dbg_ft : std_logic_vector(63 downto 0);
- signal dbg_q : std_logic_vector(15 downto 0);
- signal make_reset : std_logic;
- signal frame_pause : std_logic_vector(31 downto 0);
+ signal fr_q : std_logic_vector(8 downto 0);
+ signal fr_rd_en : std_logic;
+ signal fr_frame_valid : std_logic;
+ signal rc_rd_en : std_logic;
+ signal rc_q : std_logic_vector(8 downto 0);
+ signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
+ signal mc_data : std_logic_vector(8 downto 0);
+ signal mc_wr_en : std_logic;
+ signal fc_wr_en : std_logic;
+ signal fc_data : std_logic_vector(7 downto 0);
+ signal fc_ip_size : std_logic_vector(15 downto 0);
+ signal fc_udp_size : std_logic_vector(15 downto 0);
+ signal fc_ident : std_logic_vector(15 downto 0);
+ signal fc_flags_offset : std_logic_vector(15 downto 0);
+ signal fc_sod : std_logic;
+ signal fc_eod : std_logic;
+ signal fc_h_ready : std_logic;
+ signal fc_ready : std_logic;
+ signal rc_frame_ready : std_logic;
+ signal fr_frame_size : std_logic_vector(15 downto 0);
+ signal rc_frame_size : std_logic_vector(15 downto 0);
+ signal mc_frame_size : std_logic_vector(15 downto 0);
+ signal rc_bytes_rec : std_logic_vector(31 downto 0);
+ signal rc_debug : std_logic_vector(63 downto 0);
+ signal mc_transmit_ctrl : std_logic;
+ signal rc_loading_done : std_logic;
+ signal fr_get_frame : std_logic;
+ signal mc_transmit_done : std_logic;
+
+ signal fr_frame_proto : std_logic_vector(15 downto 0);
+ signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+
+ signal mc_type : std_logic_vector(15 downto 0);
+ signal fr_src_mac : std_logic_vector(47 downto 0);
+ signal fr_dest_mac : std_logic_vector(47 downto 0);
+ signal fr_src_ip : std_logic_vector(31 downto 0);
+ signal fr_dest_ip : std_logic_vector(31 downto 0);
+ signal fr_src_udp : std_logic_vector(15 downto 0);
+ signal fr_dest_udp : std_logic_vector(15 downto 0);
+ signal rc_src_mac : std_logic_vector(47 downto 0);
+ signal rc_dest_mac : std_logic_vector(47 downto 0);
+ signal rc_src_ip : std_logic_vector(31 downto 0);
+ signal rc_dest_ip : std_logic_vector(31 downto 0);
+ signal rc_src_udp : std_logic_vector(15 downto 0);
+ signal rc_dest_udp : std_logic_vector(15 downto 0);
+
+ signal mc_dest_mac : std_logic_vector(47 downto 0);
+ signal mc_dest_ip : std_logic_vector(31 downto 0);
+ signal mc_dest_udp : std_logic_vector(15 downto 0);
+ signal mc_src_mac : std_logic_vector(47 downto 0);
+ signal mc_src_ip : std_logic_vector(31 downto 0);
+ signal mc_src_udp : std_logic_vector(15 downto 0);
+
+ signal fc_dest_mac : std_logic_vector(47 downto 0);
+ signal fc_dest_ip : std_logic_vector(31 downto 0);
+ signal fc_dest_udp : std_logic_vector(15 downto 0);
+ signal fc_src_mac : std_logic_vector(47 downto 0);
+ signal fc_src_ip : std_logic_vector(31 downto 0);
+ signal fc_src_udp : std_logic_vector(15 downto 0);
+ signal fc_type : std_logic_vector(15 downto 0);
+ signal fc_ihl_version : std_logic_vector(7 downto 0);
+ signal fc_tos : std_logic_vector(7 downto 0);
+ signal fc_ttl : std_logic_vector(7 downto 0);
+ signal fc_protocol : std_logic_vector(7 downto 0);
+
+ signal ft_data : std_logic_vector(8 downto 0);
+ signal ft_tx_empty : std_logic;
+ signal ft_start_of_packet : std_logic;
+ signal ft_bsm_init : std_logic_vector(3 downto 0);
+ signal ft_bsm_mac : std_logic_vector(3 downto 0);
+ signal ft_bsm_trans : std_logic_vector(3 downto 0);
+
+ signal gbe_cts_number : std_logic_vector(15 downto 0);
+ signal gbe_cts_code : std_logic_vector(7 downto 0);
+ signal gbe_cts_information : std_logic_vector(7 downto 0);
+ signal gbe_cts_start_readout : std_logic;
+ signal gbe_cts_readout_type : std_logic_vector(3 downto 0);
+ signal gbe_cts_readout_finished : std_logic;
+ signal gbe_cts_status_bits : std_logic_vector(31 downto 0);
+ signal gbe_fee_data : std_logic_vector(15 downto 0);
+ signal gbe_fee_dataready : std_logic;
+ signal gbe_fee_read : std_logic;
+ signal gbe_fee_status_bits : std_logic_vector(31 downto 0);
+ signal gbe_fee_busy : std_logic;
+
+ signal fr_ip_proto : std_logic_vector(7 downto 0);
+ signal mc_ip_proto : std_logic_vector(7 downto 0);
+ signal mc_ident : std_logic_vector(15 downto 0);
+
+ signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal dbg_select_gen : std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+
+ signal global_reset, rst_n, ff : std_logic;
+ signal link_ok, dhcp_done : std_logic;
+
+ signal dum_busy, dum_read, dum_dataready : std_logic;
+ signal dum_data : std_logic_vector(15 downto 0);
+
+ signal monitor_tx_packets : std_logic_vector(31 downto 0);
+ signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
+
+ signal dbg_hist, dbg_hist2 : hist_array;
+ signal monitor_dropped : std_logic_vector(31 downto 0);
+ signal dbg_ft : std_logic_vector(63 downto 0);
+ signal dbg_q : std_logic_vector(15 downto 0);
+ signal make_reset : std_logic;
+ signal frame_pause : std_logic_vector(31 downto 0);
begin
- reset_sync : process(GSR_N, CLK_SYS_IN)
- begin
- if (GSR_N = '0') then
- ff <= '0';
- rst_n <= '0';
- elsif rising_edge(CLK_SYS_IN) then
- ff <= '1';
- rst_n <= ff;
- end if;
- end process reset_sync;
-
- global_reset <= not rst_n;
-
- fc_ihl_version <= x"45";
- fc_tos <= x"10";
- fc_ttl <= x"ff";
-
- DHCP_DONE_OUT <= dhcp_done;
-
- main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
- MAIN_CONTROL : entity work.trb_net16_gbe_main_control
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_READOUT => INCLUDE_READOUT,
- INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
- INCLUDE_DHCP => INCLUDE_DHCP,
- INCLUDE_ARP => INCLUDE_ARP,
- INCLUDE_PING => INCLUDE_PING,
- INCLUDE_FWD => INCLUDE_FWD,
- READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
- SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
- )
- port map(
- CLK => CLK_SYS_IN,
- CLK_125 => CLK_125_IN,
- RESET => RESET,
- MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => global_reset,
- MC_IDLE_TOO_LONG_OUT => open,
- MC_DHCP_DONE_OUT => dhcp_done,
- MY_IP_OUT => MY_IP_OUT,
- MC_MY_MAC_IN => MY_MAC_IN,
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => open, --ISSUE_REBOOT_OUT,
-
- -- signals to/from receive controller
- RC_FRAME_WAITING_IN => rc_frame_ready,
- RC_LOADING_DONE_OUT => rc_loading_done,
- RC_DATA_IN => rc_q,
- RC_RD_EN_OUT => rc_rd_en,
- RC_FRAME_SIZE_IN => rc_frame_size,
- RC_FRAME_PROTO_IN => rc_frame_proto,
- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
- RC_SRC_UDP_PORT_IN => rc_src_udp,
- RC_DEST_UDP_PORT_IN => rc_dest_udp,
-
- -- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
- TC_DATA_OUT => mc_data,
- TC_RD_EN_IN => mc_wr_en,
- TC_FRAME_SIZE_OUT => mc_frame_size,
- TC_FRAME_TYPE_OUT => mc_type,
- TC_IP_PROTOCOL_OUT => mc_ip_proto,
- TC_IDENT_OUT => mc_ident,
- TC_DEST_MAC_OUT => mc_dest_mac,
- TC_DEST_IP_OUT => mc_dest_ip,
- TC_DEST_UDP_OUT => mc_dest_udp,
- TC_SRC_MAC_OUT => mc_src_mac,
- TC_SRC_IP_OUT => mc_src_ip,
- TC_SRC_UDP_OUT => mc_src_udp,
- TC_TRANSMIT_DONE_IN => mc_transmit_done,
-
- -- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN => MAC_AN_READY_IN,
-
- -- signals to/from hub
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
- MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
-
- RESET_TRBNET_IN => '0',
- RESET_SCTRL_IN => '0',
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
- CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
- CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
- CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
- CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
- CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
- CFG_AUTO_THROTTLE_IN => '0', --CFG_AUTO_THROTTLE_IN,
- CFG_THROTTLE_PAUSE_IN => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
-
- FWD_DST_MAC_IN => FWD_DST_MAC_IN,
- FWD_DST_IP_IN => FWD_DST_IP_IN,
- FWD_DST_UDP_IN => FWD_DST_UDP_IN,
- FWD_DATA_IN => FWD_DATA_IN,
- FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
- FWD_SOP_IN => FWD_SOP_IN,
- FWD_EOP_IN => FWD_EOP_IN,
- FWD_READY_OUT => FWD_READY_OUT,
- FWD_FULL_OUT => FWD_FULL_OUT,
-
- TSM_HADDR_OUT => open, --mac_haddr,
- TSM_HDATA_OUT => open, --mac_hdataout,
- TSM_HCS_N_OUT => open, --mac_hcs,
- TSM_HWRITE_N_OUT => open, --mac_hwrite,
- TSM_HREAD_N_OUT => open, --mac_hread,
- TSM_HREADY_N_IN => '0', --mac_hready,
- TSM_HDATA_EN_N_IN => '1', --mac_hdata_en,
- TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec,
- TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en,
-
- MAC_READY_CONF_IN => MAC_READY_CONF_IN,
- MAC_RECONF_OUT => MAC_RECONF_OUT,
- MONITOR_SELECT_REC_OUT => dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_OUT => dbg_select_sent,
- MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
- DATA_HIST_OUT => dbg_hist,
- SCTRL_HIST_OUT => dbg_hist2
- );
- end generate main_gen;
-
- main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
- MAIN_CONTROL : entity work.trb_net16_gbe_main_control
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_READOUT => INCLUDE_READOUT,
- INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
- INCLUDE_DHCP => INCLUDE_DHCP,
- INCLUDE_ARP => INCLUDE_ARP,
- INCLUDE_PING => INCLUDE_PING,
- INCLUDE_FWD => INCLUDE_FWD,
- READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
- SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
- )
- port map(
- CLK => CLK_SYS_IN,
- CLK_125 => CLK_125_IN,
- RESET => RESET,
- MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => global_reset,
- MC_IDLE_TOO_LONG_OUT => open,
- MC_DHCP_DONE_OUT => dhcp_done,
- MC_MY_MAC_IN => MY_MAC_IN,
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
-
- -- signals to/from receive controller
- RC_FRAME_WAITING_IN => rc_frame_ready,
- RC_LOADING_DONE_OUT => rc_loading_done,
- RC_DATA_IN => rc_q,
- RC_RD_EN_OUT => rc_rd_en,
- RC_FRAME_SIZE_IN => rc_frame_size,
- RC_FRAME_PROTO_IN => rc_frame_proto,
- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
- RC_SRC_UDP_PORT_IN => rc_src_udp,
- RC_DEST_UDP_PORT_IN => rc_dest_udp,
-
- -- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
- TC_DATA_OUT => mc_data,
- TC_RD_EN_IN => mc_wr_en,
- --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
- TC_FRAME_SIZE_OUT => mc_frame_size,
- TC_FRAME_TYPE_OUT => mc_type,
- TC_IP_PROTOCOL_OUT => mc_ip_proto,
- TC_IDENT_OUT => mc_ident,
- TC_DEST_MAC_OUT => mc_dest_mac,
- TC_DEST_IP_OUT => mc_dest_ip,
- TC_DEST_UDP_OUT => mc_dest_udp,
- TC_SRC_MAC_OUT => mc_src_mac,
- TC_SRC_IP_OUT => mc_src_ip,
- TC_SRC_UDP_OUT => mc_src_udp,
- TC_TRANSMIT_DONE_IN => mc_transmit_done,
-
- -- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN => MAC_AN_READY_IN,
-
- -- signals to/from hub
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => '1',
- GSC_REPLY_DATAREADY_IN => dum_dataready,
- GSC_REPLY_DATA_IN => dum_data,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => dum_read,
- GSC_BUSY_IN => dum_busy,
- MAKE_RESET_OUT => make_reset,
- RESET_TRBNET_IN => '0',
- RESET_SCTRL_IN => '0',
- -- CTS interface
- CTS_NUMBER_IN => gbe_cts_number,
- CTS_CODE_IN => gbe_cts_code,
- CTS_INFORMATION_IN => gbe_cts_information,
- CTS_READOUT_TYPE_IN => gbe_cts_readout_type,
- CTS_START_READOUT_IN => gbe_cts_start_readout,
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,
- CTS_READ_IN => '1',
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
- --Data payload interface
- FEE_DATA_IN => gbe_fee_data,
- FEE_DATAREADY_IN => gbe_fee_dataready,
- FEE_READ_OUT => gbe_fee_read,
- FEE_STATUS_BITS_IN => gbe_fee_status_bits,
- FEE_BUSY_IN => gbe_fee_busy,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- CFG_GBE_ENABLE_IN => '1',
- CFG_IPU_ENABLE_IN => '0',
- CFG_MULT_ENABLE_IN => '0',
- CFG_SUBEVENT_ID_IN => x"0000_00cf",
- CFG_SUBEVENT_DEC_IN => x"0002_0001",
- CFG_QUEUE_DEC_IN => x"0003_0062",
- CFG_READOUT_CTR_IN => x"00_0000",
- CFG_READOUT_CTR_VALID_IN => '0',
- CFG_INSERT_TTYPE_IN => '0',
- CFG_MAX_SUB_IN => x"e998", -- 59800
- CFG_MAX_QUEUE_IN => x"ea60", -- 60000
- CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200
- CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000
-
- CFG_ADDITIONAL_HDR_IN => '0',
- CFG_MAX_REPLY_SIZE_IN => x"0000_fa00",
- CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
- CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
-
- FWD_DST_MAC_IN => FWD_DST_MAC_IN,
- FWD_DST_IP_IN => FWD_DST_IP_IN,
- FWD_DST_UDP_IN => FWD_DST_UDP_IN,
- FWD_DATA_IN => FWD_DATA_IN,
- FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
- FWD_SOP_IN => FWD_SOP_IN,
- FWD_EOP_IN => FWD_EOP_IN,
- FWD_READY_OUT => FWD_READY_OUT,
- FWD_FULL_OUT => FWD_FULL_OUT,
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => open, --mac_haddr,
- TSM_HDATA_OUT => open, --mac_hdataout,
- TSM_HCS_N_OUT => open, --mac_hcs,
- TSM_HWRITE_N_OUT => open, --mac_hwrite,
- TSM_HREAD_N_OUT => open, --mac_hread,
- TSM_HREADY_N_IN => '0', --mac_hready,
- TSM_HDATA_EN_N_IN => '1', --mac_hdata_en,
- TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec,
- TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en,
-
- MAC_READY_CONF_IN => MAC_READY_CONF_IN,
- MAC_RECONF_OUT => MAC_RECONF_OUT,
- MONITOR_SELECT_REC_OUT => dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_OUT => dbg_select_sent,
- MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
- DATA_HIST_OUT => dbg_hist,
- SCTRL_HIST_OUT => dbg_hist2
- );
-
- dummy : gbe_ipu_dummy
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- FIXED_DELAY => FIXED_DELAY
- )
- port map(
- clk => CLK_SYS_IN,
- rst => RESET,
- GBE_READY_IN => dhcp_done,
- CFG_EVENT_SIZE_IN => (others => '0'),
- CFG_TRIGGERED_MODE_IN => '0',
- TRIGGER_IN => '0',
- CTS_NUMBER_OUT => gbe_cts_number,
- CTS_CODE_OUT => gbe_cts_code,
- CTS_INFORMATION_OUT => gbe_cts_information,
- CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,
- CTS_START_READOUT_OUT => gbe_cts_start_readout,
- CTS_DATA_IN => (others => '0'),
- CTS_DATAREADY_IN => '0',
- CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,
- CTS_READ_OUT => open,
- CTS_LENGTH_IN => (others => '0'),
- CTS_ERROR_PATTERN_IN => gbe_cts_status_bits,
- -- Data payload interfac =>
- FEE_DATA_OUT => gbe_fee_data,
- FEE_DATAREADY_OUT => gbe_fee_dataready,
- FEE_READ_IN => gbe_fee_read,
- FEE_STATUS_BITS_OUT => gbe_fee_status_bits,
- FEE_BUSY_OUT => gbe_fee_busy
- );
- end generate main_with_dummy_gen;
-
- MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
-
- transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
- TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset, --RESET,
-
- -- signal to/from main controller
- TC_DATAREADY_IN => mc_transmit_ctrl,
- TC_RD_EN_OUT => mc_wr_en,
- TC_DATA_IN => mc_data(7 downto 0),
- TC_FRAME_SIZE_IN => mc_frame_size,
- TC_FRAME_TYPE_IN => mc_type,
- TC_IP_PROTOCOL_IN => mc_ip_proto,
- TC_DEST_MAC_IN => mc_dest_mac,
- TC_DEST_IP_IN => mc_dest_ip,
- TC_DEST_UDP_IN => mc_dest_udp,
- TC_SRC_MAC_IN => mc_src_mac,
- TC_SRC_IP_IN => mc_src_ip,
- TC_SRC_UDP_IN => mc_src_udp,
- TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
- TC_IDENT_IN => mc_ident,
- TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN,
-
- -- signal to/from frame constructor
- FC_DATA_OUT => fc_data,
- FC_WR_EN_OUT => fc_wr_en,
- FC_READY_IN => fc_ready,
- FC_H_READY_IN => fc_h_ready,
- FC_FRAME_TYPE_OUT => fc_type,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- FC_IP_PROTOCOL_OUT => fc_protocol,
- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
- DEST_IP_ADDRESS_OUT => fc_dest_ip,
- DEST_UDP_PORT_OUT => fc_dest_udp,
- SRC_MAC_ADDRESS_OUT => fc_src_mac,
- SRC_IP_ADDRESS_OUT => fc_src_ip,
- SRC_UDP_PORT_OUT => fc_src_udp,
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets
- );
- end generate transmit_gen;
-
- transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
- TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset, --RESET,
-
- -- signal to/from main controller
- TC_DATAREADY_IN => mc_transmit_ctrl,
- TC_RD_EN_OUT => mc_wr_en,
- TC_DATA_IN => mc_data(7 downto 0),
- TC_FRAME_SIZE_IN => mc_frame_size,
- TC_FRAME_TYPE_IN => mc_type,
- TC_IP_PROTOCOL_IN => mc_ip_proto,
- TC_DEST_MAC_IN => mc_dest_mac,
- TC_DEST_IP_IN => mc_dest_ip,
- TC_DEST_UDP_IN => mc_dest_udp,
- TC_SRC_MAC_IN => mc_src_mac,
- TC_SRC_IP_IN => mc_src_ip,
- TC_SRC_UDP_IN => mc_src_udp,
- TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
- TC_IDENT_IN => mc_ident,
- TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN,
-
- -- signal to/from frame constructor
- FC_DATA_OUT => fc_data,
- FC_WR_EN_OUT => fc_wr_en,
- FC_READY_IN => fc_ready,
- FC_H_READY_IN => fc_h_ready,
- FC_FRAME_TYPE_OUT => fc_type,
- FC_IP_SIZE_OUT => fc_ip_size,
- FC_UDP_SIZE_OUT => fc_udp_size,
- FC_IDENT_OUT => fc_ident,
- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
- FC_SOD_OUT => fc_sod,
- FC_EOD_OUT => fc_eod,
- FC_IP_PROTOCOL_OUT => fc_protocol,
- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
- DEST_IP_ADDRESS_OUT => fc_dest_ip,
- DEST_UDP_PORT_OUT => fc_dest_udp,
- SRC_MAC_ADDRESS_OUT => fc_src_mac,
- SRC_IP_ADDRESS_OUT => fc_src_ip,
- SRC_UDP_PORT_OUT => fc_src_udp,
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets
- );
- end generate transmit_with_dummy_gen;
-
- FRAME_CONSTRUCTOR : trb_net16_gbe_frame_constr
- generic map(
- FRAME_BUFFER_SIZE => FRAME_BUFFER_SIZE
- )
- port map(
- -- ports for user logic
- RESET => global_reset,
- CLK => CLK_SYS_IN,
- LINK_OK_IN => '1',
- --
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
- START_OF_DATA_IN => fc_sod,
- END_OF_DATA_IN => fc_eod,
- IP_F_SIZE_IN => fc_ip_size,
- UDP_P_SIZE_IN => fc_udp_size,
- HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
- DEST_MAC_ADDRESS_IN => fc_dest_mac,
- DEST_IP_ADDRESS_IN => fc_dest_ip,
- DEST_UDP_PORT_IN => fc_dest_udp,
- SRC_MAC_ADDRESS_IN => fc_src_mac,
- SRC_IP_ADDRESS_IN => fc_src_ip,
- SRC_UDP_PORT_IN => fc_src_udp,
- FRAME_TYPE_IN => fc_type,
- IHL_VERSION_IN => fc_ihl_version,
- TOS_IN => fc_tos,
- IDENTIFICATION_IN => fc_ident,
- FLAGS_OFFSET_IN => fc_flags_offset,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_protocol,
- FRAME_DELAY_IN => frame_pause, --(others => '0'),
- RD_CLK => CLK_125_IN,
- FT_DATA_OUT => ft_data,
- FT_TX_EMPTY_OUT => ft_tx_empty,
- FT_TX_RD_EN_IN => MAC_TX_READ_IN,
- FT_START_OF_PACKET_OUT => ft_start_of_packet,
- FT_TX_DONE_IN => MAC_TX_DONE_IN,
- FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames
- );
-
- frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
-
- MAC_TX_DATA_OUT <= ft_data(7 downto 0);
-
- dbg_q(15 downto 9) <= (others => '0');
-
- FRAME_TRANSMITTER : trb_net16_gbe_frame_trans
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset,
- LINK_OK_IN => link_ok,
- TX_MAC_CLK => CLK_125_IN,
- TX_EMPTY_IN => ft_tx_empty,
- START_OF_PACKET_IN => ft_start_of_packet,
- DATA_ENDFLAG_IN => ft_data(8),
- TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT,
- TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT,
- TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT,
- TX_DONE_IN => MAC_TX_DONE_IN,
- TX_STAT_EN_IN => MAC_TX_STAT_EN_IN,
- TX_STATVEC_IN => MAC_TX_STATS_IN,
- TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
- -- Debug
- BSM_INIT_OUT => ft_bsm_init,
- BSM_MAC_OUT => ft_bsm_mac,
- BSM_TRANS_OUT => ft_bsm_trans,
- DBG_RD_DONE_OUT => open,
- DBG_INIT_DONE_OUT => open,
- DBG_ENABLED_OUT => open,
- DEBUG_OUT => dbg_ft
- );
-
- rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
- RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset,
-
- -- signals to/from frame_receiver
- RC_DATA_IN => fr_q,
- FR_RD_EN_OUT => fr_rd_en,
- FR_FRAME_VALID_IN => fr_frame_valid,
- FR_GET_FRAME_OUT => fr_get_frame,
- FR_FRAME_SIZE_IN => fr_frame_size,
- FR_FRAME_PROTO_IN => fr_frame_proto,
- FR_IP_PROTOCOL_IN => fr_ip_proto,
- FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
- FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
- FR_SRC_IP_ADDRESS_IN => fr_src_ip,
- FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
- FR_SRC_UDP_PORT_IN => fr_src_udp,
- FR_DEST_UDP_PORT_IN => fr_dest_udp,
-
- -- signals to/from main controller
- RC_RD_EN_IN => rc_rd_en,
- RC_Q_OUT => rc_q,
- RC_FRAME_WAITING_OUT => rc_frame_ready,
- RC_LOADING_DONE_IN => rc_loading_done,
- RC_FRAME_SIZE_OUT => rc_frame_size,
- RC_FRAME_PROTO_OUT => rc_frame_proto,
- RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
- RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
- RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
- RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
- RC_SRC_UDP_PORT_OUT => rc_src_udp,
- RC_DEST_UDP_PORT_OUT => rc_dest_udp,
-
- -- statistics
- FRAMES_RECEIVED_OUT => rc_frames_rec_ctr,
- BYTES_RECEIVED_OUT => rc_bytes_rec,
- DEBUG_OUT => rc_debug
- );
-
- FRAME_RECEIVER : trb_net16_gbe_frame_receiver
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset,
- LINK_OK_IN => link_ok,
- ALLOW_RX_IN => CFG_ALLOW_RX_IN,
- RX_MAC_CLK => CLK_RX_125_IN,
- MY_MAC_IN => MY_MAC_IN,
-
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
-
- -- input signals from TS_MAC
- MAC_RX_EOF_IN => MAC_RX_EOF_IN,
- MAC_RX_ER_IN => MAC_RX_ERROR_IN,
- MAC_RXD_IN => MAC_RX_DATA_IN,
- MAC_RX_EN_IN => MAC_RX_WRITE_IN,
- MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN,
- MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT,
- MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN,
- MAC_RX_STAT_VEC_IN => MAC_RX_STATS_IN,
- -- output signal to control logic
- FR_Q_OUT => fr_q,
- FR_RD_EN_IN => fr_rd_en,
- FR_FRAME_VALID_OUT => fr_frame_valid,
- FR_GET_FRAME_IN => fr_get_frame,
- FR_FRAME_SIZE_OUT => fr_frame_size,
- FR_FRAME_PROTO_OUT => fr_frame_proto,
- FR_IP_PROTOCOL_OUT => fr_ip_proto,
- FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types,
- FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip,
- FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp,
- FR_VLAN_ID_IN => (others => '0'), --vlan_id,
-
- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
- FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
- FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
- FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
- FR_SRC_UDP_PORT_OUT => fr_src_udp,
- FR_DEST_UDP_PORT_OUT => fr_dest_udp,
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
- MONITOR_DROPPED_OUT => monitor_dropped
- );
-
- end generate rx_enable_gen;
-
- rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
- rc_q <= (others => '0');
- rc_frame_ready <= '0';
- rc_frame_size <= (others => '0');
- rc_frame_proto <= (others => '0');
-
- rc_src_mac <= (others => '0');
- rc_dest_mac <= (others => '0');
- rc_src_ip <= (others => '0');
- rc_dest_ip <= (others => '0');
- rc_src_udp <= (others => '0');
- rc_dest_udp <= (others => '0');
-
- rc_frames_rec_ctr <= (others => '0');
- rc_bytes_rec <= (others => '0');
- rc_debug <= (others => '0');
-
- monitor_rx_bytes <= (others => '0');
- monitor_rx_frames <= (others => '0');
- monitor_dropped <= (others => '0');
-
- end generate rx_disable_gen;
-
- MONITOR_RX_FRAMES_OUT <= monitor_rx_frames;
- MONITOR_RX_BYTES_OUT <= monitor_rx_bytes;
- MONITOR_TX_FRAMES_OUT <= monitor_tx_frames;
- MONITOR_TX_BYTES_OUT <= monitor_tx_bytes;
- MONITOR_TX_PACKETS_OUT <= monitor_tx_packets;
- MONITOR_DROPPED_OUT <= monitor_dropped;
-
- MONITOR_GEN_DBG_OUT <= dbg_select_gen;
+ reset_sync : process(GSR_N, CLK_SYS_IN)
+ begin
+ if (GSR_N = '0') then
+ ff <= '0';
+ rst_n <= '0';
+ elsif rising_edge(CLK_SYS_IN) then
+ ff <= '1';
+ rst_n <= ff;
+ end if;
+ end process reset_sync;
+
+ global_reset <= not rst_n;
+
+ fc_ihl_version <= x"45";
+ fc_tos <= x"10";
+ fc_ttl <= x"ff";
+
+ DHCP_DONE_OUT <= dhcp_done;
+
+ main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
+ MAIN_CONTROL : entity work.trb_net16_gbe_main_control
+ generic map(
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_READOUT => INCLUDE_READOUT,
+ INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
+ INCLUDE_DHCP => INCLUDE_DHCP,
+ INCLUDE_ARP => INCLUDE_ARP,
+ INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
+ READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
+ SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
+ )
+ port map(
+ CLK => CLK_SYS_IN,
+ CLK_125 => CLK_125_IN,
+ RESET => RESET,
+ MC_LINK_OK_OUT => link_ok,
+ MC_RESET_LINK_IN => global_reset,
+ MC_IDLE_TOO_LONG_OUT => open,
+ MC_DHCP_DONE_OUT => dhcp_done,
+ MY_IP_OUT => MY_IP_OUT,
+ MC_MY_MAC_IN => MY_MAC_IN,
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => open, --ISSUE_REBOOT_OUT,
+
+ -- signals to/from receive controller
+ RC_FRAME_WAITING_IN => rc_frame_ready,
+ RC_LOADING_DONE_OUT => rc_loading_done,
+ RC_DATA_IN => rc_q,
+ RC_RD_EN_OUT => rc_rd_en,
+ RC_FRAME_SIZE_IN => rc_frame_size,
+ RC_FRAME_PROTO_IN => rc_frame_proto,
+ RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
+ RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
+ RC_SRC_IP_ADDRESS_IN => rc_src_ip,
+ RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
+ RC_SRC_UDP_PORT_IN => rc_src_udp,
+ RC_DEST_UDP_PORT_IN => rc_dest_udp,
+
+ -- signals to/from transmit controller
+ TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
+ TC_DATA_OUT => mc_data,
+ TC_RD_EN_IN => mc_wr_en,
+ TC_FRAME_SIZE_OUT => mc_frame_size,
+ TC_FRAME_TYPE_OUT => mc_type,
+ TC_IP_PROTOCOL_OUT => mc_ip_proto,
+ TC_IDENT_OUT => mc_ident,
+ TC_DEST_MAC_OUT => mc_dest_mac,
+ TC_DEST_IP_OUT => mc_dest_ip,
+ TC_DEST_UDP_OUT => mc_dest_udp,
+ TC_SRC_MAC_OUT => mc_src_mac,
+ TC_SRC_IP_OUT => mc_src_ip,
+ TC_SRC_UDP_OUT => mc_src_udp,
+ TC_TRANSMIT_DONE_IN => mc_transmit_done,
+
+ -- signals to/from sgmii/gbe pcs_an_complete
+ PCS_AN_COMPLETE_IN => MAC_AN_READY_IN,
+
+ -- signals to/from hub
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+ MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
+
+ RESET_TRBNET_IN => '0',
+ RESET_SCTRL_IN => '0',
+
+ -- CTS interface
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data payload interface
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- ip configurator
+ SLV_ADDR_IN => SLV_ADDR_IN,
+ SLV_READ_IN => SLV_READ_IN,
+ SLV_WRITE_IN => SLV_WRITE_IN,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT,
+ SLV_DATA_IN => SLV_DATA_IN,
+ SLV_DATA_OUT => SLV_DATA_OUT,
+ CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
+ CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
+ CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
+ CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
+ CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
+ CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
+ CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
+ CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
+ CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
+ CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
+ CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
+ CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
+ CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
+ CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
+ CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
+ CFG_AUTO_THROTTLE_IN => '0', --CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
+
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN,
+ FWD_DST_IP_IN => FWD_DST_IP_IN,
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+ TSM_HADDR_OUT => open, --mac_haddr,
+ TSM_HDATA_OUT => open, --mac_hdataout,
+ TSM_HCS_N_OUT => open, --mac_hcs,
+ TSM_HWRITE_N_OUT => open, --mac_hwrite,
+ TSM_HREAD_N_OUT => open, --mac_hread,
+ TSM_HREADY_N_IN => '0', --mac_hready,
+ TSM_HDATA_EN_N_IN => '1', --mac_hdata_en,
+ TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec,
+ TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en,
+
+ MAC_READY_CONF_IN => MAC_READY_CONF_IN,
+ MAC_RECONF_OUT => MAC_RECONF_OUT,
+ MONITOR_SELECT_REC_OUT => dbg_select_rec,
+ MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
+ MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
+ MONITOR_SELECT_SENT_OUT => dbg_select_sent,
+ MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
+ MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
+ MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
+ DATA_HIST_OUT => dbg_hist,
+ SCTRL_HIST_OUT => dbg_hist2
+ );
+ end generate main_gen;
+
+ main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
+ MAIN_CONTROL : entity work.trb_net16_gbe_main_control
+ generic map(
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_READOUT => INCLUDE_READOUT,
+ INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
+ INCLUDE_DHCP => INCLUDE_DHCP,
+ INCLUDE_ARP => INCLUDE_ARP,
+ INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
+ READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
+ SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
+ )
+ port map(
+ CLK => CLK_SYS_IN,
+ CLK_125 => CLK_125_IN,
+ RESET => RESET,
+ MC_LINK_OK_OUT => link_ok,
+ MC_RESET_LINK_IN => global_reset,
+ MC_IDLE_TOO_LONG_OUT => open,
+ MC_DHCP_DONE_OUT => dhcp_done,
+ MC_MY_MAC_IN => MY_MAC_IN,
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+
+ -- signals to/from receive controller
+ RC_FRAME_WAITING_IN => rc_frame_ready,
+ RC_LOADING_DONE_OUT => rc_loading_done,
+ RC_DATA_IN => rc_q,
+ RC_RD_EN_OUT => rc_rd_en,
+ RC_FRAME_SIZE_IN => rc_frame_size,
+ RC_FRAME_PROTO_IN => rc_frame_proto,
+ RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
+ RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
+ RC_SRC_IP_ADDRESS_IN => rc_src_ip,
+ RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
+ RC_SRC_UDP_PORT_IN => rc_src_udp,
+ RC_DEST_UDP_PORT_IN => rc_dest_udp,
+
+ -- signals to/from transmit controller
+ TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
+ TC_DATA_OUT => mc_data,
+ TC_RD_EN_IN => mc_wr_en,
+ --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
+ TC_FRAME_SIZE_OUT => mc_frame_size,
+ TC_FRAME_TYPE_OUT => mc_type,
+ TC_IP_PROTOCOL_OUT => mc_ip_proto,
+ TC_IDENT_OUT => mc_ident,
+ TC_DEST_MAC_OUT => mc_dest_mac,
+ TC_DEST_IP_OUT => mc_dest_ip,
+ TC_DEST_UDP_OUT => mc_dest_udp,
+ TC_SRC_MAC_OUT => mc_src_mac,
+ TC_SRC_IP_OUT => mc_src_ip,
+ TC_SRC_UDP_OUT => mc_src_udp,
+ TC_TRANSMIT_DONE_IN => mc_transmit_done,
+
+ -- signals to/from sgmii/gbe pcs_an_complete
+ PCS_AN_COMPLETE_IN => MAC_AN_READY_IN,
+
+ -- signals to/from hub
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => '1',
+ GSC_REPLY_DATAREADY_IN => dum_dataready,
+ GSC_REPLY_DATA_IN => dum_data,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => dum_read,
+ GSC_BUSY_IN => dum_busy,
+ MAKE_RESET_OUT => make_reset,
+ RESET_TRBNET_IN => '0',
+ RESET_SCTRL_IN => '0',
+ -- CTS interface
+ CTS_NUMBER_IN => gbe_cts_number,
+ CTS_CODE_IN => gbe_cts_code,
+ CTS_INFORMATION_IN => gbe_cts_information,
+ CTS_READOUT_TYPE_IN => gbe_cts_readout_type,
+ CTS_START_READOUT_IN => gbe_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits,
+ --Data payload interface
+ FEE_DATA_IN => gbe_fee_data,
+ FEE_DATAREADY_IN => gbe_fee_dataready,
+ FEE_READ_OUT => gbe_fee_read,
+ FEE_STATUS_BITS_IN => gbe_fee_status_bits,
+ FEE_BUSY_IN => gbe_fee_busy,
+ -- ip configurator
+ SLV_ADDR_IN => SLV_ADDR_IN,
+ SLV_READ_IN => SLV_READ_IN,
+ SLV_WRITE_IN => SLV_WRITE_IN,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT,
+ SLV_DATA_IN => SLV_DATA_IN,
+ SLV_DATA_OUT => SLV_DATA_OUT,
+ CFG_GBE_ENABLE_IN => '1',
+ CFG_IPU_ENABLE_IN => '0',
+ CFG_MULT_ENABLE_IN => '0',
+ CFG_SUBEVENT_ID_IN => x"0000_00cf",
+ CFG_SUBEVENT_DEC_IN => x"0002_0001",
+ CFG_QUEUE_DEC_IN => x"0003_0062",
+ CFG_READOUT_CTR_IN => x"00_0000",
+ CFG_READOUT_CTR_VALID_IN => '0',
+ CFG_INSERT_TTYPE_IN => '0',
+ CFG_MAX_SUB_IN => x"e998", -- 59800
+ CFG_MAX_QUEUE_IN => x"ea60", -- 60000
+ CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200
+ CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000
+
+ CFG_ADDITIONAL_HDR_IN => '0',
+ CFG_MAX_REPLY_SIZE_IN => x"0000_fa00",
+ CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN,
+ FWD_DST_IP_IN => FWD_DST_IP_IN,
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => open, --mac_haddr,
+ TSM_HDATA_OUT => open, --mac_hdataout,
+ TSM_HCS_N_OUT => open, --mac_hcs,
+ TSM_HWRITE_N_OUT => open, --mac_hwrite,
+ TSM_HREAD_N_OUT => open, --mac_hread,
+ TSM_HREADY_N_IN => '0', --mac_hready,
+ TSM_HDATA_EN_N_IN => '1', --mac_hdata_en,
+ TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec,
+ TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en,
+
+ MAC_READY_CONF_IN => MAC_READY_CONF_IN,
+ MAC_RECONF_OUT => MAC_RECONF_OUT,
+ MONITOR_SELECT_REC_OUT => dbg_select_rec,
+ MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes,
+ MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes,
+ MONITOR_SELECT_SENT_OUT => dbg_select_sent,
+ MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in,
+ MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out,
+ MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen,
+ DATA_HIST_OUT => dbg_hist,
+ SCTRL_HIST_OUT => dbg_hist2
+ );
+
+ dummy : gbe_ipu_dummy
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ FIXED_DELAY => FIXED_DELAY
+ )
+ port map(
+ clk => CLK_SYS_IN,
+ rst => RESET,
+ GBE_READY_IN => dhcp_done,
+ CFG_EVENT_SIZE_IN => (others => '0'),
+ CFG_TRIGGERED_MODE_IN => '0',
+ TRIGGER_IN => '0',
+ CTS_NUMBER_OUT => gbe_cts_number,
+ CTS_CODE_OUT => gbe_cts_code,
+ CTS_INFORMATION_OUT => gbe_cts_information,
+ CTS_READOUT_TYPE_OUT => gbe_cts_readout_type,
+ CTS_START_READOUT_OUT => gbe_cts_start_readout,
+ CTS_DATA_IN => (others => '0'),
+ CTS_DATAREADY_IN => '0',
+ CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished,
+ CTS_READ_OUT => open,
+ CTS_LENGTH_IN => (others => '0'),
+ CTS_ERROR_PATTERN_IN => gbe_cts_status_bits,
+ -- Data payload interfac =>
+ FEE_DATA_OUT => gbe_fee_data,
+ FEE_DATAREADY_OUT => gbe_fee_dataready,
+ FEE_READ_IN => gbe_fee_read,
+ FEE_STATUS_BITS_OUT => gbe_fee_status_bits,
+ FEE_BUSY_OUT => gbe_fee_busy
+ );
+ end generate main_with_dummy_gen;
+
+ MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
+
+ transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
+ TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => global_reset, --RESET,
+
+ -- signal to/from main controller
+ TC_DATAREADY_IN => mc_transmit_ctrl,
+ TC_RD_EN_OUT => mc_wr_en,
+ TC_DATA_IN => mc_data(7 downto 0),
+ TC_FRAME_SIZE_IN => mc_frame_size,
+ TC_FRAME_TYPE_IN => mc_type,
+ TC_IP_PROTOCOL_IN => mc_ip_proto,
+ TC_DEST_MAC_IN => mc_dest_mac,
+ TC_DEST_IP_IN => mc_dest_ip,
+ TC_DEST_UDP_IN => mc_dest_udp,
+ TC_SRC_MAC_IN => mc_src_mac,
+ TC_SRC_IP_IN => mc_src_ip,
+ TC_SRC_UDP_IN => mc_src_udp,
+ TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
+ TC_IDENT_IN => mc_ident,
+ TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN,
+
+ -- signal to/from frame constructor
+ FC_DATA_OUT => fc_data,
+ FC_WR_EN_OUT => fc_wr_en,
+ FC_READY_IN => fc_ready,
+ FC_H_READY_IN => fc_h_ready,
+ FC_FRAME_TYPE_OUT => fc_type,
+ FC_IP_SIZE_OUT => fc_ip_size,
+ FC_UDP_SIZE_OUT => fc_udp_size,
+ FC_IDENT_OUT => fc_ident,
+ FC_FLAGS_OFFSET_OUT => fc_flags_offset,
+ FC_SOD_OUT => fc_sod,
+ FC_EOD_OUT => fc_eod,
+ FC_IP_PROTOCOL_OUT => fc_protocol,
+ DEST_MAC_ADDRESS_OUT => fc_dest_mac,
+ DEST_IP_ADDRESS_OUT => fc_dest_ip,
+ DEST_UDP_PORT_OUT => fc_dest_udp,
+ SRC_MAC_ADDRESS_OUT => fc_src_mac,
+ SRC_IP_ADDRESS_OUT => fc_src_ip,
+ SRC_UDP_PORT_OUT => fc_src_udp,
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets
+ );
+ end generate transmit_gen;
+
+ transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
+ TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => global_reset, --RESET,
+
+ -- signal to/from main controller
+ TC_DATAREADY_IN => mc_transmit_ctrl,
+ TC_RD_EN_OUT => mc_wr_en,
+ TC_DATA_IN => mc_data(7 downto 0),
+ TC_FRAME_SIZE_IN => mc_frame_size,
+ TC_FRAME_TYPE_IN => mc_type,
+ TC_IP_PROTOCOL_IN => mc_ip_proto,
+ TC_DEST_MAC_IN => mc_dest_mac,
+ TC_DEST_IP_IN => mc_dest_ip,
+ TC_DEST_UDP_IN => mc_dest_udp,
+ TC_SRC_MAC_IN => mc_src_mac,
+ TC_SRC_IP_IN => mc_src_ip,
+ TC_SRC_UDP_IN => mc_src_udp,
+ TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
+ TC_IDENT_IN => mc_ident,
+ TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN,
+
+ -- signal to/from frame constructor
+ FC_DATA_OUT => fc_data,
+ FC_WR_EN_OUT => fc_wr_en,
+ FC_READY_IN => fc_ready,
+ FC_H_READY_IN => fc_h_ready,
+ FC_FRAME_TYPE_OUT => fc_type,
+ FC_IP_SIZE_OUT => fc_ip_size,
+ FC_UDP_SIZE_OUT => fc_udp_size,
+ FC_IDENT_OUT => fc_ident,
+ FC_FLAGS_OFFSET_OUT => fc_flags_offset,
+ FC_SOD_OUT => fc_sod,
+ FC_EOD_OUT => fc_eod,
+ FC_IP_PROTOCOL_OUT => fc_protocol,
+ DEST_MAC_ADDRESS_OUT => fc_dest_mac,
+ DEST_IP_ADDRESS_OUT => fc_dest_ip,
+ DEST_UDP_PORT_OUT => fc_dest_udp,
+ SRC_MAC_ADDRESS_OUT => fc_src_mac,
+ SRC_IP_ADDRESS_OUT => fc_src_ip,
+ SRC_UDP_PORT_OUT => fc_src_udp,
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets
+ );
+ end generate transmit_with_dummy_gen;
+
+ FRAME_CONSTRUCTOR : trb_net16_gbe_frame_constr
+ generic map(
+ FRAME_BUFFER_SIZE => FRAME_BUFFER_SIZE
+ )
+ port map(
+ -- ports for user logic
+ RESET => global_reset,
+ CLK => CLK_SYS_IN,
+ LINK_OK_IN => '1',
+ --
+ WR_EN_IN => fc_wr_en,
+ DATA_IN => fc_data,
+ START_OF_DATA_IN => fc_sod,
+ END_OF_DATA_IN => fc_eod,
+ IP_F_SIZE_IN => fc_ip_size,
+ UDP_P_SIZE_IN => fc_udp_size,
+ HEADERS_READY_OUT => fc_h_ready,
+ READY_OUT => fc_ready,
+ DEST_MAC_ADDRESS_IN => fc_dest_mac,
+ DEST_IP_ADDRESS_IN => fc_dest_ip,
+ DEST_UDP_PORT_IN => fc_dest_udp,
+ SRC_MAC_ADDRESS_IN => fc_src_mac,
+ SRC_IP_ADDRESS_IN => fc_src_ip,
+ SRC_UDP_PORT_IN => fc_src_udp,
+ FRAME_TYPE_IN => fc_type,
+ IHL_VERSION_IN => fc_ihl_version,
+ TOS_IN => fc_tos,
+ IDENTIFICATION_IN => fc_ident,
+ FLAGS_OFFSET_IN => fc_flags_offset,
+ TTL_IN => fc_ttl,
+ PROTOCOL_IN => fc_protocol,
+ FRAME_DELAY_IN => frame_pause, --(others => '0'),
+ RD_CLK => CLK_125_IN,
+ FT_DATA_OUT => ft_data,
+ FT_TX_EMPTY_OUT => ft_tx_empty,
+ FT_TX_RD_EN_IN => MAC_TX_READ_IN,
+ FT_START_OF_PACKET_OUT => ft_start_of_packet,
+ FT_TX_DONE_IN => MAC_TX_DONE_IN,
+ FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames
+ );
+
+ frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
+
+ MAC_TX_DATA_OUT <= ft_data(7 downto 0);
+
+ dbg_q(15 downto 9) <= (others => '0');
+
+ FRAME_TRANSMITTER : trb_net16_gbe_frame_trans
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => global_reset,
+ LINK_OK_IN => link_ok,
+ TX_MAC_CLK => CLK_125_IN,
+ TX_EMPTY_IN => ft_tx_empty,
+ START_OF_PACKET_IN => ft_start_of_packet,
+ DATA_ENDFLAG_IN => ft_data(8),
+ TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT,
+ TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT,
+ TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT,
+ TX_DONE_IN => MAC_TX_DONE_IN,
+ TX_STAT_EN_IN => MAC_TX_STAT_EN_IN,
+ TX_STATVEC_IN => MAC_TX_STATS_IN,
+ TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
+ -- Debug
+ BSM_INIT_OUT => ft_bsm_init,
+ BSM_MAC_OUT => ft_bsm_mac,
+ BSM_TRANS_OUT => ft_bsm_trans,
+ DBG_RD_DONE_OUT => open,
+ DBG_INIT_DONE_OUT => open,
+ DBG_ENABLED_OUT => open,
+ DEBUG_OUT => dbg_ft
+ );
+
+ rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
+ RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => global_reset,
+
+ -- signals to/from frame_receiver
+ RC_DATA_IN => fr_q,
+ FR_RD_EN_OUT => fr_rd_en,
+ FR_FRAME_VALID_IN => fr_frame_valid,
+ FR_GET_FRAME_OUT => fr_get_frame,
+ FR_FRAME_SIZE_IN => fr_frame_size,
+ FR_FRAME_PROTO_IN => fr_frame_proto,
+ FR_IP_PROTOCOL_IN => fr_ip_proto,
+ FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
+ FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
+ FR_SRC_IP_ADDRESS_IN => fr_src_ip,
+ FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
+ FR_SRC_UDP_PORT_IN => fr_src_udp,
+ FR_DEST_UDP_PORT_IN => fr_dest_udp,
+
+ -- signals to/from main controller
+ RC_RD_EN_IN => rc_rd_en,
+ RC_Q_OUT => rc_q,
+ RC_FRAME_WAITING_OUT => rc_frame_ready,
+ RC_LOADING_DONE_IN => rc_loading_done,
+ RC_FRAME_SIZE_OUT => rc_frame_size,
+ RC_FRAME_PROTO_OUT => rc_frame_proto,
+ RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
+ RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
+ RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
+ RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
+ RC_SRC_UDP_PORT_OUT => rc_src_udp,
+ RC_DEST_UDP_PORT_OUT => rc_dest_udp,
+
+ -- statistics
+ FRAMES_RECEIVED_OUT => rc_frames_rec_ctr,
+ BYTES_RECEIVED_OUT => rc_bytes_rec,
+ DEBUG_OUT => rc_debug
+ );
+
+ FRAME_RECEIVER : trb_net16_gbe_frame_receiver
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => global_reset,
+ LINK_OK_IN => link_ok,
+ ALLOW_RX_IN => CFG_ALLOW_RX_IN,
+ RX_MAC_CLK => CLK_RX_125_IN,
+ MY_MAC_IN => MY_MAC_IN,
+
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
+
+ -- input signals from TS_MAC
+ MAC_RX_EOF_IN => MAC_RX_EOF_IN,
+ MAC_RX_ER_IN => MAC_RX_ERROR_IN,
+ MAC_RXD_IN => MAC_RX_DATA_IN,
+ MAC_RX_EN_IN => MAC_RX_WRITE_IN,
+ MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN,
+ MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT,
+ MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN,
+ MAC_RX_STAT_VEC_IN => MAC_RX_STATS_IN,
+ -- output signal to control logic
+ FR_Q_OUT => fr_q,
+ FR_RD_EN_IN => fr_rd_en,
+ FR_FRAME_VALID_OUT => fr_frame_valid,
+ FR_GET_FRAME_IN => fr_get_frame,
+ FR_FRAME_SIZE_OUT => fr_frame_size,
+ FR_FRAME_PROTO_OUT => fr_frame_proto,
+ FR_IP_PROTOCOL_OUT => fr_ip_proto,
+ FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types,
+ FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip,
+ FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp,
+ FR_VLAN_ID_IN => (others => '0'), --vlan_id,
+
+ FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
+ FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
+ FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
+ FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
+ FR_SRC_UDP_PORT_OUT => fr_src_udp,
+ FR_DEST_UDP_PORT_OUT => fr_dest_udp,
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
+ MONITOR_DROPPED_OUT => monitor_dropped
+ );
+
+ end generate rx_enable_gen;
+
+ rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
+ rc_q <= (others => '0');
+ rc_frame_ready <= '0';
+ rc_frame_size <= (others => '0');
+ rc_frame_proto <= (others => '0');
+
+ rc_src_mac <= (others => '0');
+ rc_dest_mac <= (others => '0');
+ rc_src_ip <= (others => '0');
+ rc_dest_ip <= (others => '0');
+ rc_src_udp <= (others => '0');
+ rc_dest_udp <= (others => '0');
+
+ rc_frames_rec_ctr <= (others => '0');
+ rc_bytes_rec <= (others => '0');
+ rc_debug <= (others => '0');
+
+ monitor_rx_bytes <= (others => '0');
+ monitor_rx_frames <= (others => '0');
+ monitor_dropped <= (others => '0');
+
+ end generate rx_disable_gen;
+
+ MONITOR_RX_FRAMES_OUT <= monitor_rx_frames;
+ MONITOR_RX_BYTES_OUT <= monitor_rx_bytes;
+ MONITOR_TX_FRAMES_OUT <= monitor_tx_frames;
+ MONITOR_TX_BYTES_OUT <= monitor_tx_bytes;
+ MONITOR_TX_PACKETS_OUT <= monitor_tx_packets;
+ MONITOR_DROPPED_OUT <= monitor_dropped;
+
+ MONITOR_GEN_DBG_OUT <= dbg_select_gen;
-- MONITOR_RX_BYTES_OUT <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32);
-- MONITOR_RX_FRAMES_OUT <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32);
use work.trb_net_gbe_components.all;
entity gbe_med_interface is
- generic (
- DO_SIMULATION : integer range 0 to 1;
- NUMBER_OF_GBE_LINKS : integer range 1 to 4;
- LINKS_ACTIVE : std_logic_vector(3 downto 0)
- );
- port (
- RESET : in std_logic;
- GSR_N : in std_logic;
- CLK_SYS_IN : in std_logic;
- CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- CLK_125_IN : in std_logic;
- CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- -- MAC status and config
- MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- -- MAC data interface
- MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
- MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ generic (
+ DO_SIMULATION : integer range 0 to 1;
+ NUMBER_OF_GBE_LINKS : integer range 1 to 4;
+ LINKS_ACTIVE : std_logic_vector(3 downto 0)
+ );
+ port (
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ CLK_SYS_IN : in std_logic;
+ CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ CLK_125_IN : in std_logic;
+ CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ -- MAC status and config
+ MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ -- MAC data interface
+ MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
+ MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
- MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
+ MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
+ MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
- DEBUG_OUT : out std_logic_vector(255 downto 0)
- );
+ DEBUG_OUT : out std_logic_vector(255 downto 0)
+ );
end entity gbe_med_interface;
architecture RTL of gbe_med_interface is
-
- component sgmii_gbe_pcs35
-port( rst_n : in std_logic;
- signal_detect : in std_logic;
- gbe_mode : in std_logic;
- sgmii_mode : in std_logic;
- operational_rate : in std_logic_vector(1 downto 0);
- debug_link_timer_short : in std_logic;
+
+ component sgmii_gbe_pcs35
+ port(
+ rst_n : in std_logic;
+ signal_detect : in std_logic;
+ gbe_mode : in std_logic;
+ sgmii_mode : in std_logic;
+ operational_rate : in std_logic_vector(1 downto 0);
+ debug_link_timer_short : in std_logic;
- force_isolate : in std_logic;
- force_loopback : in std_logic;
- force_unidir : in std_logic;
+ force_isolate : in std_logic;
+ force_loopback : in std_logic;
+ force_unidir : in std_logic;
- rx_compensation_err : out std_logic;
+ rx_compensation_err : out std_logic;
- ctc_drop_flag : out std_logic;
- ctc_add_flag : out std_logic;
- an_link_ok : out std_logic;
+ ctc_drop_flag : out std_logic;
+ ctc_add_flag : out std_logic;
+ an_link_ok : out std_logic;
- tx_clk_125 : in std_logic;
- tx_clock_enable_source : out std_logic;
- tx_clock_enable_sink : in std_logic;
- tx_d : in std_logic_vector(7 downto 0);
- tx_en : in std_logic;
- tx_er : in std_logic;
- rx_clk_125 : in std_logic;
- rx_clock_enable_source : out std_logic;
- rx_clock_enable_sink : in std_logic;
- rx_d : out std_logic_vector(7 downto 0);
- rx_dv : out std_logic;
- rx_er : out std_logic;
- col : out std_logic;
- crs : out std_logic;
- tx_data : out std_logic_vector(7 downto 0);
- tx_kcntl : out std_logic;
- tx_disparity_cntl : out std_logic;
+ tx_clk_125 : in std_logic;
+ tx_clock_enable_source : out std_logic;
+ tx_clock_enable_sink : in std_logic;
+ tx_d : in std_logic_vector(7 downto 0);
+ tx_en : in std_logic;
+ tx_er : in std_logic;
+ rx_clk_125 : in std_logic;
+ rx_clock_enable_source : out std_logic;
+ rx_clock_enable_sink : in std_logic;
+ rx_d : out std_logic_vector(7 downto 0);
+ rx_dv : out std_logic;
+ rx_er : out std_logic;
+ col : out std_logic;
+ crs : out std_logic;
+ tx_data : out std_logic_vector(7 downto 0);
+ tx_kcntl : out std_logic;
+ tx_disparity_cntl : out std_logic;
- xmit_autoneg : out std_logic;
+ xmit_autoneg : out std_logic;
- serdes_recovered_clk : in std_logic;
- rx_data : in std_logic_vector(7 downto 0);
- rx_even : in std_logic;
- rx_kcntl : in std_logic;
- rx_disp_err : in std_logic;
- rx_cv_err : in std_logic;
- rx_err_decode_mode : in std_logic;
- mr_an_complete : out std_logic;
- mr_page_rx : out std_logic;
- mr_lp_adv_ability : out std_logic_vector(15 downto 0);
- mr_main_reset : in std_logic;
- mr_an_enable : in std_logic;
- mr_restart_an : in std_logic;
- mr_adv_ability : in std_logic_vector(15 downto 0)
- );
-end component;
+ serdes_recovered_clk : in std_logic;
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_even : in std_logic;
+ rx_kcntl : in std_logic;
+ rx_disp_err : in std_logic;
+ rx_cv_err : in std_logic;
+ rx_err_decode_mode : in std_logic;
+ mr_an_complete : out std_logic;
+ mr_page_rx : out std_logic;
+ mr_lp_adv_ability : out std_logic_vector(15 downto 0);
+ mr_main_reset : in std_logic;
+ mr_an_enable : in std_logic;
+ mr_restart_an : in std_logic;
+ mr_adv_ability : in std_logic_vector(15 downto 0)
+ );
+ end component;
-component reset_controller_pcs port (
- rst_n : in std_logic;
- clk : in std_logic;
- tx_plol : in std_logic;
- rx_cdr_lol : in std_logic;
- quad_rst_out : out std_logic;
- tx_pcs_rst_out : out std_logic;
- rx_pcs_rst_out : out std_logic
- );
-end component;
-component reset_controller_cdr port (
- rst_n : in std_logic;
- clk : in std_logic;
- cdr_lol : in std_logic;
- cdr_rst_out : out std_logic
- );
-end component;
+ component reset_controller_pcs
+ port (
+ rst_n : in std_logic;
+ clk : in std_logic;
+ tx_plol : in std_logic;
+ rx_cdr_lol : in std_logic;
+ quad_rst_out : out std_logic;
+ tx_pcs_rst_out : out std_logic;
+ rx_pcs_rst_out : out std_logic
+ );
+ end component;
-component rate_resolution port (
- gbe_mode : in std_logic;
- sgmii_mode : in std_logic;
- an_enable : in std_logic;
- advertised_rate : in std_logic_vector(1 downto 0);
- link_partner_rate : in std_logic_vector(1 downto 0);
- non_an_rate : in std_logic_vector(1 downto 0);
- operational_rate : out std_logic_vector(1 downto 0)
- );
-end component;
+ component reset_controller_cdr port (
+ rst_n : in std_logic;
+ clk : in std_logic;
+ cdr_lol : in std_logic;
+ cdr_rst_out : out std_logic
+ );
+ end component;
-component register_interface_hb port (
- rst_n : in std_logic;
- hclk : in std_logic;
- gbe_mode : in std_logic;
- sgmii_mode : in std_logic;
- hcs_n : in std_logic;
- hwrite_n : in std_logic;
- haddr : in std_logic_vector(3 downto 0);
- hdatain : in std_logic_vector(7 downto 0);
- hdataout : out std_logic_vector(7 downto 0);
- hready_n : out std_logic;
- mr_an_complete : in std_logic;
- mr_page_rx : in std_logic;
- mr_lp_adv_ability : in std_logic_vector(15 downto 0);
- mr_main_reset : out std_logic;
- mr_an_enable : out std_logic;
- mr_restart_an : out std_logic;
- mr_adv_ability : out std_logic_vector(15 downto 0)
- );
-end component;
+ component rate_resolution
+ port (
+ gbe_mode : in std_logic;
+ sgmii_mode : in std_logic;
+ an_enable : in std_logic;
+ advertised_rate : in std_logic_vector(1 downto 0);
+ link_partner_rate : in std_logic_vector(1 downto 0);
+ non_an_rate : in std_logic_vector(1 downto 0);
+ operational_rate : out std_logic_vector(1 downto 0)
+ );
+ end component;
-component tsmac35 --tsmac36 --tsmac35
-port(
- --------------- clock and reset port declarations ------------------
- hclk : in std_logic;
- txmac_clk : in std_logic;
- rxmac_clk : in std_logic;
- reset_n : in std_logic;
- txmac_clk_en : in std_logic;
- rxmac_clk_en : in std_logic;
- ------------------- Input signals to the GMII ----------------
- rxd : in std_logic_vector(7 downto 0);
- rx_dv : in std_logic;
- rx_er : in std_logic;
- col : in std_logic;
- crs : in std_logic;
- -------------------- Input signals to the CPU I/F -------------------
- haddr : in std_logic_vector(7 downto 0);
- hdatain : in std_logic_vector(7 downto 0);
- hcs_n : in std_logic;
- hwrite_n : in std_logic;
- hread_n : in std_logic;
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata : in std_logic_vector(7 downto 0);
- tx_fifoavail : in std_logic;
- tx_fifoeof : in std_logic;
- tx_fifoempty : in std_logic;
- tx_sndpaustim : in std_logic_vector(15 downto 0);
- tx_sndpausreq : in std_logic;
- tx_fifoctrl : in std_logic;
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full : in std_logic;
- ignore_pkt : in std_logic;
- -------------------- Output signals from the GMII -----------------------
- txd : out std_logic_vector(7 downto 0);
- tx_en : out std_logic;
- tx_er : out std_logic;
- -------------------- Output signals from the CPU I/F -------------------
- hdataout : out std_logic_vector(7 downto 0);
- hdataout_en_n : out std_logic;
- hready_n : out std_logic;
- cpu_if_gbit_en : out std_logic;
- ---------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread : out std_logic;
- tx_discfrm : out std_logic;
- tx_staten : out std_logic;
- tx_done : out std_logic;
- tx_statvec : out std_logic_vector(30 downto 0);
- ---------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error : out std_logic;
- rx_stat_vector : out std_logic_vector(31 downto 0);
- rx_dbout : out std_logic_vector(7 downto 0);
- rx_write : out std_logic;
- rx_stat_en : out std_logic;
- rx_eof : out std_logic;
- rx_error : out std_logic
-);
-end component;
-
- signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tx_pll_lol, quad_rst : std_logic;
- signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- --signal rst_n : std_logic;
- signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0);
- signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
- signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
- signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
-
- signal synced_rst, ff : std_logic;
-
- signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
+ component register_interface_hb port (
+ rst_n : in std_logic;
+ hclk : in std_logic;
+ gbe_mode : in std_logic;
+ sgmii_mode : in std_logic;
+ hcs_n : in std_logic;
+ hwrite_n : in std_logic;
+ haddr : in std_logic_vector(3 downto 0);
+ hdatain : in std_logic_vector(7 downto 0);
+ hdataout : out std_logic_vector(7 downto 0);
+ hready_n : out std_logic;
+ mr_an_complete : in std_logic;
+ mr_page_rx : in std_logic;
+ mr_lp_adv_ability : in std_logic_vector(15 downto 0);
+ mr_main_reset : out std_logic;
+ mr_an_enable : out std_logic;
+ mr_restart_an : out std_logic;
+ mr_adv_ability : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component tsmac35
+ port(
+ --------------- clock and reset port declarations ------------------
+ hclk : in std_logic;
+ txmac_clk : in std_logic;
+ rxmac_clk : in std_logic;
+ reset_n : in std_logic;
+ txmac_clk_en : in std_logic;
+ rxmac_clk_en : in std_logic;
+ ------------------- Input signals to the GMII ----------------
+ rxd : in std_logic_vector(7 downto 0);
+ rx_dv : in std_logic;
+ rx_er : in std_logic;
+ col : in std_logic;
+ crs : in std_logic;
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr : in std_logic_vector(7 downto 0);
+ hdatain : in std_logic_vector(7 downto 0);
+ hcs_n : in std_logic;
+ hwrite_n : in std_logic;
+ hread_n : in std_logic;
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata : in std_logic_vector(7 downto 0);
+ tx_fifoavail : in std_logic;
+ tx_fifoeof : in std_logic;
+ tx_fifoempty : in std_logic;
+ tx_sndpaustim : in std_logic_vector(15 downto 0);
+ tx_sndpausreq : in std_logic;
+ tx_fifoctrl : in std_logic;
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full : in std_logic;
+ ignore_pkt : in std_logic;
+ -------------------- Output signals from the GMII -----------------------
+ txd : out std_logic_vector(7 downto 0);
+ tx_en : out std_logic;
+ tx_er : out std_logic;
+ -------------------- Output signals from the CPU I/F -------------------
+ hdataout : out std_logic_vector(7 downto 0);
+ hdataout_en_n : out std_logic;
+ hready_n : out std_logic;
+ cpu_if_gbit_en : out std_logic;
+ ---------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread : out std_logic;
+ tx_discfrm : out std_logic;
+ tx_staten : out std_logic;
+ tx_done : out std_logic;
+ tx_statvec : out std_logic_vector(30 downto 0);
+ ---------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error : out std_logic;
+ rx_stat_vector : out std_logic_vector(31 downto 0);
+ rx_dbout : out std_logic_vector(7 downto 0);
+ rx_write : out std_logic;
+ rx_stat_en : out std_logic;
+ rx_eof : out std_logic;
+ rx_error : out std_logic
+ );
+ end component;
+
+ signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_cdr_lol : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tx_pll_lol, quad_rst : std_logic;
+ signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0);
+ signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
+ signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
+ signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pcs_txd : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal pcs_tx_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal pcs_tx_er : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+
+ signal synced_rst, ff : std_logic;
+
+ signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
begin
-
- rx_power <= "1111";
- tx_power <= "1111";
-
- --rst_n <= not RESET;
-
- reset_sync : process(GSR_N, CLK_SYS_IN)
- begin
- if (GSR_N = '0') then
- ff <= '0';
- synced_rst <= '0';
- elsif rising_edge(CLK_SYS_IN) then
- ff <= '1';
- synced_rst <= ff;
- end if;
- end process reset_sync;
-
- SD_TXDIS_OUT <= "0000";
-
- CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN;
- CLK_125_RX_OUT <= sd_rx_clk;
-
- impl_gen : if DO_SIMULATION = 0 generate
-
- gbe_serdes : entity work.serdes_gbe_4ch
- port map(
- ------------------
- -- CH0 --
- hdinp_ch0 => SD_RXD_P_IN(0),
- hdinn_ch0 => SD_RXD_N_IN(0),
- hdoutp_ch0 => SD_TXD_P_OUT(0),
- hdoutn_ch0 => SD_TXD_N_OUT(0),
- rxiclk_ch0 => sd_rx_clk(0),
- txiclk_ch0 => CLK_125_IN,
- rx_full_clk_ch0 => sd_rx_clk(0),
- rx_half_clk_ch0 => open,
- tx_full_clk_ch0 => open,
- tx_half_clk_ch0 => open,
- fpga_rxrefclk_ch0 => CLK_125_IN,
- txdata_ch0 => sd_tx_data_q(7 downto 0),
- tx_k_ch0 => sd_tx_kcntl_q(0),
- xmit_ch0 => xmit(0),
- tx_disp_correct_ch0 => sd_tx_correct_disp_q(0),
- rxdata_ch0 => sd_rx_data(7 downto 0),
- rx_k_ch0 => sd_rx_kcntl(0),
- rx_disp_err_ch0 => sd_rx_disp_error(0),
- rx_cv_err_ch0 => sd_rx_cv_error(0),
- rx_serdes_rst_ch0_c => rx_serdes_rst(0),
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pwrup_ch0_c => tx_power(0),
- rx_pwrup_ch0_c => rx_power(0),
- rx_los_low_ch0_s => los(0),
- lsm_status_ch0_s => signal_detected(0),
- rx_cdr_lol_ch0_s => rx_cdr_lol(0),
- tx_pcs_rst_ch0_c => tx_pcs_rst(0),
- rx_pcs_rst_ch0_c => rx_pcs_rst(0),
- -- CH1 --
- hdinp_ch1 => SD_RXD_P_IN(1),
- hdinn_ch1 => SD_RXD_N_IN(1),
- hdoutp_ch1 => SD_TXD_P_OUT(1),
- hdoutn_ch1 => SD_TXD_N_OUT(1),
- rxiclk_ch1 => sd_rx_clk(1),
- txiclk_ch1 => CLK_125_IN,
- rx_full_clk_ch1 => sd_rx_clk(1),
- rx_half_clk_ch1 => open,
- tx_full_clk_ch1 => open,
- tx_half_clk_ch1 => open,
- fpga_rxrefclk_ch1 => CLK_125_IN,
- txdata_ch1 => sd_tx_data_q(15 downto 8),
- tx_k_ch1 => sd_tx_kcntl_q(1),
- xmit_ch1 => xmit(1),
- tx_disp_correct_ch1 => sd_tx_correct_disp_q(1),
- rxdata_ch1 => sd_rx_data(15 downto 8),
- rx_k_ch1 => sd_rx_kcntl(1),
- rx_disp_err_ch1 => sd_rx_disp_error(1),
- rx_cv_err_ch1 => sd_rx_cv_error(1),
- rx_serdes_rst_ch1_c => rx_serdes_rst(1),
- sb_felb_ch1_c => '0',
- sb_felb_rst_ch1_c => '0',
- tx_pwrup_ch1_c => tx_power(1),
- rx_pwrup_ch1_c => rx_power(1),
- rx_los_low_ch1_s => los(1),
- lsm_status_ch1_s => signal_detected(1),
- rx_cdr_lol_ch1_s => rx_cdr_lol(1),
- tx_pcs_rst_ch1_c => tx_pcs_rst(1),
- rx_pcs_rst_ch1_c => rx_pcs_rst(1),
- -- CH2 --
- hdinp_ch2 => SD_RXD_P_IN(2),
- hdinn_ch2 => SD_RXD_N_IN(2),
- hdoutp_ch2 => SD_TXD_P_OUT(2),
- hdoutn_ch2 => SD_TXD_N_OUT(2),
- rxiclk_ch2 => sd_rx_clk(2),
- txiclk_ch2 => CLK_125_IN,
- rx_full_clk_ch2 => sd_rx_clk(2),
- rx_half_clk_ch2 => open,
- tx_full_clk_ch2 => open,
- tx_half_clk_ch2 => open,
- fpga_rxrefclk_ch2 => CLK_125_IN,
- txdata_ch2 => sd_tx_data_q(23 downto 16),
- tx_k_ch2 => sd_tx_kcntl_q(2),
- xmit_ch2 => xmit(2),
- tx_disp_correct_ch2 => sd_tx_correct_disp_q(2),
- rxdata_ch2 => sd_rx_data(23 downto 16),
- rx_k_ch2 => sd_rx_kcntl(2),
- rx_disp_err_ch2 => sd_rx_disp_error(2),
- rx_cv_err_ch2 => sd_rx_cv_error(2),
- rx_serdes_rst_ch2_c => rx_serdes_rst(2),
- sb_felb_ch2_c => '0',
- sb_felb_rst_ch2_c => '0',
- tx_pwrup_ch2_c => tx_power(2),
- rx_pwrup_ch2_c => rx_power(2),
- rx_los_low_ch2_s => los(2),
- lsm_status_ch2_s => signal_detected(2),
- rx_cdr_lol_ch2_s => rx_cdr_lol(2),
- tx_pcs_rst_ch2_c => tx_pcs_rst(2),
- rx_pcs_rst_ch2_c => rx_pcs_rst(2),
- -- CH3 --
- hdinp_ch3 => SD_RXD_P_IN(3),
- hdinn_ch3 => SD_RXD_N_IN(3),
- hdoutp_ch3 => SD_TXD_P_OUT(3),
- hdoutn_ch3 => SD_TXD_N_OUT(3),
- rxiclk_ch3 => sd_rx_clk(3),
- txiclk_ch3 => CLK_125_IN,
- rx_full_clk_ch3 => sd_rx_clk(3),
- rx_half_clk_ch3 => open,
- tx_full_clk_ch3 => open,
- tx_half_clk_ch3 => open,
- fpga_rxrefclk_ch3 => CLK_125_IN,
- txdata_ch3 => sd_tx_data_q(31 downto 24),
- tx_k_ch3 => sd_tx_kcntl_q(3),
- xmit_ch3 => xmit(3),
- tx_disp_correct_ch3 => sd_tx_correct_disp_q(3),
- rxdata_ch3 => sd_rx_data(31 downto 24),
- rx_k_ch3 => sd_rx_kcntl(3),
- rx_disp_err_ch3 => sd_rx_disp_error(3),
- rx_cv_err_ch3 => sd_rx_cv_error(3),
- rx_serdes_rst_ch3_c => rx_serdes_rst(3),
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pwrup_ch3_c => tx_power(3),
- rx_pwrup_ch3_c => rx_power(3),
- rx_los_low_ch3_s => los(3),
- lsm_status_ch3_s => signal_detected(3),
- rx_cdr_lol_ch3_s => rx_cdr_lol(3),
- tx_pcs_rst_ch3_c => tx_pcs_rst(3),
- rx_pcs_rst_ch3_c => rx_pcs_rst(3),
- ---- Miscillaneous ports
- fpga_txrefclk => CLK_125_IN,
- tx_serdes_rst_c => '0',
- tx_pll_lol_qd_s => tx_pll_lol,
- tx_sync_qd_c => '0',
- rst_qd_c => quad_rst,
- serdes_rst_qd_c => '0'
- );
-
- SYNC_TX_PROC : process(CLK_125_IN)
- begin
- if rising_edge(CLK_125_IN) then
- sd_tx_data_q <= sd_tx_data;
- sd_tx_kcntl_q <= sd_tx_kcntl;
- sd_tx_correct_disp_q <= sd_tx_correct_disp;
- end if;
- end process SYNC_TX_PROC;
-
-
- pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
-
- pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate
-
- SYNC_RX_PROC : process(sd_rx_clk)
- begin
- if rising_edge(sd_rx_clk(i)) then
- sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8);
- sd_rx_kcntl_q(i) <= sd_rx_kcntl(i);
- sd_rx_disp_error_q(i) <= sd_rx_disp_error(i);
- sd_rx_cv_error_q(i) <= sd_rx_cv_error(i);
- end if;
- end process SYNC_RX_PROC;
-
- SGMII_GBE_PCS : sgmii_gbe_pcs35
- port map(
- rst_n => synced_rst, --rst_n,
- signal_detect => signal_detected(i),
- gbe_mode => '1',
- sgmii_mode => '0',
- operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
- debug_link_timer_short => '0',
-
- force_isolate => '0',
- force_loopback => '0',
- force_unidir => '0',
-
- rx_compensation_err => open,
-
- ctc_drop_flag => open,
- ctc_add_flag => open,
- an_link_ok => open,
-
- -- MAC interface
- tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes
- tx_clock_enable_source => tx_clk_en(i),
- tx_clock_enable_sink => tx_clk_en(i),
- tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
- tx_en => pcs_tx_en(i), -- TX data enable from MAC
- tx_er => pcs_tx_er(i), -- TX error from MAC
- rx_clk_125 => sd_rx_clk(i),
- rx_clock_enable_source => rx_clk_en(i),
- rx_clock_enable_sink => rx_clk_en(i),
- rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC
- rx_dv => pcs_rx_en(i), -- RX data enable to MAC
- rx_er => pcs_rx_er(i), -- RX error to MAC
- col => pcs_col(i),
- crs => pcs_crs(i),
-
- -- SerDes interface
- tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
- tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes
- tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
-
- xmit_autoneg => xmit(i),
-
- serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
- rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
- rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
- rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes
- rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes
- -- Autonegotiation stuff
- mr_an_complete => an_complete(i),
- mr_page_rx => mr_page_rx(i),
- mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16),
- mr_main_reset => mr_main_reset(i),
- mr_an_enable => '1',
- mr_restart_an => mr_restart_an(i),
- mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
- );
-
- MAC_AN_READY_OUT(i) <= an_complete(i);
-
- u0_reset_controller_pcs : reset_controller_pcs port map(
- rst_n => synced_rst, --rst_n,
- clk => CLK_125_IN,
- tx_plol => tx_pll_lol,
- rx_cdr_lol => rx_cdr_lol(i),
- quad_rst_out => open, --quad_rst,
- tx_pcs_rst_out => tx_pcs_rst(i),
- rx_pcs_rst_out => rx_pcs_rst(i)
- );
-
- u0_reset_controller_cdr : reset_controller_cdr port map(
- rst_n => synced_rst, --rst_n,
- clk => CLK_125_IN,
- cdr_lol => rx_cdr_lol(i),
- cdr_rst_out => rx_serdes_rst(i)
- );
-
- u0_rate_resolution : rate_resolution port map(
- gbe_mode => '1',
- sgmii_mode => '0',
- an_enable => '1',
- advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10),
- link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10),
- non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled
-
- operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2)
- );
-
- u0_ri : register_interface_hb port map(
- -- Control Signals
- rst_n => synced_rst, --rst_n,
- hclk => CLK_125_IN,
- gbe_mode => '1',
- sgmii_mode => '0',
-
- -- Host Bus
- hcs_n => '1',
- hwrite_n => '1',
- haddr => (others => '0'),
- hdatain => (others => '0'),
-
- hdataout => open,
- hready_n => open,
-
- -- Register Outputs
- mr_an_enable => mr_an_enable(i),
- mr_restart_an => mr_restart_an(i),
- mr_main_reset => mr_main_reset(i),
- mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16),
-
- -- Register Inputs
- mr_an_complete => an_complete(i),
- mr_page_rx => mr_page_rx(i),
- mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
- );
-
- MAC: tsmac35
- port map(
- ----------------- clock and reset port declarations ------------------
- hclk => CLK_SYS_IN,
- txmac_clk => CLK_125_IN,
- rxmac_clk => sd_rx_clk(i),
- reset_n => GSR_N,
- txmac_clk_en => '1',
- rxmac_clk_en => '1',
- ------------------- Input signals to the GMII ----------------
- rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8),
- rx_dv => pcs_rx_en_qq(i),
- rx_er => pcs_rx_er_qq(i),
- col => pcs_col(i),
- crs => pcs_crs(i),
- -------------------- Input signals to the CPU I/F -------------------
- haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
- hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
- hcs_n => tsm_hcs_n(i),
- hwrite_n => tsm_hwrite_n(i),
- hread_n => tsm_hread_n(i),
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
- tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8),
- tx_fifoavail => MAC_FIFOAVAIL_IN(i),
- tx_fifoeof => MAC_FIFOEOF_IN(i),
- tx_fifoempty => MAC_FIFOEMPTY_IN(i),
- tx_sndpaustim => x"0000",
- tx_sndpausreq => '0',
- tx_fifoctrl => '0', -- always data frame
- ---------------- Input signals to the Rx MAC FIFO I/F ---------------
- rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0',
- ignore_pkt => '0',
- ---------------- Output signals from the GMII -----------------------
- txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8),
- tx_en => pcs_tx_en(i),
- tx_er => pcs_tx_er(i),
- ----------------- Output signals from the CPU I/F -------------------
- hdataout => open,
- hdataout_en_n => tsm_hdataout_en_n(i),
- hready_n => tsm_hready_n(i),
- cpu_if_gbit_en => open,
- ------------- Output signals from the Tx MAC FIFO I/F ---------------
- tx_macread => MAC_TX_READ_OUT(i),
- tx_discfrm => MAC_TX_DISCRFRM_OUT(i),
- tx_staten => MAC_TX_STAT_EN_OUT(i),
- tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31),
- tx_done => MAC_TX_DONE_OUT(i),
- ------------- Output signals from the Rx MAC FIFO I/F ---------------
- rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i),
- rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32),
- rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8),
- rx_write => MAC_RX_WRITE_OUT(i),
- rx_stat_en => MAC_RX_STAT_EN_OUT(i),
- rx_eof => MAC_RX_EOF_OUT(i),
- rx_error => MAC_RX_ERROR_OUT(i)
- );
-
- TSMAC_CONTROLLER : trb_net16_gbe_mac_control
- port map(
- CLK => CLK_SYS_IN,
- RESET => RESET,
-
- -- signals to/from main controller
- MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i),
- MC_RECONF_IN => MAC_RECONF_IN(i),
- MC_GBE_EN_IN => '1',
- MC_RX_DISCARD_FCS => '0',
- MC_PROMISC_IN => '1',
- MC_MAC_ADDR_IN => (others => '0'),
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
- TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
- TSM_HCS_N_OUT => tsm_hcs_n(i),
- TSM_HWRITE_N_OUT => tsm_hwrite_n(i),
- TSM_HREAD_N_OUT => tsm_hread_n(i),
- TSM_HREADY_N_IN => tsm_hready_n(i),
- TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
-
- DEBUG_OUT => open
- );
-
- SYNC_GMII_RX_PROC : process(sd_rx_clk)
- begin
- if rising_edge(sd_rx_clk(i)) then
- pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8);
- pcs_rx_en_q(i) <= pcs_rx_en(i);
- pcs_rx_er_q(i) <= pcs_rx_er(i);
-
- pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8);
- pcs_rx_en_qq(i) <= pcs_rx_en_q(i);
- pcs_rx_er_qq(i) <= pcs_rx_er_q(i);
- end if;
- end process SYNC_GMII_RX_PROC;
-
- SYNC_GMII_TX_PROC : process(CLK_125_IN)
- begin
- if rising_edge(CLK_125_IN) then
- pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8);
- pcs_tx_en_q <= pcs_tx_en;
- pcs_tx_er_q <= pcs_tx_er;
-
- pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8);
- pcs_tx_en_qq <= pcs_tx_en_q;
- pcs_tx_er_qq <= pcs_tx_er_q;
- end if;
- end process SYNC_GMII_TX_PROC;
-
- end generate pcs_active_gen;
-
- end generate pcs_gen;
-
- end generate impl_gen;
+
+ rx_power <= "1111";
+ tx_power <= "1111";
+
+ --rst_n <= not RESET;
+
+ reset_sync : process(GSR_N, CLK_SYS_IN)
+ begin
+ if (GSR_N = '0') then
+ ff <= '0';
+ synced_rst <= '0';
+ elsif rising_edge(CLK_SYS_IN) then
+ ff <= '1';
+ synced_rst <= ff;
+ end if;
+ end process reset_sync;
+
+ SD_TXDIS_OUT <= "0000";
+
+ CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN;
+ CLK_125_RX_OUT <= sd_rx_clk;
+
+ impl_gen : if DO_SIMULATION = 0 generate
+
+ gbe_serdes : entity work.serdes_gbe_4ch
+ port map(
+ ------------------
+ -- CH0 --
+ hdinp_ch0 => SD_RXD_P_IN(0),
+ hdinn_ch0 => SD_RXD_N_IN(0),
+ hdoutp_ch0 => SD_TXD_P_OUT(0),
+ hdoutn_ch0 => SD_TXD_N_OUT(0),
+ rxiclk_ch0 => sd_rx_clk(0),
+ txiclk_ch0 => CLK_125_IN,
+ rx_full_clk_ch0 => sd_rx_clk(0),
+ rx_half_clk_ch0 => open,
+ tx_full_clk_ch0 => open,
+ tx_half_clk_ch0 => open,
+ fpga_rxrefclk_ch0 => CLK_125_IN,
+ txdata_ch0 => sd_tx_data_q(7 downto 0),
+ tx_k_ch0 => sd_tx_kcntl_q(0),
+ xmit_ch0 => xmit(0),
+ tx_disp_correct_ch0 => sd_tx_correct_disp_q(0),
+ rxdata_ch0 => sd_rx_data(7 downto 0),
+ rx_k_ch0 => sd_rx_kcntl(0),
+ rx_disp_err_ch0 => sd_rx_disp_error(0),
+ rx_cv_err_ch0 => sd_rx_cv_error(0),
+ rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pwrup_ch0_c => tx_power(0),
+ rx_pwrup_ch0_c => rx_power(0),
+ rx_los_low_ch0_s => los(0),
+ lsm_status_ch0_s => signal_detected(0),
+ rx_cdr_lol_ch0_s => rx_cdr_lol(0),
+ tx_pcs_rst_ch0_c => tx_pcs_rst(0),
+ rx_pcs_rst_ch0_c => rx_pcs_rst(0),
+ -- CH1 --
+ hdinp_ch1 => SD_RXD_P_IN(1),
+ hdinn_ch1 => SD_RXD_N_IN(1),
+ hdoutp_ch1 => SD_TXD_P_OUT(1),
+ hdoutn_ch1 => SD_TXD_N_OUT(1),
+ rxiclk_ch1 => sd_rx_clk(1),
+ txiclk_ch1 => CLK_125_IN,
+ rx_full_clk_ch1 => sd_rx_clk(1),
+ rx_half_clk_ch1 => open,
+ tx_full_clk_ch1 => open,
+ tx_half_clk_ch1 => open,
+ fpga_rxrefclk_ch1 => CLK_125_IN,
+ txdata_ch1 => sd_tx_data_q(15 downto 8),
+ tx_k_ch1 => sd_tx_kcntl_q(1),
+ xmit_ch1 => xmit(1),
+ tx_disp_correct_ch1 => sd_tx_correct_disp_q(1),
+ rxdata_ch1 => sd_rx_data(15 downto 8),
+ rx_k_ch1 => sd_rx_kcntl(1),
+ rx_disp_err_ch1 => sd_rx_disp_error(1),
+ rx_cv_err_ch1 => sd_rx_cv_error(1),
+ rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+ sb_felb_ch1_c => '0',
+ sb_felb_rst_ch1_c => '0',
+ tx_pwrup_ch1_c => tx_power(1),
+ rx_pwrup_ch1_c => rx_power(1),
+ rx_los_low_ch1_s => los(1),
+ lsm_status_ch1_s => signal_detected(1),
+ rx_cdr_lol_ch1_s => rx_cdr_lol(1),
+ tx_pcs_rst_ch1_c => tx_pcs_rst(1),
+ rx_pcs_rst_ch1_c => rx_pcs_rst(1),
+ -- CH2 --
+ hdinp_ch2 => SD_RXD_P_IN(2),
+ hdinn_ch2 => SD_RXD_N_IN(2),
+ hdoutp_ch2 => SD_TXD_P_OUT(2),
+ hdoutn_ch2 => SD_TXD_N_OUT(2),
+ rxiclk_ch2 => sd_rx_clk(2),
+ txiclk_ch2 => CLK_125_IN,
+ rx_full_clk_ch2 => sd_rx_clk(2),
+ rx_half_clk_ch2 => open,
+ tx_full_clk_ch2 => open,
+ tx_half_clk_ch2 => open,
+ fpga_rxrefclk_ch2 => CLK_125_IN,
+ txdata_ch2 => sd_tx_data_q(23 downto 16),
+ tx_k_ch2 => sd_tx_kcntl_q(2),
+ xmit_ch2 => xmit(2),
+ tx_disp_correct_ch2 => sd_tx_correct_disp_q(2),
+ rxdata_ch2 => sd_rx_data(23 downto 16),
+ rx_k_ch2 => sd_rx_kcntl(2),
+ rx_disp_err_ch2 => sd_rx_disp_error(2),
+ rx_cv_err_ch2 => sd_rx_cv_error(2),
+ rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+ sb_felb_ch2_c => '0',
+ sb_felb_rst_ch2_c => '0',
+ tx_pwrup_ch2_c => tx_power(2),
+ rx_pwrup_ch2_c => rx_power(2),
+ rx_los_low_ch2_s => los(2),
+ lsm_status_ch2_s => signal_detected(2),
+ rx_cdr_lol_ch2_s => rx_cdr_lol(2),
+ tx_pcs_rst_ch2_c => tx_pcs_rst(2),
+ rx_pcs_rst_ch2_c => rx_pcs_rst(2),
+ -- CH3 --
+ hdinp_ch3 => SD_RXD_P_IN(3),
+ hdinn_ch3 => SD_RXD_N_IN(3),
+ hdoutp_ch3 => SD_TXD_P_OUT(3),
+ hdoutn_ch3 => SD_TXD_N_OUT(3),
+ rxiclk_ch3 => sd_rx_clk(3),
+ txiclk_ch3 => CLK_125_IN,
+ rx_full_clk_ch3 => sd_rx_clk(3),
+ rx_half_clk_ch3 => open,
+ tx_full_clk_ch3 => open,
+ tx_half_clk_ch3 => open,
+ fpga_rxrefclk_ch3 => CLK_125_IN,
+ txdata_ch3 => sd_tx_data_q(31 downto 24),
+ tx_k_ch3 => sd_tx_kcntl_q(3),
+ xmit_ch3 => xmit(3),
+ tx_disp_correct_ch3 => sd_tx_correct_disp_q(3),
+ rxdata_ch3 => sd_rx_data(31 downto 24),
+ rx_k_ch3 => sd_rx_kcntl(3),
+ rx_disp_err_ch3 => sd_rx_disp_error(3),
+ rx_cv_err_ch3 => sd_rx_cv_error(3),
+ rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pwrup_ch3_c => tx_power(3),
+ rx_pwrup_ch3_c => rx_power(3),
+ rx_los_low_ch3_s => los(3),
+ lsm_status_ch3_s => signal_detected(3),
+ rx_cdr_lol_ch3_s => rx_cdr_lol(3),
+ tx_pcs_rst_ch3_c => tx_pcs_rst(3),
+ rx_pcs_rst_ch3_c => rx_pcs_rst(3),
+ ---- Miscillaneous portspcs_rxd
+ fpga_txrefclk => CLK_125_IN,
+ tx_serdes_rst_c => '0',
+ tx_pll_lol_qd_s => tx_pll_lol,
+ tx_sync_qd_c => '0',
+ rst_qd_c => quad_rst,
+ serdes_rst_qd_c => '0'
+ );
+
+ -- should be in generate loop?
+ SYNC_TX_PROC : process(CLK_125_IN)
+ begin
+ if rising_edge(CLK_125_IN) then
+ sd_tx_data_q <= sd_tx_data;
+ sd_tx_kcntl_q <= sd_tx_kcntl;
+ sd_tx_correct_disp_q <= sd_tx_correct_disp;
+ end if;
+ end process SYNC_TX_PROC;
+
+ pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
+
+ pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate
+
+ SYNC_RX_PROC : process(sd_rx_clk)
+ begin
+ if rising_edge(sd_rx_clk(i)) then
+ sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8);
+ sd_rx_kcntl_q(i) <= sd_rx_kcntl(i);
+ sd_rx_disp_error_q(i) <= sd_rx_disp_error(i);
+ sd_rx_cv_error_q(i) <= sd_rx_cv_error(i);
+ end if;
+ end process SYNC_RX_PROC;
+
+ SGMII_GBE_PCS : sgmii_gbe_pcs35
+ port map(
+ rst_n => synced_rst, --rst_n,
+ signal_detect => signal_detected(i),
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)),
+ debug_link_timer_short => '0',
+ force_isolate => '0',
+ force_loopback => '0',
+ force_unidir => '0',
+ rx_compensation_err => open,
+ ctc_drop_flag => open,
+ ctc_add_flag => open,
+ an_link_ok => open,
+ -- MAC interface
+ tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes
+ tx_clock_enable_source => tx_clk_en(i),
+ tx_clock_enable_sink => tx_clk_en(i),
+ tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC
+ tx_en => pcs_tx_en(i), -- TX data enable from MAC
+ tx_er => pcs_tx_er(i), -- TX error from MAC
+ rx_clk_125 => sd_rx_clk(i),
+ rx_clock_enable_source => rx_clk_en(i),
+ rx_clock_enable_sink => rx_clk_en(i),
+ rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC
+ rx_dv => pcs_rx_en(i), -- RX data enable to MAC
+ rx_er => pcs_rx_er(i), -- RX error to MAC
+ col => pcs_col(i),
+ crs => pcs_crs(i),
+ -- SerDes interface
+ tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes
+ tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes
+ tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes)
+ xmit_autoneg => xmit(i),
+ serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream
+ rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes
+ rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)
+ rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes
+ rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes
+ -- Autonegotiation stuff
+ mr_an_complete => an_complete(i),
+ mr_page_rx => mr_page_rx(i),
+ mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16),
+ mr_main_reset => mr_main_reset(i),
+ mr_an_enable => '1',
+ mr_restart_an => mr_restart_an(i),
+ mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16)
+ );
+
+ MAC_AN_READY_OUT(i) <= an_complete(i);
+
+ u0_reset_controller_pcs : reset_controller_pcs port map(
+ rst_n => synced_rst, --rst_n,
+ clk => CLK_125_IN,
+ tx_plol => tx_pll_lol,
+ rx_cdr_lol => rx_cdr_lol(i),
+ quad_rst_out => open, --quad_rst,
+ tx_pcs_rst_out => tx_pcs_rst(i),
+ rx_pcs_rst_out => rx_pcs_rst(i)
+ );
+
+ u0_reset_controller_cdr : reset_controller_cdr port map(
+ rst_n => synced_rst, --rst_n,
+ clk => CLK_125_IN,
+ cdr_lol => rx_cdr_lol(i),
+ cdr_rst_out => rx_serdes_rst(i)
+ );
+
+ u0_rate_resolution : rate_resolution port map(
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ an_enable => '1',
+ advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10),
+ link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10),
+ non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled
+ operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2)
+ );
+
+ u0_ri : register_interface_hb port map(
+ -- Control Signals
+ rst_n => synced_rst, --rst_n,
+ hclk => CLK_125_IN,
+ gbe_mode => '1',
+ sgmii_mode => '0',
+ -- Host Bus
+ hcs_n => '1',
+ hwrite_n => '1',
+ haddr => (others => '0'),
+ hdatain => (others => '0'),
+ hdataout => open,
+ hready_n => open,
+ -- Register Outputs
+ mr_an_enable => mr_an_enable(i),
+ mr_restart_an => mr_restart_an(i),
+ mr_main_reset => mr_main_reset(i),
+ mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16),
+
+ -- Register Inputs
+ mr_an_complete => an_complete(i),
+ mr_page_rx => mr_page_rx(i),
+ mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16)
+ );
+
+ MAC: tsmac35
+ port map(
+ ----------------- clock and reset port declarations ------------------
+ hclk => CLK_SYS_IN,
+ txmac_clk => CLK_125_IN,
+ rxmac_clk => sd_rx_clk(i),
+ reset_n => GSR_N,
+ txmac_clk_en => '1',
+ rxmac_clk_en => '1',
+ ------------------- Input signals to the GMII ----------------
+-- rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8),
+-- rx_dv => pcs_rx_en_qq(i),
+-- rx_er => pcs_rx_er_qq(i),
+ rxd => pcs_rxd( (i + 1) * 8 - 1 downto i * 8),
+ rx_dv => pcs_rx_en(i),
+ rx_er => pcs_rx_er(i),
+ col => pcs_col(i),
+ crs => pcs_crs(i),
+ -------------------- Input signals to the CPU I/F -------------------
+ haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
+ hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
+ hcs_n => tsm_hcs_n(i),
+ hwrite_n => tsm_hwrite_n(i),
+ hread_n => tsm_hread_n(i),
+ ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8),
+ tx_fifoavail => MAC_FIFOAVAIL_IN(i),
+ tx_fifoeof => MAC_FIFOEOF_IN(i),
+ tx_fifoempty => MAC_FIFOEMPTY_IN(i),
+ tx_sndpaustim => x"0000",
+ tx_sndpausreq => '0',
+ tx_fifoctrl => '0', -- always data frame
+ ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+ rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0',
+ ignore_pkt => '0',
+ ---------------- Output signals from the GMII -----------------------
+ txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8),
+ tx_en => pcs_tx_en(i),
+ tx_er => pcs_tx_er(i),
+ ----------------- Output signals from the CPU I/F -------------------
+ hdataout => open,
+ hdataout_en_n => tsm_hdataout_en_n(i),
+ hready_n => tsm_hready_n(i),
+ cpu_if_gbit_en => open,
+ ------------- Output signals from the Tx MAC FIFO I/F ---------------
+ tx_macread => MAC_TX_READ_OUT(i),
+ tx_discfrm => MAC_TX_DISCRFRM_OUT(i),
+ tx_staten => MAC_TX_STAT_EN_OUT(i),
+ tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31),
+ tx_done => MAC_TX_DONE_OUT(i),
+ ------------- Output signals from the Rx MAC FIFO I/F ---------------
+ rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i),
+ rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32),
+ rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8),
+ rx_write => MAC_RX_WRITE_OUT(i),
+ rx_stat_en => MAC_RX_STAT_EN_OUT(i),
+ rx_eof => MAC_RX_EOF_OUT(i),
+ rx_error => MAC_RX_ERROR_OUT(i)
+ );
+
+ TSMAC_CONTROLLER : trb_net16_gbe_mac_control
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
+ -- signals to/from main controller
+ MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i),
+ MC_RECONF_IN => MAC_RECONF_IN(i),
+ MC_GBE_EN_IN => '1',
+ MC_RX_DISCARD_FCS => '0',
+ MC_PROMISC_IN => '1',
+ MC_MAC_ADDR_IN => (others => '0'),
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8),
+ TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8),
+ TSM_HCS_N_OUT => tsm_hcs_n(i),
+ TSM_HWRITE_N_OUT => tsm_hwrite_n(i),
+ TSM_HREAD_N_OUT => tsm_hread_n(i),
+ TSM_HREADY_N_IN => tsm_hready_n(i),
+ TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i),
+ -- Debug
+ DEBUG_OUT => open
+ );
+
+ SYNC_GMII_RX_PROC : process(sd_rx_clk)
+ begin
+ if rising_edge(sd_rx_clk(i)) then
+ pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8);
+ pcs_rx_en_q(i) <= pcs_rx_en(i);
+ pcs_rx_er_q(i) <= pcs_rx_er(i);
+
+ pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8);
+ pcs_rx_en_qq(i) <= pcs_rx_en_q(i);
+ pcs_rx_er_qq(i) <= pcs_rx_er_q(i);
+ end if;
+ end process SYNC_GMII_RX_PROC;
+
+ end generate pcs_active_gen;
+
+ end generate pcs_gen;
+
+ end generate impl_gen;
- sim_gen : if DO_SIMULATION = 1 generate
-
- process
- begin
-
- MAC_AN_READY_OUT <= (others => '0');
- wait for 2 us;
- MAC_AN_READY_OUT <= (others => '1');
-
- wait;
- end process;
-
- process(CLK_125_IN)
- begin
- if rising_edge(CLK_125_IN) then
- MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN;
-
- fifo_eof_q <= MAC_FIFOEOF_IN;
- fifo_eof_qq <= fifo_eof_q;
- fifo_eof_qqq <= fifo_eof_qq;
- fifo_eof_qqqq <= fifo_eof_qqq;
-
- MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN;
- end if;
- end process;
-
-
- end generate sim_gen;
-
+ sim_gen : if DO_SIMULATION = 1 generate
+
+ process
+ begin
+
+ MAC_AN_READY_OUT <= (others => '0');
+ wait for 2 us;
+ MAC_AN_READY_OUT <= (others => '1');
+
+ wait;
+ end process;
+
+ process(CLK_125_IN)
+ begin
+ if rising_edge(CLK_125_IN) then
+ MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN;
+
+ fifo_eof_q <= MAC_FIFOEOF_IN;
+ fifo_eof_qq <= fifo_eof_q;
+ fifo_eof_qqq <= fifo_eof_qq;
+ fifo_eof_qqqq <= fifo_eof_qqq;
+
+ MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN;
+ end if;
+ end process;
+
+
+ end generate sim_gen;
+
end architecture RTL;
entity gbe_wrapper is
- generic(
- DO_SIMULATION : integer range 0 to 1 := 0;
- INCLUDE_DEBUG : integer range 0 to 1 := 0;
- USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
- USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- FIXED_SIZE_MODE : integer range 0 to 1 := 1;
- INCREMENTAL_MODE : integer range 0 to 1 := 0;
- FIXED_SIZE : integer range 0 to 65535 := 10;
- FIXED_DELAY_MODE : integer range 0 to 1 := 1;
- UP_DOWN_MODE : integer range 0 to 1 := 0;
- UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
- FIXED_DELAY : integer range 0 to 16777215 := 16777215;
- NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4;
- LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111";
- LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111"
- );
- port(
- CLK_SYS_IN : in std_logic;
- CLK_125_IN : in std_logic;
- RESET : in std_logic;
- GSR_N : in std_logic;
- SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
-
- TRIGGER_IN : in std_logic; -- for debug purpose only
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
- CTS_CODE_IN : in std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- SlowControl
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
- ISSUE_REBOOT_OUT : out std_logic;
- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- -- IP configuration
- BUS_IP_RX : in CTRLBUS_RX;
- BUS_IP_TX : out CTRLBUS_TX;
- -- Registers config
- BUS_REG_RX : in CTRLBUS_RX;
- BUS_REG_TX : out CTRLBUS_TX;
+ generic(
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ INCLUDE_DEBUG : integer range 0 to 1 := 0;
+ USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
+ USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
+ RX_PATH_ENABLE : integer range 0 to 1 := 1;
+ FIXED_SIZE_MODE : integer range 0 to 1 := 1;
+ INCREMENTAL_MODE : integer range 0 to 1 := 0;
+ FIXED_SIZE : integer range 0 to 65535 := 10;
+ FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+ UP_DOWN_MODE : integer range 0 to 1 := 0;
+ UP_DOWN_LIMIT : integer range 0 to 16777215 := 0;
+ FIXED_DELAY : integer range 0 to 16777215 := 16777215;
+ NUMBER_OF_GBE_LINKS : integer range 1 to 4 := 4;
+ LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_PING : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_ARP : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_DHCP : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_READOUT : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_SLOWCTRL : std_logic_vector(3 downto 0) := "1111";
+ LINK_HAS_FWD : std_logic_vector(3 downto 0) := "1111"
+ );
+ port(
+ CLK_SYS_IN : in std_logic;
+ CLK_125_IN : in std_logic;
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
+
+ TRIGGER_IN : in std_logic; -- for debug purpose only
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ -- SlowControl
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- IP configuration
+ BUS_IP_RX : in CTRLBUS_RX;
+ BUS_IP_TX : out CTRLBUS_TX;
+ -- Registers config
+ BUS_REG_RX : in CTRLBUS_RX;
+ BUS_REG_TX : out CTRLBUS_TX;
-- Forwarder
- FWD_DST_MAC_IN : in std_logic_vector(48 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_DST_IP_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_DST_UDP_IN : in std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0) := (others => '0');
- FWD_DATA_VALID_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_SOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_EOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
- FWD_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- MAKE_RESET_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(127 downto 0)
- );
+ FWD_DST_MAC_IN : in std_logic_vector(48 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DST_IP_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DST_UDP_IN : in std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0) := (others => '0');
+ FWD_DATA_VALID_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_SOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_EOP_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
+ FWD_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ FWD_FULL_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ MAKE_RESET_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(127 downto 0)
+ );
end entity gbe_wrapper;
architecture RTL of gbe_wrapper is
- signal mac_ready_conf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_reconf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_an_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_fifoavail : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_fifoeof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_fifoempty : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_fifofull : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal mac_tx_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_tx_discrfrm : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_tx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_tx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
- signal mac_tx_done : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_fifo_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
- signal mac_rx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
- signal mac_rx_write : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_eof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mac_rx_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- signal clk_125_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal clk_125_rx_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- signal cfg_gbe_enable : std_logic;
- signal cfg_ipu_enable : std_logic;
- signal cfg_mult_enable : std_logic;
- signal cfg_subevent_id : std_logic_vector(31 downto 0);
- signal cfg_subevent_dec : std_logic_vector(31 downto 0);
- signal cfg_queue_dec : std_logic_vector(31 downto 0);
- signal cfg_readout_ctr : std_logic_vector(23 downto 0);
- signal cfg_readout_ctr_valid : std_logic;
- signal cfg_insert_ttype : std_logic;
- signal cfg_max_sub : std_logic_vector(15 downto 0);
- signal cfg_max_queue : std_logic_vector(15 downto 0);
- signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
- signal cfg_max_single_sub : std_logic_vector(15 downto 0);
- signal cfg_additional_hdr : std_logic;
- signal cfg_soft_rst : std_logic;
- signal cfg_allow_rx : std_logic;
- signal cfg_max_frame : std_logic_vector(15 downto 0);
-
- signal dbg_hist, dbg_hist2 : hist_array;
-
- signal mac_0, mac_1, mac_2, mac_3 : std_logic_vector(47 downto 0);
- signal cfg_max_reply : std_logic_vector(31 downto 0);
-
- signal mlt_cts_number : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_code : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_information : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_readout_type : std_logic_vector(4 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_start_readout : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_data : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_readout_finished : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_length : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_cts_error_pattern : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_fee_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_fee_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_fee_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_fee_status : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_fee_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- signal mlt_gsc_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_init_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_init_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_init_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_init_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_reply_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_reply_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_reply_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_reply_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- signal mlt_gsc_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
-
- signal local_cts_number : std_logic_vector(15 downto 0);
- signal local_cts_code : std_logic_vector(7 downto 0);
- signal local_cts_information : std_logic_vector(7 downto 0);
- signal local_cts_readout_type : std_logic_vector(3 downto 0);
- signal local_cts_start_readout : std_logic;
- signal local_cts_readout_finished : std_logic;
- signal local_cts_status_bits : std_logic_vector(31 downto 0);
- signal local_fee_data : std_logic_vector(15 downto 0);
- signal local_fee_dataready : std_logic;
- signal local_fee_read : std_logic;
- signal local_fee_status_bits : std_logic_vector(31 downto 0);
- signal local_fee_busy : std_logic;
- signal dhcp_done : std_logic_vector(3 downto 0);
- signal all_links_ready : std_logic;
- signal monitor_rx_frames, monitor_rx_bytes, monitor_tx_frames, monitor_tx_bytes, monitor_tx_packets, monitor_dropped : std_logic_vector(4 * 32 - 1 downto 0);
- signal sum_rx_frames, sum_rx_bytes, sum_tx_frames, sum_tx_bytes, sum_tx_packets, sum_dropped : std_logic_vector(31 downto 0);
-
- signal busip0, busip1, busip2, busip3 : CTRLBUS_TX;
- signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
- --attribute nopad : string;
- --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true";
-
- signal dummy_event : std_logic_vector(15 downto 0);
- signal dummy_mode : std_logic;
- signal make_reset0, make_reset1, make_reset2, make_reset3 : std_logic := '0';
- signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
-
- signal cfg_autothrottle : std_logic;
- signal cfg_throttle_pause : std_logic_vector(15 downto 0);
-
- signal issue_reboot : std_logic_vector(3 downto 0);
+ signal mac_ready_conf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_reconf : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_an_ready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_fifoavail : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_fifoeof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_fifoempty : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_fifofull : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal mac_tx_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_tx_discrfrm : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_tx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_tx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
+ signal mac_tx_done : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_fifo_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_stats : std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
+ signal mac_rx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+ signal mac_rx_write : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_stat_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_eof : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mac_rx_err : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ signal clk_125_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal clk_125_rx_from_pcs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ signal cfg_gbe_enable : std_logic;
+ signal cfg_ipu_enable : std_logic;
+ signal cfg_mult_enable : std_logic;
+ signal cfg_subevent_id : std_logic_vector(31 downto 0);
+ signal cfg_subevent_dec : std_logic_vector(31 downto 0);
+ signal cfg_queue_dec : std_logic_vector(31 downto 0);
+ signal cfg_readout_ctr : std_logic_vector(23 downto 0);
+ signal cfg_readout_ctr_valid : std_logic;
+ signal cfg_insert_ttype : std_logic;
+ signal cfg_max_sub : std_logic_vector(15 downto 0);
+ signal cfg_max_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_single_sub : std_logic_vector(15 downto 0);
+ signal cfg_additional_hdr : std_logic;
+ signal cfg_soft_rst : std_logic;
+ signal cfg_allow_rx : std_logic;
+ signal cfg_max_frame : std_logic_vector(15 downto 0);
+
+ signal dbg_hist, dbg_hist2 : hist_array;
+
+ signal mac_0, mac_1, mac_2, mac_3 : std_logic_vector(47 downto 0);
+ signal cfg_max_reply : std_logic_vector(31 downto 0);
+
+ signal mlt_cts_number : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_code : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_information : std_logic_vector(8 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_readout_type : std_logic_vector(4 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_start_readout : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_data : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_readout_finished : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_length : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_cts_error_pattern : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_fee_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_fee_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_fee_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_fee_status : std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_fee_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ signal mlt_gsc_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_init_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_init_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_init_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_init_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_reply_dataready : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_reply_data : std_logic_vector(16 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_reply_packet : std_logic_vector(3 * NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_reply_read : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ signal mlt_gsc_busy : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+ signal local_cts_number : std_logic_vector(15 downto 0);
+ signal local_cts_code : std_logic_vector(7 downto 0);
+ signal local_cts_information : std_logic_vector(7 downto 0);
+ signal local_cts_readout_type : std_logic_vector(3 downto 0);
+ signal local_cts_start_readout : std_logic;
+ signal local_cts_readout_finished : std_logic;
+ signal local_cts_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_data : std_logic_vector(15 downto 0);
+ signal local_fee_dataready : std_logic;
+ signal local_fee_read : std_logic;
+ signal local_fee_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_busy : std_logic;
+ signal dhcp_done : std_logic_vector(3 downto 0);
+ signal all_links_ready : std_logic;
+ signal monitor_rx_frames, monitor_rx_bytes, monitor_tx_frames, monitor_tx_bytes, monitor_tx_packets, monitor_dropped : std_logic_vector(4 * 32 - 1 downto 0);
+ signal sum_rx_frames, sum_rx_bytes, sum_tx_frames, sum_tx_bytes, sum_tx_packets, sum_dropped : std_logic_vector(31 downto 0);
+
+ signal busip0, busip1, busip2, busip3 : CTRLBUS_TX;
+ signal SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+ --attribute nopad : string;
+ --attribute nopad of SD_RXD_P_IN, SD_RXD_N_IN, SD_TXD_P_OUT, SD_TXD_N_OUT : signal is "true";
+
+ signal dummy_event : std_logic_vector(15 downto 0);
+ signal dummy_mode : std_logic;
+ signal make_reset0, make_reset1, make_reset2, make_reset3 : std_logic := '0';
+ signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+
+ signal cfg_autothrottle : std_logic;
+ signal cfg_throttle_pause : std_logic_vector(15 downto 0);
+
+ signal issue_reboot : std_logic_vector(3 downto 0);
signal my_ip : std_logic_vector(127 downto 0);
begin
- mac_impl_gen : if DO_SIMULATION = 0 generate
- mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
- mac_1 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"1" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
- mac_2 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"2" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
- mac_3 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"3" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
- end generate mac_impl_gen;
-
- mac_sim_gen : if DO_SIMULATION = 1 generate
- mac_0 <= x"ffffffffffff";
- mac_1 <= x"ffffffffffff";
- mac_2 <= x"ffffffffffff";
- mac_3 <= x"ffffffffffff";
- end generate mac_sim_gen;
-
- all_links_ready <= '1' when dhcp_done = x"f" else '0';
-
- MAKE_RESET_OUT <= '1' when make_reset3 = '1' or make_reset2 = '1' or make_reset1 = '1' or make_reset0 = '1' else '0';
-
- ISSUE_REBOOT_OUT <= '0' when issue_reboot = "0000" else '1';
-
- physical_impl_gen : if DO_SIMULATION = 0 generate
- physical : entity work.gbe_med_interface
- generic map(DO_SIMULATION => DO_SIMULATION,
- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS,
- LINKS_ACTIVE => LINKS_ACTIVE)
- port map(
- RESET => RESET,
- GSR_N => GSR_N,
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_OUT => clk_125_from_pcs,
- CLK_125_IN => CLK_125_IN,
- CLK_125_RX_OUT => clk_125_rx_from_pcs,
- MAC_READY_CONF_OUT => mac_ready_conf,
- MAC_RECONF_IN => mac_reconf,
- MAC_AN_READY_OUT => mac_an_ready,
- MAC_FIFOAVAIL_IN => mac_fifoavail,
- MAC_FIFOEOF_IN => mac_fifoeof,
- MAC_FIFOEMPTY_IN => mac_fifoempty,
- MAC_RX_FIFOFULL_IN => mac_rx_fifofull,
- MAC_TX_DATA_IN => mac_tx_data,
- MAC_TX_READ_OUT => mac_tx_read,
- MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm,
- MAC_TX_STAT_EN_OUT => mac_tx_stat_en,
- MAC_TX_STATS_OUT => mac_tx_stats,
- MAC_TX_DONE_OUT => mac_tx_done,
- MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err,
- MAC_RX_STATS_OUT => mac_rx_stats,
- MAC_RX_DATA_OUT => mac_rx_data,
- MAC_RX_WRITE_OUT => mac_rx_write,
- MAC_RX_STAT_EN_OUT => mac_rx_stat_en,
- MAC_RX_EOF_OUT => mac_rx_eof,
- MAC_RX_ERROR_OUT => mac_rx_err,
- SD_RXD_P_IN => SD_RXD_P_IN,
- SD_RXD_N_IN => SD_RXD_N_IN,
- SD_TXD_P_OUT => SD_TXD_P_OUT,
- SD_TXD_N_OUT => SD_TXD_N_OUT,
- SD_PRSNT_N_IN => SD_PRSNT_N_IN,
- SD_LOS_IN => SD_LOS_IN,
- SD_TXDIS_OUT => SD_TXDIS_OUT,
- DEBUG_OUT => open
- );
- end generate physical_impl_gen;
-
- -- sfp8
- GEN_LINK_3 : if (LINKS_ACTIVE(3) = '1') generate
- gbe_inst3 : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- INCLUDE_READOUT => LINK_HAS_READOUT(3),
- INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(3),
- INCLUDE_DHCP => LINK_HAS_DHCP(3),
- INCLUDE_ARP => LINK_HAS_ARP(3),
- INCLUDE_PING => LINK_HAS_PING(3),
+ mac_impl_gen : if DO_SIMULATION = 0 generate
+ mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+ mac_1 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"1" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+ mac_2 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"2" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+ mac_3 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"3" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+ end generate mac_impl_gen;
+
+ mac_sim_gen : if DO_SIMULATION = 1 generate
+ mac_0 <= x"ffffffffffff";
+ mac_1 <= x"ffffffffffff";
+ mac_2 <= x"ffffffffffff";
+ mac_3 <= x"ffffffffffff";
+ end generate mac_sim_gen;
+
+ all_links_ready <= '1' when dhcp_done = x"f" else '0';
+
+ MAKE_RESET_OUT <= '1' when make_reset3 = '1' or make_reset2 = '1' or make_reset1 = '1' or make_reset0 = '1' else '0';
+
+ ISSUE_REBOOT_OUT <= '0' when issue_reboot = "0000" else '1';
+
+ physical_impl_gen : if DO_SIMULATION = 0 generate
+ physical : entity work.gbe_med_interface
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS,
+ LINKS_ACTIVE => LINKS_ACTIVE
+ )
+ port map(
+ RESET => RESET,
+ GSR_N => GSR_N,
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_OUT => clk_125_from_pcs,
+ CLK_125_IN => CLK_125_IN,
+ CLK_125_RX_OUT => clk_125_rx_from_pcs,
+ MAC_READY_CONF_OUT => mac_ready_conf,
+ MAC_RECONF_IN => mac_reconf,
+ MAC_AN_READY_OUT => mac_an_ready,
+ MAC_FIFOAVAIL_IN => mac_fifoavail,
+ MAC_FIFOEOF_IN => mac_fifoeof,
+ MAC_FIFOEMPTY_IN => mac_fifoempty,
+ MAC_RX_FIFOFULL_IN => mac_rx_fifofull,
+ MAC_TX_DATA_IN => mac_tx_data,
+ MAC_TX_READ_OUT => mac_tx_read,
+ MAC_TX_DISCRFRM_OUT => mac_tx_discrfrm,
+ MAC_TX_STAT_EN_OUT => mac_tx_stat_en,
+ MAC_TX_STATS_OUT => mac_tx_stats,
+ MAC_TX_DONE_OUT => mac_tx_done,
+ MAC_RX_FIFO_ERR_OUT => mac_rx_fifo_err,
+ MAC_RX_STATS_OUT => mac_rx_stats,
+ MAC_RX_DATA_OUT => mac_rx_data,
+ MAC_RX_WRITE_OUT => mac_rx_write,
+ MAC_RX_STAT_EN_OUT => mac_rx_stat_en,
+ MAC_RX_EOF_OUT => mac_rx_eof,
+ MAC_RX_ERROR_OUT => mac_rx_err,
+ SD_RXD_P_IN => SD_RXD_P_IN,
+ SD_RXD_N_IN => SD_RXD_N_IN,
+ SD_TXD_P_OUT => SD_TXD_P_OUT,
+ SD_TXD_N_OUT => SD_TXD_N_OUT,
+ SD_PRSNT_N_IN => SD_PRSNT_N_IN,
+ SD_LOS_IN => SD_LOS_IN,
+ SD_TXDIS_OUT => SD_TXDIS_OUT,
+ DEBUG_OUT => open
+ );
+ end generate physical_impl_gen;
+
+ -- sfp8
+ GEN_LINK_3 : if (LINKS_ACTIVE(3) = '1') generate
+ gbe_inst3 : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ INCLUDE_READOUT => LINK_HAS_READOUT(3),
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(3),
+ INCLUDE_DHCP => LINK_HAS_DHCP(3),
+ INCLUDE_ARP => LINK_HAS_ARP(3),
+ INCLUDE_PING => LINK_HAS_PING(3),
INCLUDE_FWD => LINK_HAS_FWD(3),
- FRAME_BUFFER_SIZE => 1,
- READOUT_BUFFER_SIZE => 4,
- SLOWCTRL_BUFFER_SIZE => 2,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY => FIXED_DELAY)
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_IN => CLK_125_IN,
- CLK_RX_125_IN => clk_125_rx_from_pcs(3),
- RESET => RESET,
- GSR_N => GSR_N,
- MY_MAC_IN => mac_3,
- DHCP_DONE_OUT => dhcp_done(3),
- MY_IP_OUT => my_ip(127 downto 96),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(3),
- MAC_READY_CONF_IN => mac_ready_conf(3),
- MAC_RECONF_OUT => mac_reconf(3),
- MAC_AN_READY_IN => mac_an_ready(3),
- MAC_FIFOAVAIL_OUT => mac_fifoavail(3),
- MAC_FIFOEOF_OUT => mac_fifoeof(3),
- MAC_FIFOEMPTY_OUT => mac_fifoempty(3),
- MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(3),
- MAC_TX_DATA_OUT => mac_tx_data(4 * 8 - 1 downto 3 * 8),
- MAC_TX_READ_IN => mac_tx_read(3),
- MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(3),
- MAC_TX_STAT_EN_IN => mac_tx_stat_en(3),
- MAC_TX_STATS_IN => mac_tx_stats(4 * 31 - 1 downto 3 * 31),
- MAC_TX_DONE_IN => mac_tx_done(3),
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(3),
- MAC_RX_STATS_IN => mac_rx_stats(4 * 32 - 1 downto 3 * 32),
- MAC_RX_DATA_IN => mac_rx_data(4 * 8 - 1 downto 3 * 8),
- MAC_RX_WRITE_IN => mac_rx_write(3),
- MAC_RX_STAT_EN_IN => mac_rx_stat_en(3),
- MAC_RX_EOF_IN => mac_rx_eof(3),
- MAC_RX_ERROR_IN => mac_rx_err(3),
- CTS_NUMBER_IN => mlt_cts_number(4 * 16 - 1 downto 3 * 16),
- CTS_CODE_IN => mlt_cts_code(4 * 8 - 1 downto 3 * 8),
- CTS_INFORMATION_IN => mlt_cts_information(4 * 8 - 1 downto 3 * 8),
- CTS_READOUT_TYPE_IN => mlt_cts_readout_type(4 * 4 - 1 downto 3 * 4),
- CTS_START_READOUT_IN => mlt_cts_start_readout(3),
- CTS_DATA_OUT => mlt_cts_data(4 * 32 - 1 downto 3 * 32),
- CTS_DATAREADY_OUT => mlt_cts_dataready(3),
- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(3),
- CTS_READ_IN => mlt_cts_read(3),
- CTS_LENGTH_OUT => mlt_cts_length(4 * 16 - 1 downto 3 * 16),
- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(4 * 32 - 1 downto 3 * 32),
- FEE_DATA_IN => mlt_fee_data(4 * 16 - 1 downto 3 * 16),
- FEE_DATAREADY_IN => mlt_fee_dataready(3),
- FEE_READ_OUT => mlt_fee_read(3),
- FEE_STATUS_BITS_IN => mlt_fee_status(4 * 32 - 1 downto 3 * 32),
- FEE_BUSY_IN => mlt_fee_busy(3),
- GSC_CLK_IN => mlt_gsc_clk(3),
- GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(3),
- GSC_INIT_DATA_OUT => mlt_gsc_init_data(4 * 16 - 1 downto 3 * 16),
- GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(4 * 3 - 1 downto 3 * 3),
- GSC_INIT_READ_IN => mlt_gsc_init_read(3),
- GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(3),
- GSC_REPLY_DATA_IN => mlt_gsc_reply_data(4 * 16 - 1 downto 3 * 16),
- GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(4 * 3 - 1 downto 3 * 3),
- GSC_REPLY_READ_OUT => mlt_gsc_reply_read(3),
- GSC_BUSY_IN => mlt_gsc_busy(3),
- SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
- SLV_READ_IN => BUS_IP_RX.read,
- SLV_WRITE_IN => BUS_IP_RX.write,
- SLV_BUSY_OUT => busip3.nack,
- SLV_ACK_OUT => busip3.ack,
- SLV_DATA_IN => BUS_IP_RX.data,
- SLV_DATA_OUT => busip3.data,
- CFG_GBE_ENABLE_IN => cfg_gbe_enable,
- CFG_IPU_ENABLE_IN => cfg_ipu_enable,
- CFG_MULT_ENABLE_IN => cfg_mult_enable,
- CFG_MAX_FRAME_IN => cfg_max_frame,
- CFG_ALLOW_RX_IN => cfg_allow_rx,
- CFG_SOFT_RESET_IN => cfg_soft_rst,
- CFG_SUBEVENT_ID_IN => cfg_subevent_id,
- CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
- CFG_QUEUE_DEC_IN => cfg_queue_dec,
- CFG_READOUT_CTR_IN => cfg_readout_ctr,
- CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
- CFG_MAX_SUB_IN => cfg_max_sub,
- CFG_MAX_QUEUE_IN => cfg_max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
- CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
- CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
- CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
- CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => clk_125_rx_from_pcs(3),
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_3,
+ DHCP_DONE_OUT => dhcp_done(3),
+ MY_IP_OUT => my_ip(127 downto 96),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(3),
+ MAC_READY_CONF_IN => mac_ready_conf(3),
+ MAC_RECONF_OUT => mac_reconf(3),
+ MAC_AN_READY_IN => mac_an_ready(3),
+ MAC_FIFOAVAIL_OUT => mac_fifoavail(3),
+ MAC_FIFOEOF_OUT => mac_fifoeof(3),
+ MAC_FIFOEMPTY_OUT => mac_fifoempty(3),
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(3),
+ MAC_TX_DATA_OUT => mac_tx_data(4 * 8 - 1 downto 3 * 8),
+ MAC_TX_READ_IN => mac_tx_read(3),
+ MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(3),
+ MAC_TX_STAT_EN_IN => mac_tx_stat_en(3),
+ MAC_TX_STATS_IN => mac_tx_stats(4 * 31 - 1 downto 3 * 31),
+ MAC_TX_DONE_IN => mac_tx_done(3),
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(3),
+ MAC_RX_STATS_IN => mac_rx_stats(4 * 32 - 1 downto 3 * 32),
+ MAC_RX_DATA_IN => mac_rx_data(4 * 8 - 1 downto 3 * 8),
+ MAC_RX_WRITE_IN => mac_rx_write(3),
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en(3),
+ MAC_RX_EOF_IN => mac_rx_eof(3),
+ MAC_RX_ERROR_IN => mac_rx_err(3),
+ CTS_NUMBER_IN => mlt_cts_number(4 * 16 - 1 downto 3 * 16),
+ CTS_CODE_IN => mlt_cts_code(4 * 8 - 1 downto 3 * 8),
+ CTS_INFORMATION_IN => mlt_cts_information(4 * 8 - 1 downto 3 * 8),
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type(4 * 4 - 1 downto 3 * 4),
+ CTS_START_READOUT_IN => mlt_cts_start_readout(3),
+ CTS_DATA_OUT => mlt_cts_data(4 * 32 - 1 downto 3 * 32),
+ CTS_DATAREADY_OUT => mlt_cts_dataready(3),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(3),
+ CTS_READ_IN => mlt_cts_read(3),
+ CTS_LENGTH_OUT => mlt_cts_length(4 * 16 - 1 downto 3 * 16),
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(4 * 32 - 1 downto 3 * 32),
+ FEE_DATA_IN => mlt_fee_data(4 * 16 - 1 downto 3 * 16),
+ FEE_DATAREADY_IN => mlt_fee_dataready(3),
+ FEE_READ_OUT => mlt_fee_read(3),
+ FEE_STATUS_BITS_IN => mlt_fee_status(4 * 32 - 1 downto 3 * 32),
+ FEE_BUSY_IN => mlt_fee_busy(3),
+ GSC_CLK_IN => mlt_gsc_clk(3),
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(3),
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data(4 * 16 - 1 downto 3 * 16),
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(4 * 3 - 1 downto 3 * 3),
+ GSC_INIT_READ_IN => mlt_gsc_init_read(3),
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(3),
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data(4 * 16 - 1 downto 3 * 16),
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(4 * 3 - 1 downto 3 * 3),
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read(3),
+ GSC_BUSY_IN => mlt_gsc_busy(3),
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip3.nack,
+ SLV_ACK_OUT => busip3.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip3.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
FWD_DST_MAC_IN => FWD_DST_MAC_IN(4 * 48 - 1 downto 3 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(4 * 32 - 1 downto 3 * 32),
FWD_READY_OUT => FWD_READY_OUT(3),
FWD_FULL_OUT => FWD_FULL_OUT(3),
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames(4 * 32 - 1 downto 3 * 32),
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes(4 * 32 - 1 downto 3 * 32),
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames(4 * 32 - 1 downto 3 * 32),
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes(4 * 32 - 1 downto 3 * 32),
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets(4 * 32 - 1 downto 3 * 32),
- MONITOR_DROPPED_OUT => monitor_dropped(4 * 32 - 1 downto 3 * 32),
- MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
- MAKE_RESET_OUT => make_reset3
- );
- end generate GEN_LINK_3;
-
- NO_LINK3_GEN : if (LINKS_ACTIVE(3) = '0') generate
- make_reset3 <= '0';
- busip3.data <= (others => '0');
- busip3.ack <= '0';
- busip3.nack <= '0';
- monitor_rx_frames(4 * 32 - 1 downto 3 * 32) <= (others => '0');
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames(4 * 32 - 1 downto 3 * 32),
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes(4 * 32 - 1 downto 3 * 32),
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames(4 * 32 - 1 downto 3 * 32),
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes(4 * 32 - 1 downto 3 * 32),
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets(4 * 32 - 1 downto 3 * 32),
+ MONITOR_DROPPED_OUT => monitor_dropped(4 * 32 - 1 downto 3 * 32),
+ MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
+ MAKE_RESET_OUT => make_reset3
+ );
+ end generate GEN_LINK_3;
+
+ NO_LINK3_GEN : if (LINKS_ACTIVE(3) = '0') generate
+ make_reset3 <= '0';
+ busip3.data <= (others => '0');
+ busip3.ack <= '0';
+ busip3.nack <= '0';
+ monitor_rx_frames(4 * 32 - 1 downto 3 * 32) <= (others => '0');
monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) <= (others => '0');
monitor_tx_frames(4 * 32 - 1 downto 3 * 32) <= (others => '0');
monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) <= (others => '0');
mlt_cts_readout_finished(3) <= '0';
mlt_cts_length(4 * 16 - 1 downto 3 * 16) <= (others => '0');
mlt_cts_error_pattern(4 * 32 - 1 downto 3 * 32) <= (others => '0');
- end generate NO_LINK3_GEN;
-
- -- sfp7
- GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate
- gbe_inst2 : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
- RX_PATH_ENABLE => 1,
- INCLUDE_READOUT => LINK_HAS_READOUT(2),
- INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(2),
- INCLUDE_DHCP => LINK_HAS_DHCP(2),
- INCLUDE_ARP => LINK_HAS_ARP(2),
- INCLUDE_PING => LINK_HAS_PING(2),
- INCLUDE_FWD => LINK_HAS_FWD(2),
- FRAME_BUFFER_SIZE => 1,
- READOUT_BUFFER_SIZE => 4,
- SLOWCTRL_BUFFER_SIZE => 2,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY => FIXED_DELAY)
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_IN => CLK_125_IN,
- CLK_RX_125_IN => clk_125_rx_from_pcs(2),
- RESET => RESET,
- GSR_N => GSR_N,
- MY_MAC_IN => mac_2,
- DHCP_DONE_OUT => dhcp_done(2),
- MY_IP_OUT => my_ip(95 downto 64),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(2),
- MAC_READY_CONF_IN => mac_ready_conf(2),
- MAC_RECONF_OUT => mac_reconf(2),
- MAC_AN_READY_IN => mac_an_ready(2),
- MAC_FIFOAVAIL_OUT => mac_fifoavail(2),
- MAC_FIFOEOF_OUT => mac_fifoeof(2),
- MAC_FIFOEMPTY_OUT => mac_fifoempty(2),
- MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(2),
- MAC_TX_DATA_OUT => mac_tx_data(3 * 8 - 1 downto 2 * 8),
- MAC_TX_READ_IN => mac_tx_read(2),
- MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(2),
- MAC_TX_STAT_EN_IN => mac_tx_stat_en(2),
- MAC_TX_STATS_IN => mac_tx_stats(3 * 31 - 1 downto 2 * 31),
- MAC_TX_DONE_IN => mac_tx_done(2),
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(2),
- MAC_RX_STATS_IN => mac_rx_stats(3 * 32 - 1 downto 2 * 32),
- MAC_RX_DATA_IN => mac_rx_data(3 * 8 - 1 downto 2 * 8),
- MAC_RX_WRITE_IN => mac_rx_write(2),
- MAC_RX_STAT_EN_IN => mac_rx_stat_en(2),
- MAC_RX_EOF_IN => mac_rx_eof(2),
- MAC_RX_ERROR_IN => mac_rx_err(2),
- CTS_NUMBER_IN => mlt_cts_number(3 * 16 - 1 downto 2 * 16),
- CTS_CODE_IN => mlt_cts_code(3 * 8 - 1 downto 2 * 8),
- CTS_INFORMATION_IN => mlt_cts_information(3 * 8 - 1 downto 2 * 8),
- CTS_READOUT_TYPE_IN => mlt_cts_readout_type(3 * 4 - 1 downto 2 * 4),
- CTS_START_READOUT_IN => mlt_cts_start_readout(2),
- CTS_DATA_OUT => mlt_cts_data(3 * 32 - 1 downto 2 * 32),
- CTS_DATAREADY_OUT => mlt_cts_dataready(2),
- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(2),
- CTS_READ_IN => mlt_cts_read(2),
- CTS_LENGTH_OUT => mlt_cts_length(3 * 16 - 1 downto 2 * 16),
- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32),
- FEE_DATA_IN => mlt_fee_data(3 * 16 - 1 downto 2 * 16),
- FEE_DATAREADY_IN => mlt_fee_dataready(2),
- FEE_READ_OUT => mlt_fee_read(2),
- FEE_STATUS_BITS_IN => mlt_fee_status(3 * 32 - 1 downto 2 * 32),
- FEE_BUSY_IN => mlt_fee_busy(2),
- GSC_CLK_IN => mlt_gsc_clk(2),
- GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(2),
- GSC_INIT_DATA_OUT => mlt_gsc_init_data(3 * 16 - 1 downto 2 * 16),
- GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(3 * 3 - 1 downto 2 * 3),
- GSC_INIT_READ_IN => mlt_gsc_init_read(2),
- GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(2),
- GSC_REPLY_DATA_IN => mlt_gsc_reply_data(3 * 16 - 1 downto 2 * 16),
- GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(3 * 3 - 1 downto 2 * 3),
- GSC_REPLY_READ_OUT => mlt_gsc_reply_read(2),
- GSC_BUSY_IN => mlt_gsc_busy(2),
- SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
- SLV_READ_IN => BUS_IP_RX.read,
- SLV_WRITE_IN => BUS_IP_RX.write,
- SLV_BUSY_OUT => busip2.nack,
- SLV_ACK_OUT => busip2.ack,
- SLV_DATA_IN => BUS_IP_RX.data,
- SLV_DATA_OUT => busip2.data,
- CFG_GBE_ENABLE_IN => cfg_gbe_enable,
- CFG_IPU_ENABLE_IN => cfg_ipu_enable,
- CFG_MULT_ENABLE_IN => cfg_mult_enable,
- CFG_MAX_FRAME_IN => cfg_max_frame,
- CFG_ALLOW_RX_IN => cfg_allow_rx,
- CFG_SOFT_RESET_IN => cfg_soft_rst,
- CFG_SUBEVENT_ID_IN => cfg_subevent_id,
- CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
- CFG_QUEUE_DEC_IN => cfg_queue_dec,
- CFG_READOUT_CTR_IN => cfg_readout_ctr,
- CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
- CFG_MAX_SUB_IN => cfg_max_sub,
- CFG_MAX_QUEUE_IN => cfg_max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
- CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
- CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
- CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
- CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ end generate NO_LINK3_GEN;
+
+ -- sfp7
+ GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate
+ gbe_inst2 : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => 1,
+ INCLUDE_READOUT => LINK_HAS_READOUT(2),
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(2),
+ INCLUDE_DHCP => LINK_HAS_DHCP(2),
+ INCLUDE_ARP => LINK_HAS_ARP(2),
+ INCLUDE_PING => LINK_HAS_PING(2),
+ INCLUDE_FWD => LINK_HAS_FWD(2),
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => clk_125_rx_from_pcs(2),
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_2,
+ DHCP_DONE_OUT => dhcp_done(2),
+ MY_IP_OUT => my_ip(95 downto 64),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(2),
+ MAC_READY_CONF_IN => mac_ready_conf(2),
+ MAC_RECONF_OUT => mac_reconf(2),
+ MAC_AN_READY_IN => mac_an_ready(2),
+ MAC_FIFOAVAIL_OUT => mac_fifoavail(2),
+ MAC_FIFOEOF_OUT => mac_fifoeof(2),
+ MAC_FIFOEMPTY_OUT => mac_fifoempty(2),
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(2),
+ MAC_TX_DATA_OUT => mac_tx_data(3 * 8 - 1 downto 2 * 8),
+ MAC_TX_READ_IN => mac_tx_read(2),
+ MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(2),
+ MAC_TX_STAT_EN_IN => mac_tx_stat_en(2),
+ MAC_TX_STATS_IN => mac_tx_stats(3 * 31 - 1 downto 2 * 31),
+ MAC_TX_DONE_IN => mac_tx_done(2),
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(2),
+ MAC_RX_STATS_IN => mac_rx_stats(3 * 32 - 1 downto 2 * 32),
+ MAC_RX_DATA_IN => mac_rx_data(3 * 8 - 1 downto 2 * 8),
+ MAC_RX_WRITE_IN => mac_rx_write(2),
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en(2),
+ MAC_RX_EOF_IN => mac_rx_eof(2),
+ MAC_RX_ERROR_IN => mac_rx_err(2),
+ CTS_NUMBER_IN => mlt_cts_number(3 * 16 - 1 downto 2 * 16),
+ CTS_CODE_IN => mlt_cts_code(3 * 8 - 1 downto 2 * 8),
+ CTS_INFORMATION_IN => mlt_cts_information(3 * 8 - 1 downto 2 * 8),
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type(3 * 4 - 1 downto 2 * 4),
+ CTS_START_READOUT_IN => mlt_cts_start_readout(2),
+ CTS_DATA_OUT => mlt_cts_data(3 * 32 - 1 downto 2 * 32),
+ CTS_DATAREADY_OUT => mlt_cts_dataready(2),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(2),
+ CTS_READ_IN => mlt_cts_read(2),
+ CTS_LENGTH_OUT => mlt_cts_length(3 * 16 - 1 downto 2 * 16),
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32),
+ FEE_DATA_IN => mlt_fee_data(3 * 16 - 1 downto 2 * 16),
+ FEE_DATAREADY_IN => mlt_fee_dataready(2),
+ FEE_READ_OUT => mlt_fee_read(2),
+ FEE_STATUS_BITS_IN => mlt_fee_status(3 * 32 - 1 downto 2 * 32),
+ FEE_BUSY_IN => mlt_fee_busy(2),
+ GSC_CLK_IN => mlt_gsc_clk(2),
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(2),
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data(3 * 16 - 1 downto 2 * 16),
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(3 * 3 - 1 downto 2 * 3),
+ GSC_INIT_READ_IN => mlt_gsc_init_read(2),
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(2),
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data(3 * 16 - 1 downto 2 * 16),
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(3 * 3 - 1 downto 2 * 3),
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read(2),
+ GSC_BUSY_IN => mlt_gsc_busy(2),
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip2.nack,
+ SLV_ACK_OUT => busip2.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip2.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
FWD_DST_MAC_IN => FWD_DST_MAC_IN(3 * 48 - 1 downto 2 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(3 * 32 - 1 downto 2 * 32),
FWD_DST_UDP_IN => FWD_DST_UDP_IN(3 * 16 - 1 downto 2 * 16),
FWD_READY_OUT => FWD_READY_OUT(2),
FWD_FULL_OUT => FWD_FULL_OUT(2),
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames(3 * 32 - 1 downto 2 * 32),
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes(3 * 32 - 1 downto 2 * 32),
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames(3 * 32 - 1 downto 2 * 32),
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes(3 * 32 - 1 downto 2 * 32),
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets(3 * 32 - 1 downto 2 * 32),
- MONITOR_DROPPED_OUT => monitor_dropped(3 * 32 - 1 downto 2 * 32),
- MONITOR_GEN_DBG_OUT => open,
- MAKE_RESET_OUT => make_reset2
- );
- end generate GEN_LINK_2;
-
- NO_LINK2_GEN : if (LINKS_ACTIVE(2) = '0') generate
- make_reset2 <= '0';
- busip2.data <= (others => '0');
- busip2.ack <= '0';
- busip2.nack <= '0';
-
- monitor_rx_frames(3 * 32 - 1 downto 2 * 32) <= (others => '0');
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames(3 * 32 - 1 downto 2 * 32),
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes(3 * 32 - 1 downto 2 * 32),
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames(3 * 32 - 1 downto 2 * 32),
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes(3 * 32 - 1 downto 2 * 32),
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets(3 * 32 - 1 downto 2 * 32),
+ MONITOR_DROPPED_OUT => monitor_dropped(3 * 32 - 1 downto 2 * 32),
+ MONITOR_GEN_DBG_OUT => open,
+ MAKE_RESET_OUT => make_reset2
+ );
+ end generate GEN_LINK_2;
+
+ NO_LINK2_GEN : if (LINKS_ACTIVE(2) = '0') generate
+ make_reset2 <= '0';
+ busip2.data <= (others => '0');
+ busip2.ack <= '0';
+ busip2.nack <= '0';
+
+ monitor_rx_frames(3 * 32 - 1 downto 2 * 32) <= (others => '0');
monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) <= (others => '0');
monitor_tx_frames(3 * 32 - 1 downto 2 * 32) <= (others => '0');
monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) <= (others => '0');
mlt_cts_readout_finished(2) <= '0';
mlt_cts_length(3 * 16 - 1 downto 2 * 16) <= (others => '0');
mlt_cts_error_pattern(3 * 32 - 1 downto 2 * 32) <= (others => '0');
- end generate NO_LINK2_GEN;
-
- -- sfp6
- GEN_LINK_1 : if (LINKS_ACTIVE(1) = '1') generate
- gbe_inst1 : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
- RX_PATH_ENABLE => 1,
- INCLUDE_READOUT => LINK_HAS_READOUT(1),
- INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(1),
- INCLUDE_DHCP => LINK_HAS_DHCP(1),
- INCLUDE_ARP => LINK_HAS_ARP(1),
- INCLUDE_PING => LINK_HAS_PING(1),
- INCLUDE_FWD => LINK_HAS_FWD(1),
- FRAME_BUFFER_SIZE => 1,
- READOUT_BUFFER_SIZE => 4,
- SLOWCTRL_BUFFER_SIZE => 2,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY => FIXED_DELAY)
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_IN => CLK_125_IN,
- CLK_RX_125_IN => clk_125_rx_from_pcs(1),
- RESET => RESET,
- GSR_N => GSR_N,
- MY_MAC_IN => mac_1,
- DHCP_DONE_OUT => dhcp_done(1),
- MY_IP_OUT => my_ip(63 downto 32),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(1),
- MAC_READY_CONF_IN => mac_ready_conf(1),
- MAC_RECONF_OUT => mac_reconf(1),
- MAC_AN_READY_IN => mac_an_ready(1),
- MAC_FIFOAVAIL_OUT => mac_fifoavail(1),
- MAC_FIFOEOF_OUT => mac_fifoeof(1),
- MAC_FIFOEMPTY_OUT => mac_fifoempty(1),
- MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(1),
- MAC_TX_DATA_OUT => mac_tx_data(2 * 8 - 1 downto 1 * 8),
- MAC_TX_READ_IN => mac_tx_read(1),
- MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(1),
- MAC_TX_STAT_EN_IN => mac_tx_stat_en(1),
- MAC_TX_STATS_IN => mac_tx_stats(2 * 31 - 1 downto 1 * 31),
- MAC_TX_DONE_IN => mac_tx_done(1),
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(1),
- MAC_RX_STATS_IN => mac_rx_stats(2 * 32 - 1 downto 1 * 32),
- MAC_RX_DATA_IN => mac_rx_data(2 * 8 - 1 downto 1 * 8),
- MAC_RX_WRITE_IN => mac_rx_write(1),
- MAC_RX_STAT_EN_IN => mac_rx_stat_en(1),
- MAC_RX_EOF_IN => mac_rx_eof(1),
- MAC_RX_ERROR_IN => mac_rx_err(1),
- CTS_NUMBER_IN => mlt_cts_number(2 * 16 - 1 downto 1 * 16),
- CTS_CODE_IN => mlt_cts_code(2 * 8 - 1 downto 1 * 8),
- CTS_INFORMATION_IN => mlt_cts_information(2 * 8 - 1 downto 1 * 8),
- CTS_READOUT_TYPE_IN => mlt_cts_readout_type(2 * 4 - 1 downto 1 * 4),
- CTS_START_READOUT_IN => mlt_cts_start_readout(1),
- CTS_DATA_OUT => mlt_cts_data(2 * 32 - 1 downto 1 * 32),
- CTS_DATAREADY_OUT => mlt_cts_dataready(1),
- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(1),
- CTS_READ_IN => mlt_cts_read(1),
- CTS_LENGTH_OUT => mlt_cts_length(2 * 16 - 1 downto 1 * 16),
- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32),
- FEE_DATA_IN => mlt_fee_data(2 * 16 - 1 downto 1 * 16),
- FEE_DATAREADY_IN => mlt_fee_dataready(1),
- FEE_READ_OUT => mlt_fee_read(1),
- FEE_STATUS_BITS_IN => mlt_fee_status(2 * 32 - 1 downto 1 * 32),
- FEE_BUSY_IN => mlt_fee_busy(1),
- GSC_CLK_IN => mlt_gsc_clk(1),
- GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(1),
- GSC_INIT_DATA_OUT => mlt_gsc_init_data(2 * 16 - 1 downto 1 * 16),
- GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(2 * 3 - 1 downto 1 * 3),
- GSC_INIT_READ_IN => mlt_gsc_init_read(1),
- GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(1),
- GSC_REPLY_DATA_IN => mlt_gsc_reply_data(2 * 16 - 1 downto 1 * 16),
- GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(2 * 3 - 1 downto 1 * 3),
- GSC_REPLY_READ_OUT => mlt_gsc_reply_read(1),
- GSC_BUSY_IN => mlt_gsc_busy(1),
- SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
- SLV_READ_IN => BUS_IP_RX.read,
- SLV_WRITE_IN => BUS_IP_RX.write,
- SLV_BUSY_OUT => busip1.nack,
- SLV_ACK_OUT => busip1.ack,
- SLV_DATA_IN => BUS_IP_RX.data,
- SLV_DATA_OUT => busip1.data,
- CFG_GBE_ENABLE_IN => cfg_gbe_enable,
- CFG_IPU_ENABLE_IN => cfg_ipu_enable,
- CFG_MULT_ENABLE_IN => cfg_mult_enable,
- CFG_MAX_FRAME_IN => cfg_max_frame,
- CFG_ALLOW_RX_IN => cfg_allow_rx,
- CFG_SOFT_RESET_IN => cfg_soft_rst,
- CFG_SUBEVENT_ID_IN => cfg_subevent_id,
- CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
- CFG_QUEUE_DEC_IN => cfg_queue_dec,
- CFG_READOUT_CTR_IN => cfg_readout_ctr,
- CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
- CFG_MAX_SUB_IN => cfg_max_sub,
- CFG_MAX_QUEUE_IN => cfg_max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
- CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
- CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
- CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
- CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ end generate NO_LINK2_GEN;
+
+ -- sfp6
+ GEN_LINK_1 : if (LINKS_ACTIVE(1) = '1') generate
+ gbe_inst1 : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => 1,
+ INCLUDE_READOUT => LINK_HAS_READOUT(1),
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(1),
+ INCLUDE_DHCP => LINK_HAS_DHCP(1),
+ INCLUDE_ARP => LINK_HAS_ARP(1),
+ INCLUDE_PING => LINK_HAS_PING(1),
+ INCLUDE_FWD => LINK_HAS_FWD(1),
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => clk_125_rx_from_pcs(1),
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_1,
+ DHCP_DONE_OUT => dhcp_done(1),
+ MY_IP_OUT => my_ip(63 downto 32),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(1),
+ MAC_READY_CONF_IN => mac_ready_conf(1),
+ MAC_RECONF_OUT => mac_reconf(1),
+ MAC_AN_READY_IN => mac_an_ready(1),
+ MAC_FIFOAVAIL_OUT => mac_fifoavail(1),
+ MAC_FIFOEOF_OUT => mac_fifoeof(1),
+ MAC_FIFOEMPTY_OUT => mac_fifoempty(1),
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(1),
+ MAC_TX_DATA_OUT => mac_tx_data(2 * 8 - 1 downto 1 * 8),
+ MAC_TX_READ_IN => mac_tx_read(1),
+ MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(1),
+ MAC_TX_STAT_EN_IN => mac_tx_stat_en(1),
+ MAC_TX_STATS_IN => mac_tx_stats(2 * 31 - 1 downto 1 * 31),
+ MAC_TX_DONE_IN => mac_tx_done(1),
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(1),
+ MAC_RX_STATS_IN => mac_rx_stats(2 * 32 - 1 downto 1 * 32),
+ MAC_RX_DATA_IN => mac_rx_data(2 * 8 - 1 downto 1 * 8),
+ MAC_RX_WRITE_IN => mac_rx_write(1),
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en(1),
+ MAC_RX_EOF_IN => mac_rx_eof(1),
+ MAC_RX_ERROR_IN => mac_rx_err(1),
+ CTS_NUMBER_IN => mlt_cts_number(2 * 16 - 1 downto 1 * 16),
+ CTS_CODE_IN => mlt_cts_code(2 * 8 - 1 downto 1 * 8),
+ CTS_INFORMATION_IN => mlt_cts_information(2 * 8 - 1 downto 1 * 8),
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type(2 * 4 - 1 downto 1 * 4),
+ CTS_START_READOUT_IN => mlt_cts_start_readout(1),
+ CTS_DATA_OUT => mlt_cts_data(2 * 32 - 1 downto 1 * 32),
+ CTS_DATAREADY_OUT => mlt_cts_dataready(1),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(1),
+ CTS_READ_IN => mlt_cts_read(1),
+ CTS_LENGTH_OUT => mlt_cts_length(2 * 16 - 1 downto 1 * 16),
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32),
+ FEE_DATA_IN => mlt_fee_data(2 * 16 - 1 downto 1 * 16),
+ FEE_DATAREADY_IN => mlt_fee_dataready(1),
+ FEE_READ_OUT => mlt_fee_read(1),
+ FEE_STATUS_BITS_IN => mlt_fee_status(2 * 32 - 1 downto 1 * 32),
+ FEE_BUSY_IN => mlt_fee_busy(1),
+ GSC_CLK_IN => mlt_gsc_clk(1),
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(1),
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data(2 * 16 - 1 downto 1 * 16),
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(2 * 3 - 1 downto 1 * 3),
+ GSC_INIT_READ_IN => mlt_gsc_init_read(1),
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(1),
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data(2 * 16 - 1 downto 1 * 16),
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(2 * 3 - 1 downto 1 * 3),
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read(1),
+ GSC_BUSY_IN => mlt_gsc_busy(1),
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip1.nack,
+ SLV_ACK_OUT => busip1.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip1.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
FWD_DST_MAC_IN => FWD_DST_MAC_IN(2 * 48 - 1 downto 1 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(2 * 32 - 1 downto 1 * 32),
FWD_READY_OUT => FWD_READY_OUT(1),
FWD_FULL_OUT => FWD_FULL_OUT(1),
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames(2 * 32 - 1 downto 1 * 32),
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes(2 * 32 - 1 downto 1 * 32),
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames(2 * 32 - 1 downto 1 * 32),
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes(2 * 32 - 1 downto 1 * 32),
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets(2 * 32 - 1 downto 1 * 32),
- MONITOR_DROPPED_OUT => monitor_dropped(2 * 32 - 1 downto 1 * 32),
- MONITOR_GEN_DBG_OUT => open,
- MAKE_RESET_OUT => make_reset1
- );
- end generate GEN_LINK_1;
-
- NO_LINK1_GEN : if (LINKS_ACTIVE(1) = '0') generate
- make_reset1 <= '0';
- busip1.data <= (others => '0');
- busip1.ack <= '0';
- busip1.nack <= '0';
-
- monitor_rx_frames(2 * 32 - 1 downto 1 * 32) <= (others => '0');
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames(2 * 32 - 1 downto 1 * 32),
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes(2 * 32 - 1 downto 1 * 32),
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames(2 * 32 - 1 downto 1 * 32),
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes(2 * 32 - 1 downto 1 * 32),
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets(2 * 32 - 1 downto 1 * 32),
+ MONITOR_DROPPED_OUT => monitor_dropped(2 * 32 - 1 downto 1 * 32),
+ MONITOR_GEN_DBG_OUT => open,
+ MAKE_RESET_OUT => make_reset1
+ );
+ end generate GEN_LINK_1;
+
+ NO_LINK1_GEN : if (LINKS_ACTIVE(1) = '0') generate
+ make_reset1 <= '0';
+ busip1.data <= (others => '0');
+ busip1.ack <= '0';
+ busip1.nack <= '0';
+
+ monitor_rx_frames(2 * 32 - 1 downto 1 * 32) <= (others => '0');
monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) <= (others => '0');
monitor_tx_frames(2 * 32 - 1 downto 1 * 32) <= (others => '0');
monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) <= (others => '0');
mlt_cts_readout_finished(1) <= '0';
mlt_cts_length(2 * 16 - 1 downto 1 * 16) <= (others => '0');
mlt_cts_error_pattern(2 * 32 - 1 downto 1 * 32) <= (others => '0');
- end generate NO_LINK1_GEN;
-
- -- sfp5
- GEN_LINK_0 : if (LINKS_ACTIVE(0) = '1') generate
- gbe_inst0 : entity work.gbe_logic_wrapper
- generic map(DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
- RX_PATH_ENABLE => 1,
- INCLUDE_READOUT => LINK_HAS_READOUT(0),
- INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0),
- INCLUDE_DHCP => LINK_HAS_DHCP(0),
- INCLUDE_ARP => LINK_HAS_ARP(0),
- INCLUDE_PING => LINK_HAS_PING(0),
- INCLUDE_FWD => LINK_HAS_FWD(0),
- FRAME_BUFFER_SIZE => 1,
- READOUT_BUFFER_SIZE => 4,
- SLOWCTRL_BUFFER_SIZE => 2,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY => FIXED_DELAY)
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- CLK_125_IN => CLK_125_IN,
- CLK_RX_125_IN => clk_125_rx_from_pcs(0),
- RESET => RESET,
- GSR_N => GSR_N,
- MY_MAC_IN => mac_0,
- DHCP_DONE_OUT => dhcp_done(0),
- MY_IP_OUT => my_ip(31 downto 0),
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => issue_reboot(0),
- MAC_READY_CONF_IN => mac_ready_conf(0),
- MAC_RECONF_OUT => mac_reconf(0),
- MAC_AN_READY_IN => mac_an_ready(0),
- MAC_FIFOAVAIL_OUT => mac_fifoavail(0),
- MAC_FIFOEOF_OUT => mac_fifoeof(0),
- MAC_FIFOEMPTY_OUT => mac_fifoempty(0),
- MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(0),
- MAC_TX_DATA_OUT => mac_tx_data(1 * 8 - 1 downto 0 * 8),
- MAC_TX_READ_IN => mac_tx_read(0),
- MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(0),
- MAC_TX_STAT_EN_IN => mac_tx_stat_en(0),
- MAC_TX_STATS_IN => mac_tx_stats(1 * 31 - 1 downto 0 * 31),
- MAC_TX_DONE_IN => mac_tx_done(0),
- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(0),
- MAC_RX_STATS_IN => mac_rx_stats(1 * 32 - 1 downto 0 * 32),
- MAC_RX_DATA_IN => mac_rx_data(1 * 8 - 1 downto 0 * 8),
- MAC_RX_WRITE_IN => mac_rx_write(0),
- MAC_RX_STAT_EN_IN => mac_rx_stat_en(0),
- MAC_RX_EOF_IN => mac_rx_eof(0),
- MAC_RX_ERROR_IN => mac_rx_err(0),
- CTS_NUMBER_IN => mlt_cts_number(1 * 16 - 1 downto 0 * 16),
- CTS_CODE_IN => mlt_cts_code(1 * 8 - 1 downto 0 * 8),
- CTS_INFORMATION_IN => mlt_cts_information(1 * 8 - 1 downto 0 * 8),
- CTS_READOUT_TYPE_IN => mlt_cts_readout_type(1 * 4 - 1 downto 0 * 4),
- CTS_START_READOUT_IN => mlt_cts_start_readout(0),
- CTS_DATA_OUT => mlt_cts_data(1 * 32 - 1 downto 0 * 32),
- CTS_DATAREADY_OUT => mlt_cts_dataready(0),
- CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
- CTS_READ_IN => mlt_cts_read(0),
- CTS_LENGTH_OUT => mlt_cts_length(1 * 16 - 1 downto 0 * 16),
- CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(1 * 32 - 1 downto 0 * 32),
- FEE_DATA_IN => mlt_fee_data(1 * 16 - 1 downto 0 * 16),
- FEE_DATAREADY_IN => mlt_fee_dataready(0),
- FEE_READ_OUT => mlt_fee_read(0),
- FEE_STATUS_BITS_IN => mlt_fee_status(1 * 32 - 1 downto 0 * 32),
- FEE_BUSY_IN => mlt_fee_busy(0),
- GSC_CLK_IN => mlt_gsc_clk(0),
- GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(0),
- GSC_INIT_DATA_OUT => mlt_gsc_init_data(1 * 16 - 1 downto 0 * 16),
- GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(1 * 3 - 1 downto 0 * 3),
- GSC_INIT_READ_IN => mlt_gsc_init_read(0),
- GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(0),
- GSC_REPLY_DATA_IN => mlt_gsc_reply_data(1 * 16 - 1 downto 0 * 16),
- GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(1 * 3 - 1 downto 0 * 3),
- GSC_REPLY_READ_OUT => mlt_gsc_reply_read(0),
- GSC_BUSY_IN => mlt_gsc_busy(0),
- SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
- SLV_READ_IN => BUS_IP_RX.read,
- SLV_WRITE_IN => BUS_IP_RX.write,
- SLV_BUSY_OUT => busip0.nack,
- SLV_ACK_OUT => busip0.ack,
- SLV_DATA_IN => BUS_IP_RX.data,
- SLV_DATA_OUT => busip0.data,
- CFG_GBE_ENABLE_IN => cfg_gbe_enable,
- CFG_IPU_ENABLE_IN => cfg_ipu_enable,
- CFG_MULT_ENABLE_IN => cfg_mult_enable,
- CFG_MAX_FRAME_IN => cfg_max_frame,
- CFG_ALLOW_RX_IN => cfg_allow_rx,
- CFG_SOFT_RESET_IN => cfg_soft_rst,
- CFG_SUBEVENT_ID_IN => cfg_subevent_id,
- CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
- CFG_QUEUE_DEC_IN => cfg_queue_dec,
- CFG_READOUT_CTR_IN => cfg_readout_ctr,
- CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
- CFG_MAX_SUB_IN => cfg_max_sub,
- CFG_MAX_QUEUE_IN => cfg_max_queue,
- CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
- CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
- CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
- CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
- CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ end generate NO_LINK1_GEN;
+
+ -- sfp5
+ GEN_LINK_0 : if (LINKS_ACTIVE(0) = '1') generate
+ gbe_inst0 : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => 1,
+ INCLUDE_READOUT => LINK_HAS_READOUT(0),
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL(0),
+ INCLUDE_DHCP => LINK_HAS_DHCP(0),
+ INCLUDE_ARP => LINK_HAS_ARP(0),
+ INCLUDE_PING => LINK_HAS_PING(0),
+ INCLUDE_FWD => LINK_HAS_FWD(0),
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => clk_125_rx_from_pcs(0),
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_0,
+ DHCP_DONE_OUT => dhcp_done(0),
+ MY_IP_OUT => my_ip(31 downto 0),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot(0),
+ MAC_READY_CONF_IN => mac_ready_conf(0),
+ MAC_RECONF_OUT => mac_reconf(0),
+ MAC_AN_READY_IN => mac_an_ready(0),
+ MAC_FIFOAVAIL_OUT => mac_fifoavail(0),
+ MAC_FIFOEOF_OUT => mac_fifoeof(0),
+ MAC_FIFOEMPTY_OUT => mac_fifoempty(0),
+ MAC_RX_FIFOFULL_OUT => mac_rx_fifofull(0),
+ MAC_TX_DATA_OUT => mac_tx_data(1 * 8 - 1 downto 0 * 8),
+ MAC_TX_READ_IN => mac_tx_read(0),
+ MAC_TX_DISCRFRM_IN => mac_tx_discrfrm(0),
+ MAC_TX_STAT_EN_IN => mac_tx_stat_en(0),
+ MAC_TX_STATS_IN => mac_tx_stats(1 * 31 - 1 downto 0 * 31),
+ MAC_TX_DONE_IN => mac_tx_done(0),
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err(0),
+ MAC_RX_STATS_IN => mac_rx_stats(1 * 32 - 1 downto 0 * 32),
+ MAC_RX_DATA_IN => mac_rx_data(1 * 8 - 1 downto 0 * 8),
+ MAC_RX_WRITE_IN => mac_rx_write(0),
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en(0),
+ MAC_RX_EOF_IN => mac_rx_eof(0),
+ MAC_RX_ERROR_IN => mac_rx_err(0),
+ CTS_NUMBER_IN => mlt_cts_number(1 * 16 - 1 downto 0 * 16),
+ CTS_CODE_IN => mlt_cts_code(1 * 8 - 1 downto 0 * 8),
+ CTS_INFORMATION_IN => mlt_cts_information(1 * 8 - 1 downto 0 * 8),
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type(1 * 4 - 1 downto 0 * 4),
+ CTS_START_READOUT_IN => mlt_cts_start_readout(0),
+ CTS_DATA_OUT => mlt_cts_data(1 * 32 - 1 downto 0 * 32),
+ CTS_DATAREADY_OUT => mlt_cts_dataready(0),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
+ CTS_READ_IN => mlt_cts_read(0),
+ CTS_LENGTH_OUT => mlt_cts_length(1 * 16 - 1 downto 0 * 16),
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern(1 * 32 - 1 downto 0 * 32),
+ FEE_DATA_IN => mlt_fee_data(1 * 16 - 1 downto 0 * 16),
+ FEE_DATAREADY_IN => mlt_fee_dataready(0),
+ FEE_READ_OUT => mlt_fee_read(0),
+ FEE_STATUS_BITS_IN => mlt_fee_status(1 * 32 - 1 downto 0 * 32),
+ FEE_BUSY_IN => mlt_fee_busy(0),
+ GSC_CLK_IN => mlt_gsc_clk(0),
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready(0),
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data(1 * 16 - 1 downto 0 * 16),
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet(1 * 3 - 1 downto 0 * 3),
+ GSC_INIT_READ_IN => mlt_gsc_init_read(0),
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready(0),
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data(1 * 16 - 1 downto 0 * 16),
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet(1 * 3 - 1 downto 0 * 3),
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read(0),
+ GSC_BUSY_IN => mlt_gsc_busy(0),
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip0.nack,
+ SLV_ACK_OUT => busip0.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip0.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
FWD_DST_MAC_IN => FWD_DST_MAC_IN(1 * 48 - 1 downto 0 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(1 * 32 - 1 downto 0 * 32),
FWD_READY_OUT => FWD_READY_OUT(0),
FWD_FULL_OUT => FWD_FULL_OUT(0),
- MONITOR_RX_FRAMES_OUT => monitor_rx_frames(1 * 32 - 1 downto 0 * 32),
- MONITOR_RX_BYTES_OUT => monitor_rx_bytes(1 * 32 - 1 downto 0 * 32),
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames(1 * 32 - 1 downto 0 * 32),
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes(1 * 32 - 1 downto 0 * 32),
- MONITOR_TX_PACKETS_OUT => monitor_tx_packets(1 * 32 - 1 downto 0 * 32),
- MONITOR_DROPPED_OUT => monitor_dropped(1 * 32 - 1 downto 0 * 32),
- MONITOR_GEN_DBG_OUT => open,
- MAKE_RESET_OUT => make_reset0
- );
- end generate GEN_LINK_0;
-
- NO_LINK0_GEN : if (LINKS_ACTIVE(0) = '0') generate
- make_reset0 <= '0';
- busip0.data <= (others => '0');
- busip0.ack <= '0';
- busip0.nack <= '0';
- monitor_rx_frames(1 * 32 - 1 downto 0 * 32) <= (others => '0');
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames(1 * 32 - 1 downto 0 * 32),
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes(1 * 32 - 1 downto 0 * 32),
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames(1 * 32 - 1 downto 0 * 32),
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes(1 * 32 - 1 downto 0 * 32),
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets(1 * 32 - 1 downto 0 * 32),
+ MONITOR_DROPPED_OUT => monitor_dropped(1 * 32 - 1 downto 0 * 32),
+ MONITOR_GEN_DBG_OUT => open,
+ MAKE_RESET_OUT => make_reset0
+ );
+ end generate GEN_LINK_0;
+
+ NO_LINK0_GEN : if (LINKS_ACTIVE(0) = '0') generate
+ make_reset0 <= '0';
+ busip0.data <= (others => '0');
+ busip0.ack <= '0';
+ busip0.nack <= '0';
+ monitor_rx_frames(1 * 32 - 1 downto 0 * 32) <= (others => '0');
monitor_rx_bytes(1 * 32 - 1 downto 0 * 32) <= (others => '0');
monitor_tx_frames(1 * 32 - 1 downto 0 * 32) <= (others => '0');
monitor_tx_bytes(1 * 32 - 1 downto 0 * 32) <= (others => '0');
mlt_cts_readout_finished(0) <= '0';
mlt_cts_length(1 * 16 - 1 downto 0 * 16) <= (others => '0');
mlt_cts_error_pattern(1 * 32 - 1 downto 0 * 32) <= (others => '0');
- end generate NO_LINK0_GEN;
-
- BUS_IP_TX.ack <= busip0.ack or busip1.ack or busip2.ack or busip3.ack when rising_edge(CLK_SYS_IN);
- BUS_IP_TX.nack <= busip0.nack or busip1.nack or busip2.nack or busip3.nack when rising_edge(CLK_SYS_IN);
- BUS_IP_TX.data <= busip0.data or busip1.data or busip2.data or busip3.data when rising_edge(CLK_SYS_IN);
-
- real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
- ipu_mult : entity work.gbe_ipu_multiplexer
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- LINK_HAS_READOUT => LINK_HAS_READOUT,
- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
- )
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- RESET => RESET,
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- MLT_CTS_NUMBER_OUT => mlt_cts_number,
- MLT_CTS_CODE_OUT => mlt_cts_code,
- MLT_CTS_INFORMATION_OUT => mlt_cts_information,
- MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
- MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
- MLT_CTS_DATA_IN => mlt_cts_data,
- MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
- MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
- MLT_CTS_READ_OUT => mlt_cts_read,
- MLT_CTS_LENGTH_IN => mlt_cts_length,
- MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
- MLT_FEE_DATA_OUT => mlt_fee_data,
- MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
- MLT_FEE_READ_IN => mlt_fee_read,
- MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
- MLT_FEE_BUSY_OUT => mlt_fee_busy,
- DEBUG_OUT => open
- );
- end generate real_ipu_gen;
-
- dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
- ipu_mult : entity work.gbe_ipu_multiplexer
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_DEBUG => INCLUDE_DEBUG,
- LINK_HAS_READOUT => LINK_HAS_READOUT,
- NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
- )
- port map(
- CLK_SYS_IN => CLK_SYS_IN,
- RESET => RESET,
- CTS_NUMBER_IN => local_cts_number,
- CTS_CODE_IN => local_cts_code,
- CTS_INFORMATION_IN => local_cts_information,
- CTS_READOUT_TYPE_IN => local_cts_readout_type,
- CTS_START_READOUT_IN => local_cts_start_readout,
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => local_cts_readout_finished,
- CTS_READ_IN => '1',
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => local_cts_status_bits,
- FEE_DATA_IN => local_fee_data,
- FEE_DATAREADY_IN => local_fee_dataready,
- FEE_READ_OUT => local_fee_read,
- FEE_STATUS_BITS_IN => local_fee_status_bits,
- FEE_BUSY_IN => local_fee_busy,
- MLT_CTS_NUMBER_OUT => mlt_cts_number,
- MLT_CTS_CODE_OUT => mlt_cts_code,
- MLT_CTS_INFORMATION_OUT => mlt_cts_information,
- MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
- MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
- MLT_CTS_DATA_IN => mlt_cts_data,
- MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
- MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
- MLT_CTS_READ_OUT => mlt_cts_read,
- MLT_CTS_LENGTH_IN => mlt_cts_length,
- MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
- MLT_FEE_DATA_OUT => mlt_fee_data,
- MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
- MLT_FEE_READ_IN => mlt_fee_read,
- MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
- MLT_FEE_BUSY_OUT => mlt_fee_busy,
- DEBUG_OUT => open
- );
-
- dummy : entity work.gbe_ipu_dummy
- generic map(
- DO_SIMULATION => DO_SIMULATION,
- FIXED_SIZE_MODE => FIXED_SIZE_MODE,
- INCREMENTAL_MODE => INCREMENTAL_MODE,
- FIXED_SIZE => FIXED_SIZE,
- UP_DOWN_MODE => UP_DOWN_MODE,
- UP_DOWN_LIMIT => UP_DOWN_LIMIT,
- FIXED_DELAY_MODE => FIXED_DELAY_MODE,
- FIXED_DELAY => FIXED_DELAY
- )
- port map(
- clk => CLK_SYS_IN,
- rst => RESET,
- GBE_READY_IN => all_links_ready,
- CFG_EVENT_SIZE_IN => dummy_event,
- CFG_TRIGGERED_MODE_IN => '0',
- TRIGGER_IN => TRIGGER_IN,
- CTS_NUMBER_OUT => local_cts_number,
- CTS_CODE_OUT => local_cts_code,
- CTS_INFORMATION_OUT => local_cts_information,
- CTS_READOUT_TYPE_OUT => local_cts_readout_type,
- CTS_START_READOUT_OUT => local_cts_start_readout,
- CTS_DATA_IN => (others => '0'),
- CTS_DATAREADY_IN => '0',
- CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
- CTS_READ_OUT => open,
- CTS_LENGTH_IN => (others => '0'),
- CTS_ERROR_PATTERN_IN => local_cts_status_bits,
- -- Data payload interface
- FEE_DATA_OUT => local_fee_data,
- FEE_DATAREADY_OUT => local_fee_dataready,
- FEE_READ_IN => local_fee_read,
- FEE_STATUS_BITS_OUT => local_fee_status_bits,
- FEE_BUSY_OUT => local_fee_busy
- );
-
- -- handler for triggers
- DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
- port map(
- CLK_IPU => CLK_SYS_IN,
- CLK_GBE => CLK_125_IN,
- RESET => RESET,
- --Event information coming from CTS
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- slow control interface
- START_CONFIG_OUT => open,
- BANK_SELECT_OUT => open,
- CONFIG_DONE_IN => '1',
- DATA_GBE_ENABLE_IN => '1',
- DATA_IPU_ENABLE_IN => '1',
- MULT_EVT_ENABLE_IN => '1',
- MAX_SUBEVENT_SIZE_IN => (others => '0'),
- MAX_QUEUE_SIZE_IN => (others => '0'),
- MAX_SUBS_IN_QUEUE_IN => (others => '0'),
- MAX_SINGLE_SUB_SIZE_IN => (others => '0'),
- READOUT_CTR_IN => (others => '0'),
- READOUT_CTR_VALID_IN => '0',
- CFG_AUTO_THROTTLE_IN => '0',
- CFG_THROTTLE_PAUSE_IN => (others => '0'),
- -- PacketConstructor interface
- PC_WR_EN_OUT => open,
- PC_DATA_OUT => open,
- PC_READY_IN => '1',
- PC_SOS_OUT => open,
- PC_EOS_OUT => open,
- PC_EOQ_OUT => open,
- PC_SUB_SIZE_OUT => open,
- PC_TRIG_NR_OUT => open,
- PC_TRIGGER_TYPE_OUT => open,
- MONITOR_OUT => open,
- DEBUG_OUT => open
- );
- end generate dummy_ipu_gen;
-
- setup_imp_gen : if (DO_SIMULATION = 0) generate
- SETUP : gbe_setup
- port map(
- CLK => CLK_SYS_IN,
- RESET => RESET,
-
- -- interface to regio bus
- BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
- BUS_DATA_IN => BUS_REG_RX.data,
- BUS_DATA_OUT => BUS_REG_TX.data,
- BUS_WRITE_EN_IN => BUS_REG_RX.write,
- BUS_READ_EN_IN => BUS_REG_RX.read,
- BUS_ACK_OUT => BUS_REG_TX.ack,
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
- GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
- GBE_QUEUE_DEC_OUT => cfg_queue_dec,
- GBE_MAX_FRAME_OUT => cfg_max_frame,
- GBE_USE_GBE_OUT => cfg_gbe_enable,
- GBE_USE_TRBNET_OUT => cfg_ipu_enable,
- GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
- GBE_READOUT_CTR_OUT => cfg_readout_ctr,
- GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
- GBE_ALLOW_RX_OUT => cfg_allow_rx,
- GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
- GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
- GBE_SOFT_RESET_OUT => cfg_soft_rst,
- GBE_MAX_REPLY_OUT => cfg_max_reply,
- GBE_MAX_SUB_OUT => cfg_max_sub,
- GBE_MAX_QUEUE_OUT => cfg_max_queue,
- GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
- GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
- GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
- GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
- MONITOR_RX_BYTES_IN => sum_rx_bytes,
- MONITOR_RX_FRAMES_IN => sum_rx_frames,
- MONITOR_TX_BYTES_IN => sum_tx_bytes,
- MONITOR_TX_FRAMES_IN => sum_tx_frames,
- MONITOR_TX_PACKETS_IN => sum_tx_packets,
- MONITOR_DROPPED_IN => sum_dropped,
- MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent,
- MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg, --dbg_select_gen,
+ end generate NO_LINK0_GEN;
+
+ BUS_IP_TX.ack <= busip0.ack or busip1.ack or busip2.ack or busip3.ack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.nack <= busip0.nack or busip1.nack or busip2.nack or busip3.nack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.data <= busip0.data or busip1.data or busip2.data or busip3.data when rising_edge(CLK_SYS_IN);
+
+ real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => LINK_HAS_READOUT,
+ NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+ end generate real_ipu_gen;
+
+ dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => LINK_HAS_READOUT,
+ NUMBER_OF_GBE_LINKS => NUMBER_OF_GBE_LINKS
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => local_cts_number,
+ CTS_CODE_IN => local_cts_code,
+ CTS_INFORMATION_IN => local_cts_information,
+ CTS_READOUT_TYPE_IN => local_cts_readout_type,
+ CTS_START_READOUT_IN => local_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => local_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => local_cts_status_bits,
+ FEE_DATA_IN => local_fee_data,
+ FEE_DATAREADY_IN => local_fee_dataready,
+ FEE_READ_OUT => local_fee_read,
+ FEE_STATUS_BITS_IN => local_fee_status_bits,
+ FEE_BUSY_IN => local_fee_busy,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+
+ dummy : entity work.gbe_ipu_dummy
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ FIXED_DELAY => FIXED_DELAY
+ )
+ port map(
+ clk => CLK_SYS_IN,
+ rst => RESET,
+ GBE_READY_IN => all_links_ready,
+ CFG_EVENT_SIZE_IN => dummy_event,
+ CFG_TRIGGERED_MODE_IN => '0',
+ TRIGGER_IN => TRIGGER_IN,
+ CTS_NUMBER_OUT => local_cts_number,
+ CTS_CODE_OUT => local_cts_code,
+ CTS_INFORMATION_OUT => local_cts_information,
+ CTS_READOUT_TYPE_OUT => local_cts_readout_type,
+ CTS_START_READOUT_OUT => local_cts_start_readout,
+ CTS_DATA_IN => (others => '0'),
+ CTS_DATAREADY_IN => '0',
+ CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
+ CTS_READ_OUT => open,
+ CTS_LENGTH_IN => (others => '0'),
+ CTS_ERROR_PATTERN_IN => local_cts_status_bits,
+ -- Data payload interface
+ FEE_DATA_OUT => local_fee_data,
+ FEE_DATAREADY_OUT => local_fee_dataready,
+ FEE_READ_IN => local_fee_read,
+ FEE_STATUS_BITS_OUT => local_fee_status_bits,
+ FEE_BUSY_OUT => local_fee_busy
+ );
+
+ -- handler for triggers
+ DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
+ port map(
+ CLK_IPU => CLK_SYS_IN,
+ CLK_GBE => CLK_125_IN,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => open,
+ BANK_SELECT_OUT => open,
+ CONFIG_DONE_IN => '1',
+ DATA_GBE_ENABLE_IN => '1',
+ DATA_IPU_ENABLE_IN => '1',
+ MULT_EVT_ENABLE_IN => '1',
+ MAX_SUBEVENT_SIZE_IN => (others => '0'),
+ MAX_QUEUE_SIZE_IN => (others => '0'),
+ MAX_SUBS_IN_QUEUE_IN => (others => '0'),
+ MAX_SINGLE_SUB_SIZE_IN => (others => '0'),
+ READOUT_CTR_IN => (others => '0'),
+ READOUT_CTR_VALID_IN => '0',
+ CFG_AUTO_THROTTLE_IN => '0',
+ CFG_THROTTLE_PAUSE_IN => (others => '0'),
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => open,
+ PC_DATA_OUT => open,
+ PC_READY_IN => '1',
+ PC_SOS_OUT => open,
+ PC_EOS_OUT => open,
+ PC_EOQ_OUT => open,
+ PC_SUB_SIZE_OUT => open,
+ PC_TRIG_NR_OUT => open,
+ PC_TRIGGER_TYPE_OUT => open,
+ MONITOR_OUT => open,
+ DEBUG_OUT => open
+ );
+ end generate dummy_ipu_gen;
+
+ setup_imp_gen : if (DO_SIMULATION = 0) generate
+ SETUP : gbe_setup
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
+
+ -- interface to regio bus
+ BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
+ BUS_DATA_IN => BUS_REG_RX.data,
+ BUS_DATA_OUT => BUS_REG_TX.data,
+ BUS_WRITE_EN_IN => BUS_REG_RX.write,
+ BUS_READ_EN_IN => BUS_REG_RX.read,
+ BUS_ACK_OUT => BUS_REG_TX.ack,
+
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
+ GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
+ GBE_QUEUE_DEC_OUT => cfg_queue_dec,
+ GBE_MAX_FRAME_OUT => cfg_max_frame,
+ GBE_USE_GBE_OUT => cfg_gbe_enable,
+ GBE_USE_TRBNET_OUT => cfg_ipu_enable,
+ GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
+ GBE_READOUT_CTR_OUT => cfg_readout_ctr,
+ GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
+ GBE_ALLOW_RX_OUT => cfg_allow_rx,
+ GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
+ GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
+ GBE_SOFT_RESET_OUT => cfg_soft_rst,
+ GBE_MAX_REPLY_OUT => cfg_max_reply,
+ GBE_MAX_SUB_OUT => cfg_max_sub,
+ GBE_MAX_QUEUE_OUT => cfg_max_queue,
+ GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
+ GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
+ GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
+ GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
+ MONITOR_RX_BYTES_IN => sum_rx_bytes,
+ MONITOR_RX_FRAMES_IN => sum_rx_frames,
+ MONITOR_TX_BYTES_IN => sum_tx_bytes,
+ MONITOR_TX_FRAMES_IN => sum_tx_frames,
+ MONITOR_TX_PACKETS_IN => sum_tx_packets,
+ MONITOR_DROPPED_IN => sum_dropped,
+ MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec,
+ MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes,
+ MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes,
+ MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent,
+ MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in,
+ MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out,
+ MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg, --dbg_select_gen,
MONITOR_IP_IN => my_ip,
- DUMMY_EVENT_SIZE_OUT => dummy_event,
- DUMMY_TRIGGERED_MODE_OUT => dummy_mode,
- DATA_HIST_IN => (others => (others => '0')), --dbg_hist,
- SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2
- );
- end generate;
-
- setup_sim_gen : if (DO_SIMULATION = 1) generate
- cfg_subevent_id <= x"12345678";
- cfg_subevent_dec <= x"00010002";
- cfg_queue_dec <= x"00030004";
- cfg_max_frame <= x"0578";
- cfg_gbe_enable <= '1';
- cfg_ipu_enable <= '1';
- cfg_mult_enable <= '0';
- cfg_readout_ctr <= x"000000";
- cfg_readout_ctr_valid <= '0';
- cfg_allow_rx <= '1';
- cfg_additional_hdr <= '0';
- cfg_insert_ttype <= '0';
- cfg_soft_rst <= '0';
- cfg_max_reply <= x"0000fff0";
- cfg_max_sub <= x"fff0";
- cfg_max_queue <= x"fff0";
- cfg_max_subs_in_queue <= x"0001";
- cfg_max_single_sub <= x"fff0";
- cfg_throttle_pause <= x"0000";
-
- end generate;
-
- NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
- GSC_INIT_DATAREADY_OUT <= '0';
- GSC_INIT_DATA_OUT <= (others => '0');
- GSC_INIT_PACKET_NUM_OUT <= (others => '0');
- GSC_REPLY_READ_OUT <= '1';
- mlt_gsc_clk <= (others => '0');
- mlt_gsc_init_read <= (others => '0');
- mlt_gsc_reply_dataready <= (others => '0');
- mlt_gsc_reply_data <= (others => '0');
- mlt_gsc_reply_packet <= (others => '0');
- mlt_gsc_busy <= (others => '0');
- end generate NOSCTRL_MAP_GEN;
-
- SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate
- SCTRL_LOOP_GEN : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
- ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '1') generate
- mlt_gsc_clk(i) <= GSC_CLK_IN;
- GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready(i);
- GSC_INIT_DATA_OUT <= mlt_gsc_init_data((i + 1) * 16 - 1 downto i * 16);
- GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet((i + 1) * 3 - 1 downto i * 3);
- mlt_gsc_init_read(i) <= GSC_INIT_READ_IN;
- mlt_gsc_reply_dataready(i) <= GSC_REPLY_DATAREADY_IN;
- mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= GSC_REPLY_DATA_IN;
- mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= GSC_REPLY_PACKET_NUM_IN;
- GSC_REPLY_READ_OUT <= mlt_gsc_reply_read(i);
- mlt_gsc_busy(i) <= GSC_BUSY_IN;
- end generate ACTIVE_MAP_GEN;
-
- INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '0') generate
- mlt_gsc_clk(i) <= '0';
- mlt_gsc_init_read(i) <= '0';
- mlt_gsc_reply_dataready(i) <= '0';
- mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= (others => '0');
- mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= (others => '0');
- mlt_gsc_busy(i) <= '0';
- end generate INACTIVE_MAP_GEN;
- end generate SCTRL_LOOP_GEN;
- end generate SCTRL_MAP_GEN;
-
- sum_rx_bytes <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32);
- sum_rx_frames <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32);
- sum_tx_bytes <= monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_tx_bytes(1 * 32 - 1 downto 0 * 32);
- sum_tx_frames <= monitor_tx_frames(4 * 32 - 1 downto 3 * 32) + monitor_tx_frames(3 * 32 - 1 downto 2 * 32) + monitor_tx_frames(2 * 32 - 1 downto 1 * 32) + monitor_tx_frames(1 * 32 - 1 downto 0 * 32);
- sum_tx_packets <= monitor_tx_packets(4 * 32 - 1 downto 3 * 32) + monitor_tx_packets(3 * 32 - 1 downto 2 * 32) + monitor_tx_packets(2 * 32 - 1 downto 1 * 32) + monitor_tx_packets(1 * 32 - 1 downto 0 * 32);
- sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32);
-
- include_debug_gen : if (INCLUDE_DEBUG = 1) generate
- DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64);
- DEBUG_OUT(127 downto 65) <= (others => '0');
- end generate;
-
- testbench_sim : if DO_SIMULATION = 1 generate
- clk_125_rx_from_pcs(0) <= CLK_125_IN;
- clk_125_rx_from_pcs(1) <= CLK_125_IN;
- clk_125_rx_from_pcs(2) <= CLK_125_IN;
- clk_125_rx_from_pcs(3) <= CLK_125_IN;
-
- done_generate : for i in 0 to 3 generate
- process
- begin
- mac_tx_done(i) <= '0';
- wait until rising_edge(mac_fifoeof(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- wait until rising_edge(clk_125_rx_from_pcs(i));
- mac_tx_done(i) <= '1';
- wait until rising_edge(clk_125_rx_from_pcs(i));
- end process;
- end generate done_generate;
-
- process
- begin
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_tx_read(0) <= mac_fifoavail(0);
- mac_tx_read(1) <= mac_fifoavail(1);
- mac_tx_read(2) <= mac_fifoavail(2);
- mac_tx_read(3) <= mac_fifoavail(3);
- end process;
-
- mac_rx_eof(1) <= mac_rx_eof(0);
- mac_rx_eof(2) <= mac_rx_eof(0);
- mac_rx_eof(3) <= mac_rx_eof(0);
- mac_rx_write(1) <= mac_rx_write(0);
- mac_rx_write(2) <= mac_rx_write(0);
- mac_rx_write(3) <= mac_rx_write(0);
- mac_rx_data(2 * 8 - 1 downto 1 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
- mac_rx_data(3 * 8 - 1 downto 2 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
- mac_rx_data(4 * 8 - 1 downto 3 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
-
- testbench_proc : process
- begin
-
- --trigger <= '0';
- --gbe_ready <= '0';
- mac_rx_write(0) <= '0';
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- mac_rx_eof(0) <= '0';
-
- wait for 5 us;
-
- -- FIRST FRAME UDP - DHCP Offer
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <= '1';
- -- dest mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- src mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- frame type
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- ip headers
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- -- udp headers
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
- -- dhcp data
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; --transcation id
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; --transcation id
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa"; --transcation id
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce"; --transcation id
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- end loop;
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_eof(0) <= '1';
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <= '0';
- mac_rx_eof(0) <= '0';
-
- wait for 6 us;
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <= '1';
- -- dest mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- src mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- frame type
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- ip headers
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- -- udp headers
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
- -- dhcp data
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
-
- for i in 0 to 219 loop
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- end loop;
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"05";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_eof(0) <= '1';
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <= '0';
- mac_rx_eof(0) <= '0';
-
- wait for 5 us;
-
- wait for 2 us;
-
- --gbe_ready <= '1';
-
- wait for 1 us;
-
- --trigger <= '1';
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <= '1';
- -- dest mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- src mac
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- frame type
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- ip headers
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- -- ping headers
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"47";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"d3";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"0d";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"3c";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- -- ping data
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"8c";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"da";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e7";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"4d";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"36";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c4";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"0d";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"03";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"04";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"05";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"07";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
-
- -- ping data
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_eof(0) <= '1';
- mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
-
- wait until rising_edge(clk_125_rx_from_pcs(0));
- mac_rx_write(0) <='0';
- mac_rx_eof(0) <= '0';
-
-
- wait for 10 us;
+ DUMMY_EVENT_SIZE_OUT => dummy_event,
+ DUMMY_TRIGGERED_MODE_OUT => dummy_mode,
+ DATA_HIST_IN => (others => (others => '0')), --dbg_hist,
+ SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2
+ );
+ end generate;
+
+ setup_sim_gen : if (DO_SIMULATION = 1) generate
+ cfg_subevent_id <= x"12345678";
+ cfg_subevent_dec <= x"00010002";
+ cfg_queue_dec <= x"00030004";
+ cfg_max_frame <= x"0578";
+ cfg_gbe_enable <= '1';
+ cfg_ipu_enable <= '1';
+ cfg_mult_enable <= '0';
+ cfg_readout_ctr <= x"000000";
+ cfg_readout_ctr_valid <= '0';
+ cfg_allow_rx <= '1';
+ cfg_additional_hdr <= '0';
+ cfg_insert_ttype <= '0';
+ cfg_soft_rst <= '0';
+ cfg_max_reply <= x"0000fff0";
+ cfg_max_sub <= x"fff0";
+ cfg_max_queue <= x"fff0";
+ cfg_max_subs_in_queue <= x"0001";
+ cfg_max_single_sub <= x"fff0";
+ cfg_throttle_pause <= x"0000";
+
+ end generate;
+
+ NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
+ GSC_INIT_DATAREADY_OUT <= '0';
+ GSC_INIT_DATA_OUT <= (others => '0');
+ GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+ GSC_REPLY_READ_OUT <= '1';
+ mlt_gsc_clk <= (others => '0');
+ mlt_gsc_init_read <= (others => '0');
+ mlt_gsc_reply_dataready <= (others => '0');
+ mlt_gsc_reply_data <= (others => '0');
+ mlt_gsc_reply_packet <= (others => '0');
+ mlt_gsc_busy <= (others => '0');
+ end generate NOSCTRL_MAP_GEN;
+
+ SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= "0000") generate
+ SCTRL_LOOP_GEN : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate
+ ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '1') generate
+ mlt_gsc_clk(i) <= GSC_CLK_IN;
+ GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready(i);
+ GSC_INIT_DATA_OUT <= mlt_gsc_init_data((i + 1) * 16 - 1 downto i * 16);
+ GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet((i + 1) * 3 - 1 downto i * 3);
+ mlt_gsc_init_read(i) <= GSC_INIT_READ_IN;
+ mlt_gsc_reply_dataready(i) <= GSC_REPLY_DATAREADY_IN;
+ mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= GSC_REPLY_DATA_IN;
+ mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= GSC_REPLY_PACKET_NUM_IN;
+ GSC_REPLY_READ_OUT <= mlt_gsc_reply_read(i);
+ mlt_gsc_busy(i) <= GSC_BUSY_IN;
+ end generate ACTIVE_MAP_GEN;
+
+ INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL(i) = '0') generate
+ mlt_gsc_clk(i) <= '0';
+ mlt_gsc_init_read(i) <= '0';
+ mlt_gsc_reply_dataready(i) <= '0';
+ mlt_gsc_reply_data((i + 1) * 16 - 1 downto i * 16) <= (others => '0');
+ mlt_gsc_reply_packet((i + 1) * 3 - 1 downto i * 3) <= (others => '0');
+ mlt_gsc_busy(i) <= '0';
+ end generate INACTIVE_MAP_GEN;
+ end generate SCTRL_LOOP_GEN;
+ end generate SCTRL_MAP_GEN;
+
+ sum_rx_bytes <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32);
+ sum_rx_frames <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32);
+ sum_tx_bytes <= monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_tx_bytes(1 * 32 - 1 downto 0 * 32);
+ sum_tx_frames <= monitor_tx_frames(4 * 32 - 1 downto 3 * 32) + monitor_tx_frames(3 * 32 - 1 downto 2 * 32) + monitor_tx_frames(2 * 32 - 1 downto 1 * 32) + monitor_tx_frames(1 * 32 - 1 downto 0 * 32);
+ sum_tx_packets <= monitor_tx_packets(4 * 32 - 1 downto 3 * 32) + monitor_tx_packets(3 * 32 - 1 downto 2 * 32) + monitor_tx_packets(2 * 32 - 1 downto 1 * 32) + monitor_tx_packets(1 * 32 - 1 downto 0 * 32);
+ sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32);
+
+ include_debug_gen : if (INCLUDE_DEBUG = 1) generate
+ DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64);
+ DEBUG_OUT(127 downto 65) <= (others => '0');
+ end generate;
+
+ testbench_sim : if DO_SIMULATION = 1 generate
+ clk_125_rx_from_pcs(0) <= CLK_125_IN;
+ clk_125_rx_from_pcs(1) <= CLK_125_IN;
+ clk_125_rx_from_pcs(2) <= CLK_125_IN;
+ clk_125_rx_from_pcs(3) <= CLK_125_IN;
+
+ done_generate : for i in 0 to 3 generate
+ process
+ begin
+ mac_tx_done(i) <= '0';
+ wait until rising_edge(mac_fifoeof(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ mac_tx_done(i) <= '1';
+ wait until rising_edge(clk_125_rx_from_pcs(i));
+ end process;
+ end generate done_generate;
+
+ process
+ begin
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_tx_read(0) <= mac_fifoavail(0);
+ mac_tx_read(1) <= mac_fifoavail(1);
+ mac_tx_read(2) <= mac_fifoavail(2);
+ mac_tx_read(3) <= mac_fifoavail(3);
+ end process;
+
+ mac_rx_eof(1) <= mac_rx_eof(0);
+ mac_rx_eof(2) <= mac_rx_eof(0);
+ mac_rx_eof(3) <= mac_rx_eof(0);
+ mac_rx_write(1) <= mac_rx_write(0);
+ mac_rx_write(2) <= mac_rx_write(0);
+ mac_rx_write(3) <= mac_rx_write(0);
+ mac_rx_data(2 * 8 - 1 downto 1 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
+ mac_rx_data(3 * 8 - 1 downto 2 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
+ mac_rx_data(4 * 8 - 1 downto 3 * 8) <= mac_rx_data(1 * 8 - 1 downto 0 * 8);
+
+ testbench_proc : process
+ begin
+
+ --trigger <= '0';
+ --gbe_ready <= '0';
+ mac_rx_write(0) <= '0';
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ mac_rx_eof(0) <= '0';
+
+ wait for 5 us;
+
+ -- FIRST FRAME UDP - DHCP Offer
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '1';
+ -- dest mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- src mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- frame type
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- ip headers
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ -- udp headers
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ -- dhcp data
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; --transcation id
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff"; --transcation id
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa"; --transcation id
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce"; --transcation id
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
+
+ for i in 0 to 219 loop
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ end loop;
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_eof(0) <= '1';
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '0';
+ mac_rx_eof(0) <= '0';
+
+ wait for 6 us;
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '1';
+ -- dest mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- src mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- frame type
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- ip headers
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"11"; -- udp
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ -- udp headers
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"43";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"44";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"2c";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ -- dhcp data
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"fa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ce";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
+
+ for i in 0 to 219 loop
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ end loop;
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"35";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"05";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_eof(0) <= '1';
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '0';
+ mac_rx_eof(0) <= '0';
+
+ wait for 5 us;
+
+ wait for 2 us;
+
+ --gbe_ready <= '1';
+
+ wait for 1 us;
+
+ --trigger <= '1';
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <= '1';
+ -- dest mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- src mac
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"bb";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"dd";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ee";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- frame type
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- ip headers
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"45";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"10";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"5a";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"49";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"ff";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"cc";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"a8";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ -- ping headers
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"47";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"d3";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"0d";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"3c";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ -- ping data
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"8c";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"da";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e7";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"4d";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"36";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"c4";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"0d";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"00";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"02";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"03";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"04";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"05";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"06";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"07";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"08";
+
+ -- ping data
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"e0";
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"01";
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_eof(0) <= '1';
+ mac_rx_data(1 * 8 - 1 downto 0 * 8) <= x"aa";
+
+ wait until rising_edge(clk_125_rx_from_pcs(0));
+ mac_rx_write(0) <='0';
+ mac_rx_eof(0) <= '0';
+
+
+ wait for 10 us;
-- ETHERNET PAUSE FRAME
-- mac_rx_write(0) <='0';
-- mac_rx_eof(0) <= '0';
- wait;
+ wait;
- end process testbench_proc;
+ end process testbench_proc;
- end generate testbench_sim;
+ end generate testbench_sim;
end architecture RTL;
entity trb_net16_gbe_main_control is
- generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0;
-
- INCLUDE_READOUT : std_logic := '0';
- INCLUDE_SLOWCTRL : std_logic := '0';
- INCLUDE_DHCP : std_logic := '0';
- INCLUDE_ARP : std_logic := '0';
- INCLUDE_PING : std_logic := '0';
- INCLUDE_FWD : std_logic := '0';
-
- READOUT_BUFFER_SIZE : integer range 1 to 4;
- SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
- );
- port(
- CLK : in std_logic; -- system clock
- CLK_125 : in std_logic;
- RESET : in std_logic;
-
- MC_LINK_OK_OUT : out std_logic;
- MC_RESET_LINK_IN : in std_logic;
- MC_IDLE_TOO_LONG_OUT : out std_logic;
- MC_DHCP_DONE_OUT : out std_logic;
- MY_IP_OUT : out std_logic_vector(31 downto 0);
- MC_MY_MAC_IN : in std_logic_vector(47 downto 0);
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
- ISSUE_REBOOT_OUT : out std_logic;
- -- signals to/from receive controller
- RC_FRAME_WAITING_IN : in std_logic;
- RC_LOADING_DONE_OUT : out std_logic;
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- RC_RD_EN_OUT : out std_logic;
- RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- -- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_TRANSMIT_DONE_IN : in std_logic;
-
- -- signals to/from sgmii/gbe pcs_an_complete
- PCS_AN_COMPLETE_IN : in std_logic;
-
- -- signals to/from hub
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- RESET_TRBNET_IN : in std_logic;
- RESET_SCTRL_IN : in std_logic;
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
- CTS_CODE_IN : in std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
-
- CFG_ADDITIONAL_HDR_IN : in std_logic;
- CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
-
- CFG_AUTO_THROTTLE_IN : in std_logic;
- CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
-
- MAKE_RESET_OUT : out std_logic;
+ generic(
+ RX_PATH_ENABLE : integer range 0 to 1 := 1;
+ DO_SIMULATION : integer range 0 to 1 := 0;
+
+ INCLUDE_READOUT : std_logic := '0';
+ INCLUDE_SLOWCTRL : std_logic := '0';
+ INCLUDE_DHCP : std_logic := '0';
+ INCLUDE_ARP : std_logic := '0';
+ INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
+
+ READOUT_BUFFER_SIZE : integer range 1 to 4;
+ SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
+ );
+ port(
+ CLK : in std_logic; -- system clock
+ CLK_125 : in std_logic;
+ RESET : in std_logic;
+
+ MC_LINK_OK_OUT : out std_logic;
+ MC_RESET_LINK_IN : in std_logic;
+ MC_IDLE_TOO_LONG_OUT : out std_logic;
+ MC_DHCP_DONE_OUT : out std_logic;
+ MY_IP_OUT : out std_logic_vector(31 downto 0);
+ MC_MY_MAC_IN : in std_logic_vector(47 downto 0);
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+ -- signals to/from receive controller
+ RC_FRAME_WAITING_IN : in std_logic;
+ RC_LOADING_DONE_OUT : out std_logic;
+ RC_DATA_IN : in std_logic_vector(8 downto 0);
+ RC_RD_EN_OUT : out std_logic;
+ RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
+ RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+
+ RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ -- signals to/from transmit controller
+ TC_TRANSMIT_CTRL_OUT : out std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_RD_EN_IN : in std_logic;
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_TRANSMIT_DONE_IN : in std_logic;
+
+ -- signals to/from sgmii/gbe pcs_an_complete
+ PCS_AN_COMPLETE_IN : in std_logic;
+
+ -- signals to/from hub
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+
+ RESET_TRBNET_IN : in std_logic;
+ RESET_SCTRL_IN : in std_logic;
+ -- signal for data readout
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ -- ip configurator
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+
+ CFG_GBE_ENABLE_IN : in std_logic;
+ CFG_IPU_ENABLE_IN : in std_logic;
+ CFG_MULT_ENABLE_IN : in std_logic;
+ CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
+ CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
+ CFG_READOUT_CTR_VALID_IN : in std_logic;
+ CFG_INSERT_TTYPE_IN : in std_logic;
+ CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
+
+ CFG_ADDITIONAL_HDR_IN : in std_logic;
+ CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
+
+ CFG_AUTO_THROTTLE_IN : in std_logic;
+ CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+
+ MAKE_RESET_OUT : out std_logic;
-- Forwarder
- FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
- FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
- FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
- FWD_DATA_IN : in std_logic_vector(7 downto 0);
- FWD_DATA_VALID_IN : in std_logic;
- FWD_SOP_IN : in std_logic;
- FWD_EOP_IN : in std_logic;
- FWD_READY_OUT : out std_logic;
- FWD_FULL_OUT : out std_logic;
-
- -- signal to/from Host interface of TriSpeed MAC
- TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
- TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
- TSM_HCS_N_OUT : out std_logic;
- TSM_HWRITE_N_OUT : out std_logic;
- TSM_HREAD_N_OUT : out std_logic;
- TSM_HREADY_N_IN : in std_logic;
- TSM_HDATA_EN_N_IN : in std_logic;
- TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
- TSM_RX_STAT_EN_IN : in std_logic;
-
- MAC_READY_CONF_IN : in std_logic;
- MAC_RECONF_OUT : out std_logic;
-
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
-
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array;
-
- DEBUG_OUT : out std_logic_vector(63 downto 0)
- );
+ FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
+ FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
+ FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
+ FWD_DATA_IN : in std_logic_vector(7 downto 0);
+ FWD_DATA_VALID_IN : in std_logic;
+ FWD_SOP_IN : in std_logic;
+ FWD_EOP_IN : in std_logic;
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
+ TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
+ TSM_HCS_N_OUT : out std_logic;
+ TSM_HWRITE_N_OUT : out std_logic;
+ TSM_HREAD_N_OUT : out std_logic;
+ TSM_HREADY_N_IN : in std_logic;
+ TSM_HDATA_EN_N_IN : in std_logic;
+ TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
+ TSM_RX_STAT_EN_IN : in std_logic;
+
+ MAC_READY_CONF_IN : in std_logic;
+ MAC_RECONF_OUT : out std_logic;
+
+ MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+
+ DATA_HIST_OUT : out hist_array;
+ SCTRL_HIST_OUT : out hist_array;
+
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
end trb_net16_gbe_main_control;
architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is
- --attribute HGROUP : string;
- --attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
+ --attribute HGROUP : string;
+ --attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
- attribute syn_encoding : string;
+ attribute syn_encoding : string;
- signal tsm_ready : std_logic;
- signal tsm_reconf : std_logic;
- signal tsm_haddr : std_logic_vector(7 downto 0);
- signal tsm_hdata : std_logic_vector(7 downto 0);
- signal tsm_hcs_n : std_logic;
- signal tsm_hwrite_n : std_logic;
- signal tsm_hread_n : std_logic;
+ signal tsm_ready : std_logic;
+ signal tsm_reconf : std_logic;
+ signal tsm_haddr : std_logic_vector(7 downto 0);
+ signal tsm_hdata : std_logic_vector(7 downto 0);
+ signal tsm_hcs_n : std_logic;
+ signal tsm_hwrite_n : std_logic;
+ signal tsm_hread_n : std_logic;
- type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
- signal link_current_state, link_next_state : link_states;
- attribute syn_encoding of link_current_state : signal is "onehot";
+ type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
+ signal link_current_state, link_next_state : link_states;
+ attribute syn_encoding of link_current_state : signal is "onehot";
- signal link_down_ctr : std_logic_vector(15 downto 0);
- signal link_down_ctr_lock : std_logic;
- signal link_ok : std_logic;
- signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
+ signal link_down_ctr : std_logic_vector(15 downto 0);
+ signal link_down_ctr_lock : std_logic;
+ signal link_ok : std_logic;
+ signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
- signal mac_control_debug : std_logic_vector(63 downto 0);
+ signal mac_control_debug : std_logic_vector(63 downto 0);
- type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP);
- signal flow_current_state, flow_next_state : flow_states;
- attribute syn_encoding of flow_current_state : signal is "onehot";
+ type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP);
+ signal flow_current_state, flow_next_state : flow_states;
+ attribute syn_encoding of flow_current_state : signal is "onehot";
- signal state : std_logic_vector(3 downto 0);
- signal link_state : std_logic_vector(3 downto 0);
- signal redirect_state : std_logic_vector(3 downto 0);
+ signal state : std_logic_vector(3 downto 0);
+ signal link_state : std_logic_vector(3 downto 0);
+ signal redirect_state : std_logic_vector(3 downto 0);
- signal ps_wr_en : std_logic;
- signal ps_response_ready : std_logic;
- signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal rc_rd_en : std_logic;
- signal first_byte : std_logic;
- signal first_byte_q : std_logic;
- signal first_byte_qq : std_logic;
- signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal loaded_bytes_ctr : std_Logic_vector(15 downto 0);
+ signal ps_wr_en : std_logic;
+ signal ps_response_ready : std_logic;
+ signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal rc_rd_en : std_logic;
+ signal first_byte : std_logic;
+ signal first_byte_q : std_logic;
+ signal first_byte_qq : std_logic;
+ signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal loaded_bytes_ctr : std_Logic_vector(15 downto 0);
- signal dhcp_start : std_logic;
- signal dhcp_done : std_logic;
- signal wait_ctr : std_logic_vector(31 downto 0);
+ signal dhcp_start : std_logic;
+ signal dhcp_done : std_logic;
+ signal wait_ctr : std_logic_vector(31 downto 0);
- signal rc_data_local : std_logic_vector(8 downto 0);
+ signal rc_data_local : std_logic_vector(8 downto 0);
- -- debug
- signal frame_waiting_ctr : std_logic_vector(15 downto 0);
- signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ -- debug
+ signal frame_waiting_ctr : std_logic_vector(15 downto 0);
+ signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP);
- signal redirect_current_state, redirect_next_state : redirect_states;
- attribute syn_encoding of redirect_current_state : signal is "onehot";
+ type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP);
+ signal redirect_current_state, redirect_next_state : redirect_states;
+ attribute syn_encoding of redirect_current_state : signal is "onehot";
- signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
+ signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
- type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
- signal stats_current_state, stats_next_state : stats_states;
+ type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
+ signal stats_current_state, stats_next_state : stats_states;
- signal stat_rdy, stat_ack : std_logic;
- signal rx_stat_en_q : std_logic;
- signal rx_stat_vec_q : std_logic_vector(31 downto 0);
+ signal stat_rdy, stat_ack : std_logic;
+ signal rx_stat_en_q : std_logic;
+ signal rx_stat_vec_q : std_logic_vector(31 downto 0);
- type array_of_ctrs is array (15 downto 0) of std_logic_vector(31 downto 0);
- signal arr : array_of_ctrs;
- signal stats_ctr : integer range 0 to 15;
- signal stat_data : std_logic_vector(31 downto 0);
- signal stat_addr : std_logic_vector(7 downto 0);
+ type array_of_ctrs is array (15 downto 0) of std_logic_vector(31 downto 0);
+ signal arr : array_of_ctrs;
+ signal stats_ctr : integer range 0 to 15;
+ signal stat_data : std_logic_vector(31 downto 0);
+ signal stat_addr : std_logic_vector(7 downto 0);
- signal nothing_sent : std_logic;
- signal nothing_sent_ctr : std_logic_vector(31 downto 0);
+ signal nothing_sent : std_logic;
+ signal nothing_sent_ctr : std_logic_vector(31 downto 0);
- signal dbg_ps : std_Logic_vector(63 downto 0);
+ signal dbg_ps : std_Logic_vector(63 downto 0);
- signal tc_data : std_logic_vector(8 downto 0);
+ signal tc_data : std_logic_vector(8 downto 0);
- attribute syn_preserve : boolean;
- attribute syn_keep : boolean;
- attribute syn_keep of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
- attribute syn_preserve of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_keep of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
+ attribute syn_preserve of nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
- signal mc_busy : std_logic;
- signal incl_dhcp : std_logic;
- signal flow_state : std_logic_vector(3 downto 0);
- signal selector_debug : std_logic_vector(63 downto 0);
+ signal mc_busy : std_logic;
+ signal incl_dhcp : std_logic;
+ signal flow_state : std_logic_vector(3 downto 0);
+ signal selector_debug : std_logic_vector(63 downto 0);
begin
- protocol_selector : entity work.trb_net16_gbe_protocol_selector
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION,
- INCLUDE_READOUT => INCLUDE_READOUT,
- INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
- INCLUDE_DHCP => INCLUDE_DHCP,
- INCLUDE_ARP => INCLUDE_ARP,
- INCLUDE_PING => INCLUDE_PING,
- INCLUDE_FWD => INCLUDE_FWD,
- READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
- SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- RESET_FOR_DHCP => MC_RESET_LINK_IN,
- PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
- PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en,
- PS_PROTO_SELECT_IN => proto_select,
- PS_BUSY_OUT => ps_busy,
- PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
- PS_RESPONSE_READY_OUT => ps_response_ready,
- PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN,
- TC_DATA_OUT => tc_data,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT,
- TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT,
- TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT,
- TC_IDENT_OUT => TC_IDENT_OUT,
- TC_DEST_MAC_OUT => TC_DEST_MAC_OUT,
- TC_DEST_IP_OUT => TC_DEST_IP_OUT,
- TC_DEST_UDP_OUT => TC_DEST_UDP_OUT,
- TC_SRC_MAC_OUT => TC_SRC_MAC_OUT,
- TC_SRC_IP_OUT => TC_SRC_IP_OUT,
- TC_SRC_UDP_OUT => TC_SRC_UDP_OUT,
- MC_BUSY_IN => mc_busy,
- MY_MAC_IN => MC_MY_MAC_IN,
- MY_IP_OUT => MY_IP_OUT,
- DHCP_START_IN => dhcp_start,
- DHCP_DONE_OUT => dhcp_done,
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
- MAKE_RESET_OUT => MAKE_RESET_OUT,
-
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
- CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
- CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
- CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
- CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
- CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
- CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
- CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
-
- FWD_DST_MAC_IN => FWD_DST_MAC_IN,
- FWD_DST_IP_IN => FWD_DST_IP_IN,
- FWD_DST_UDP_IN => FWD_DST_UDP_IN,
- FWD_DATA_IN => FWD_DATA_IN,
- FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
- FWD_SOP_IN => FWD_SOP_IN,
- FWD_EOP_IN => FWD_EOP_IN,
- FWD_READY_OUT => FWD_READY_OUT,
- FWD_FULL_OUT => FWD_FULL_OUT,
-
-
- -- input for statistics from outside
- STAT_DATA_IN => stat_data,
- STAT_ADDR_IN => stat_addr,
- STAT_DATA_RDY_IN => stat_rdy,
- STAT_DATA_ACK_OUT => stat_ack,
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT,
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT,
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT,
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT,
- MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT,
- MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT,
- MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT,
- DATA_HIST_OUT => DATA_HIST_OUT,
- SCTRL_HIST_OUT => SCTRL_HIST_OUT,
- DEBUG_OUT => selector_debug
- );
-
- TC_DATA_OUT <= tc_data;
-
- -- gk 07.11.11
- -- do not select any response constructors when dropping a frame
- proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
-
- -- gk 07.11.11
- DISABLE_REDIRECT_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- disable_redirect <= '0';
- elsif (redirect_current_state = CHECK_TYPE) then
- if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then
- disable_redirect <= '1';
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then
- disable_redirect <= '1';
- else
- disable_redirect <= '0';
- end if;
- else
- disable_redirect <= disable_redirect;
- end if;
- end if;
- end process DISABLE_REDIRECT_PROC;
-
- -- warning
- SYNC_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- rc_data_local <= RC_DATA_IN;
- end if;
- end process SYNC_PROC;
-
- REDIRECT_MACHINE_PROC : process(RESET, CLK)
- begin
- if RESET = '1' then
- redirect_current_state <= IDLE;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- redirect_current_state <= redirect_next_state;
- else
- redirect_current_state <= IDLE;
- end if;
- end if;
- end process REDIRECT_MACHINE_PROC;
-
- REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN)
- begin
- redirect_state <= x"0";
-
- case redirect_current_state is
- when IDLE =>
- redirect_state <= x"1";
- if (RC_FRAME_WAITING_IN = '1') then
- redirect_next_state <= CHECK_TYPE;
- else
- redirect_next_state <= IDLE;
- end if;
-
- when CHECK_TYPE =>
- redirect_state <= x"2";
- if (link_current_state = ACTIVE) then
- redirect_next_state <= CHECK_BUSY;
- elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
- redirect_next_state <= CHECK_BUSY;
- else
- redirect_next_state <= DROP;
- end if;
-
- when DROP =>
- redirect_state <= x"3";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE;
- else
- redirect_next_state <= DROP;
- end if;
-
- when CHECK_BUSY =>
- redirect_state <= x"4";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
- redirect_next_state <= LOAD;
- else
- redirect_next_state <= BUSY;
- end if;
-
- when LOAD =>
- redirect_state <= x"5";
- if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE;
- else
- redirect_next_state <= LOAD;
- end if;
-
- when BUSY =>
- redirect_state <= x"6";
- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
- redirect_next_state <= LOAD;
- else
- redirect_next_state <= BUSY;
- end if;
-
- when WAIT_ONE =>
- redirect_state <= x"7";
- redirect_next_state <= FINISH;
-
- when FINISH =>
- redirect_state <= x"8";
- redirect_next_state <= CLEANUP;
-
- when CLEANUP =>
- redirect_state <= x"9";
- redirect_next_state <= IDLE;
-
- when others => redirect_next_state <= IDLE;
-
- end case;
- end process REDIRECT_MACHINE;
-
- rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0';
- RC_RD_EN_OUT <= rc_rd_en;
-
- LOADING_DONE_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then
- RC_LOADING_DONE_OUT <= '1';
- else
- RC_LOADING_DONE_OUT <= '0';
- end if;
- end if;
- end process LOADING_DONE_PROC;
-
- PS_WR_EN_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- ps_wr_en <= rc_rd_en;
- ps_wr_en_q <= ps_wr_en;
- ps_wr_en_qq <= ps_wr_en_q;
- end if;
- end process PS_WR_EN_PROC;
-
- LOADED_BYTES_CTR_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (redirect_current_state = IDLE) then
- loaded_bytes_ctr <= (others => '0');
- elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
- loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- end if;
- end process LOADED_BYTES_CTR_PROC;
-
- FIRST_BYTE_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- first_byte_q <= first_byte;
- first_byte_qq <= first_byte_q;
-
- if (redirect_current_state = IDLE) then
- first_byte <= '1';
- else
- first_byte <= '0';
- end if;
- end if;
- end process FIRST_BYTE_PROC;
-
- --*********************
- -- DATA FLOW CONTROL
-
- FLOW_MACHINE_PROC : process(RESET, CLK)
- begin
- if RESET = '1' then
- flow_current_state <= IDLE;
- elsif rising_edge(CLK) then
- flow_current_state <= flow_next_state;
- end if;
- end process FLOW_MACHINE_PROC;
-
- FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data)
- begin
- flow_state <= x"0";
-
- case flow_current_state is
- when IDLE =>
- flow_state <= x"1";
- if (ps_response_ready = '1') then
- flow_next_state <= TRANSMIT_CTRL;
- else
- flow_next_state <= IDLE;
- end if;
-
- when TRANSMIT_CTRL =>
- flow_state <= x"2";
- if (tc_data(8) = '1') then
- flow_next_state <= WAIT_FOR_FC;
- else
- flow_next_state <= TRANSMIT_CTRL;
- end if;
-
- when WAIT_FOR_FC =>
- flow_state <= x"3";
- if (TC_TRANSMIT_DONE_IN = '1') then
- flow_next_state <= CLEANUP;
- else
- flow_next_state <= WAIT_FOR_FC;
- end if;
-
- when CLEANUP =>
- flow_state <= x"4";
- flow_next_state <= IDLE;
-
- when others => flow_next_state <= IDLE;
-
- end case;
- end process FLOW_MACHINE;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if (flow_current_state = IDLE and ps_response_ready = '1') then
- TC_TRANSMIT_CTRL_OUT <= '1';
- else
- TC_TRANSMIT_CTRL_OUT <= '0';
- end if;
-
- if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then
- mc_busy <= '1';
- else
- mc_busy <= '0';
- end if;
- end if;
- end process;
-
- --***********************
- -- LINK STATE CONTROL
-
- lsm_impl_gen : if DO_SIMULATION = 0 generate
- LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
- begin
- if MC_RESET_LINK_IN = '1' then
- link_current_state <= INACTIVE;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- link_current_state <= link_next_state;
- else
- link_current_state <= INACTIVE;
- end if;
- end if;
- end process;
- end generate lsm_impl_gen;
-
- lsm_sim_gen : if DO_SIMULATION = 1 generate
- LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
- begin
- if MC_RESET_LINK_IN = '1' then
- link_current_state <= GET_ADDRESS;
- elsif rising_edge(CLK) then
- if RX_PATH_ENABLE = 1 then
- link_current_state <= link_next_state;
- else
- link_current_state <= ACTIVE;
- end if;
- end if;
- end process;
- end generate lsm_sim_gen;
-
- incl_dhcp_gen : if (INCLUDE_DHCP = '1') generate
- incl_dhcp <= '1';
- end generate incl_dhcp_gen;
- noincl_dhcp_gen : if (INCLUDE_DHCP = '0') generate
- incl_dhcp <= '0';
- end generate noincl_dhcp_gen;
-
- LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr)
- begin
- link_state <= x"0";
-
- case link_current_state is
- when INACTIVE =>
- link_state <= x"1";
- if (PCS_AN_COMPLETE_IN = '1') then
- link_next_state <= TIMEOUT;
- else
- link_next_state <= INACTIVE;
- end if;
-
- when TIMEOUT =>
- link_state <= x"2";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (link_ok_timeout_ctr = x"ffff") then
- link_next_state <= ENABLE_MAC; --FINALIZE;
- else
- link_next_state <= TIMEOUT;
- end if;
- end if;
-
- when ENABLE_MAC =>
- link_state <= x"3";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- --elsif (tsm_ready = '1') then
- elsif (MAC_READY_CONF_IN = '1') then
- link_next_state <= FINALIZE; --INACTIVE;
- else
- link_next_state <= ENABLE_MAC;
- end if;
-
- when FINALIZE =>
- link_state <= x"4";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
- end if;
-
- when WAIT_FOR_BOOT =>
- link_state <= x"5";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (wait_ctr = x"0000_1000") then
- if (incl_dhcp = '1') then
- link_next_state <= GET_ADDRESS;
- else
- link_next_state <= ACTIVE;
- end if;
- else
- link_next_state <= WAIT_FOR_BOOT;
- end if;
- end if;
-
- when GET_ADDRESS =>
- link_state <= x"6";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- if (dhcp_done = '1') then
- link_next_state <= ACTIVE;
- else
- link_next_state <= GET_ADDRESS;
- end if;
- end if;
-
- when ACTIVE =>
- link_state <= x"7";
- if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE;
- else
- link_next_state <= ACTIVE;
- end if;
-
- when others => link_next_state <= INACTIVE;
-
- end case;
- end process LINK_STATE_MACHINE;
-
- MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0';
-
- LINK_OK_CTR_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- --if (RESET = '1') or (link_current_state /= TIMEOUT) then
- if (link_current_state /= TIMEOUT) then
- link_ok_timeout_ctr <= (others => '0');
- elsif (link_current_state = TIMEOUT) then
- link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
- end if;
-
- -- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then
- -- link_ok <= '1';
- -- else
- -- link_ok <= '0';
- -- end if;
-
- if (link_current_state = GET_ADDRESS) then
- dhcp_start <= '1';
- else
- dhcp_start <= '0';
- end if;
- end if;
- end process LINK_OK_CTR_PROC;
-
- --link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0';
- link_ok <= '1';
-
- WAIT_CTR_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (link_current_state = WAIT_FOR_BOOT) then
- wait_ctr <= wait_ctr + x"1";
- else
- wait_ctr <= (others => '0');
- end if;
- end if;
- end process WAIT_CTR_PROC;
-
- --dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
-
- --LINK_DOWN_CTR_PROC : process(CLK)
- --begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') then
- -- link_down_ctr <= (others => '0');
- -- link_down_ctr_lock <= '0';
- -- elsif (PCS_AN_COMPLETE_IN = '1') then
- -- link_down_ctr_lock <= '0';
- -- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then
- -- link_down_ctr <= link_down_ctr + x"1";
- -- link_down_ctr_lock <= '1';
- -- end if;
- -- end if;
- --end process LINK_DOWN_CTR_PROC;
-
- MC_LINK_OK_OUT <= link_ok; -- or nothing_sent;
-
- -- END OF LINK STATE CONTROL
- --*************
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
- tsm_reconf <= '1';
- else
- tsm_reconf <= '0';
- end if;
- end if;
- end process;
- MAC_RECONF_OUT <= tsm_reconf;
- --tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0';
-
- TSM_HADDR_OUT <= tsm_haddr;
- TSM_HCS_N_OUT <= tsm_hcs_n;
- TSM_HDATA_OUT <= tsm_hdata;
- TSM_HREAD_N_OUT <= tsm_hread_n;
- TSM_HWRITE_N_OUT <= tsm_hwrite_n;
-
- -- END OF TRI SPEED MAC CONTROLLER
- --***************
-
-
- -- *****
- -- STATISTICS
- -- *****
-
- --
- --CTRS_GEN : for n in 0 to 15 generate
- --
- -- CTR_PROC : process(CLK)
- -- begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') then
- -- arr(n) <= (others => '0');
- -- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then
- -- arr(n) <= arr(n) + x"1";
- -- end if;
- -- end if;
- -- end process CTR_PROC;
- --
- --end generate CTRS_GEN;
- --
- --STAT_VEC_SYNC : signal_sync
- --generic map (
- -- WIDTH => 32,
- -- DEPTH => 2
- --)
- --port map (
- -- RESET => RESET,
- -- CLK0 => CLK,
- -- CLK1 => CLK,
- -- D_IN => TSM_RX_STAT_VEC_IN,
- -- D_OUT => rx_stat_vec_q
- --);
- --
- --
- --STAT_VEC_EN_SYNC : pulse_sync
- --port map(
- -- CLK_A_IN => CLK_125,
- -- RESET_A_IN => RESET,
- -- PULSE_A_IN => TSM_RX_STAT_EN_IN,
- -- CLK_B_IN => CLK,
- -- RESET_B_IN => RESET,
- -- PULSE_B_OUT => rx_stat_en_q
- --);
- --
- --
- --STATS_MACHINE_PROC : process(CLK)
- --begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') then
- -- stats_current_state <= IDLE;
- -- else
- -- stats_current_state <= stats_next_state;
- -- end if;
- -- end if;
- --end process STATS_MACHINE_PROC;
- --
- --STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr)
- --begin
- --
- -- case (stats_current_state) is
- --
- -- when IDLE =>
- -- if (rx_stat_en_q = '1') then
- -- stats_next_state <= LOAD_VECTOR;
- -- else
- -- stats_next_state <= IDLE;
- -- end if;
- --
- -- when LOAD_VECTOR =>
- -- --if (stat_ack = '1') then
- -- if (stats_ctr = 15) then
- -- stats_next_state <= CLEANUP;
- -- else
- -- stats_next_state <= LOAD_VECTOR;
- -- end if;
- --
- -- when CLEANUP =>
- -- stats_next_state <= IDLE;
- --
- -- end case;
- --
- --end process STATS_MACHINE;
- --
- --STATS_CTR_PROC : process(CLK)
- --begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') or (stats_current_state = IDLE) then
- -- stats_ctr <= 0;
- -- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then
- -- stats_ctr <= stats_ctr + 1;
- -- end if;
- -- end if;
- --end process STATS_CTR_PROC;
- --
- ----stat_data <= arr(stats_ctr);
- --
- --stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8));
- --
- --stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
- --
- --stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24);
- --stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16);
- --stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8);
- --stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0);
-
-
- -- **** debug
- --FRAME_WAITING_CTR_PROC : process(CLK)
- --begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') then
- -- frame_waiting_ctr <= (others => '0');
- -- elsif (RC_FRAME_WAITING_IN = '1') then
- -- frame_waiting_ctr <= frame_waiting_ctr + x"1";
- -- end if;
- -- end if;
- --end process FRAME_WAITING_CTR_PROC;
- --
- --SAVE_VALUES_PROC : process(CLK)
- --begin
- -- if rising_edge(CLK) then
- -- if (RESET = '1') then
- -- ps_busy_q <= (others => '0');
- -- rc_frame_proto_q <= (others => '0');
- -- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then
- -- ps_busy_q <= ps_busy;
- -- rc_frame_proto_q <= RC_FRAME_PROTO_IN;
- -- end if;
- -- end if;
- --end process SAVE_VALUES_PROC;
-
-
- -- ****
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- DEBUG_OUT(3 downto 0) <= redirect_state;
- DEBUG_OUT(7 downto 4) <= flow_state;
- DEBUG_OUT(11 downto 8) <= link_state;
- DEBUG_OUT(31 downto 12) <= (others => '0');
-
- DEBUG_OUT(63 downto 32) <= selector_debug(31 downto 0);
- end if;
- end process;
+ protocol_selector : entity work.trb_net16_gbe_protocol_selector
+ generic map(
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_READOUT => INCLUDE_READOUT,
+ INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL,
+ INCLUDE_DHCP => INCLUDE_DHCP,
+ INCLUDE_ARP => INCLUDE_ARP,
+ INCLUDE_PING => INCLUDE_PING,
+ INCLUDE_FWD => INCLUDE_FWD,
+ READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE,
+ SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ RESET_FOR_DHCP => MC_RESET_LINK_IN,
+ PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
+ PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en,
+ PS_PROTO_SELECT_IN => proto_select,
+ PS_BUSY_OUT => ps_busy,
+ PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
+ PS_RESPONSE_READY_OUT => ps_response_ready,
+ PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN,
+ TC_DATA_OUT => tc_data,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT,
+ TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT,
+ TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT,
+ TC_IDENT_OUT => TC_IDENT_OUT,
+ TC_DEST_MAC_OUT => TC_DEST_MAC_OUT,
+ TC_DEST_IP_OUT => TC_DEST_IP_OUT,
+ TC_DEST_UDP_OUT => TC_DEST_UDP_OUT,
+ TC_SRC_MAC_OUT => TC_SRC_MAC_OUT,
+ TC_SRC_IP_OUT => TC_SRC_IP_OUT,
+ TC_SRC_UDP_OUT => TC_SRC_UDP_OUT,
+ MC_BUSY_IN => mc_busy,
+ MY_MAC_IN => MC_MY_MAC_IN,
+ MY_IP_OUT => MY_IP_OUT,
+ DHCP_START_IN => dhcp_start,
+ DHCP_DONE_OUT => dhcp_done,
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+ MAKE_RESET_OUT => MAKE_RESET_OUT,
+
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
+
+ -- CTS interface
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data payload interface
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- ip configurator
+ SLV_ADDR_IN => SLV_ADDR_IN,
+ SLV_READ_IN => SLV_READ_IN,
+ SLV_WRITE_IN => SLV_WRITE_IN,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT,
+ SLV_DATA_IN => SLV_DATA_IN,
+ SLV_DATA_OUT => SLV_DATA_OUT,
+ CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
+ CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
+ CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
+ CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
+ CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
+ CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
+ CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
+ CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
+ CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
+ CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
+ CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
+ CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
+ CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
+ CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
+ CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
+ CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN,
+ FWD_DST_IP_IN => FWD_DST_IP_IN,
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+
+ -- input for statistics from outside
+ STAT_DATA_IN => stat_data,
+ STAT_ADDR_IN => stat_addr,
+ STAT_DATA_RDY_IN => stat_rdy,
+ STAT_DATA_ACK_OUT => stat_ack,
+ MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT,
+ MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT,
+ MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT,
+ MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT,
+ MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT,
+ MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT,
+ MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT,
+ DATA_HIST_OUT => DATA_HIST_OUT,
+ SCTRL_HIST_OUT => SCTRL_HIST_OUT,
+ DEBUG_OUT => selector_debug
+ );
+
+ TC_DATA_OUT <= tc_data;
+
+ -- gk 07.11.11
+ -- do not select any response constructors when dropping a frame
+ proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
+
+ -- gk 07.11.11
+ DISABLE_REDIRECT_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ disable_redirect <= '0';
+ elsif (redirect_current_state = CHECK_TYPE) then
+ if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then
+ disable_redirect <= '1';
+ elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then
+ disable_redirect <= '1';
+ else
+ disable_redirect <= '0';
+ end if;
+ else
+ disable_redirect <= disable_redirect;
+ end if;
+ end if;
+ end process DISABLE_REDIRECT_PROC;
+
+ -- warning
+ SYNC_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ rc_data_local <= RC_DATA_IN;
+ end if;
+ end process SYNC_PROC;
+
+ REDIRECT_MACHINE_PROC : process(RESET, CLK)
+ begin
+ if RESET = '1' then
+ redirect_current_state <= IDLE;
+ elsif rising_edge(CLK) then
+ if RX_PATH_ENABLE = 1 then
+ redirect_current_state <= redirect_next_state;
+ else
+ redirect_current_state <= IDLE;
+ end if;
+ end if;
+ end process REDIRECT_MACHINE_PROC;
+
+ REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN)
+ begin
+ redirect_state <= x"0";
+
+ case redirect_current_state is
+ when IDLE =>
+ redirect_state <= x"1";
+ if (RC_FRAME_WAITING_IN = '1') then
+ redirect_next_state <= CHECK_TYPE;
+ else
+ redirect_next_state <= IDLE;
+ end if;
+
+ when CHECK_TYPE =>
+ redirect_state <= x"2";
+ if (link_current_state = ACTIVE) then
+ redirect_next_state <= CHECK_BUSY;
+ elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
+ redirect_next_state <= CHECK_BUSY;
+ else
+ redirect_next_state <= DROP;
+ end if;
+
+ when DROP =>
+ redirect_state <= x"3";
+ if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
+ redirect_next_state <= WAIT_ONE;
+ else
+ redirect_next_state <= DROP;
+ end if;
+
+ when CHECK_BUSY =>
+ redirect_state <= x"4";
+ if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
+ redirect_next_state <= LOAD;
+ else
+ redirect_next_state <= BUSY;
+ end if;
+
+ when LOAD =>
+ redirect_state <= x"5";
+ if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
+ redirect_next_state <= WAIT_ONE;
+ else
+ redirect_next_state <= LOAD;
+ end if;
+
+ when BUSY =>
+ redirect_state <= x"6";
+ if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
+ redirect_next_state <= LOAD;
+ else
+ redirect_next_state <= BUSY;
+ end if;
+
+ when WAIT_ONE =>
+ redirect_state <= x"7";
+ redirect_next_state <= FINISH;
+
+ when FINISH =>
+ redirect_state <= x"8";
+ redirect_next_state <= CLEANUP;
+
+ when CLEANUP =>
+ redirect_state <= x"9";
+ redirect_next_state <= IDLE;
+
+ when others => redirect_next_state <= IDLE;
+
+ end case;
+ end process REDIRECT_MACHINE;
+
+ rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0';
+ RC_RD_EN_OUT <= rc_rd_en;
+
+ LOADING_DONE_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then
+ RC_LOADING_DONE_OUT <= '1';
+ else
+ RC_LOADING_DONE_OUT <= '0';
+ end if;
+ end if;
+ end process LOADING_DONE_PROC;
+
+ PS_WR_EN_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ ps_wr_en <= rc_rd_en;
+ ps_wr_en_q <= ps_wr_en;
+ ps_wr_en_qq <= ps_wr_en_q;
+ end if;
+ end process PS_WR_EN_PROC;
+
+ LOADED_BYTES_CTR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (redirect_current_state = IDLE) then
+ loaded_bytes_ctr <= (others => '0');
+ elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
+ loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
+ else
+ loaded_bytes_ctr <= loaded_bytes_ctr;
+ end if;
+ end if;
+ end process LOADED_BYTES_CTR_PROC;
+
+ FIRST_BYTE_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ first_byte_q <= first_byte;
+ first_byte_qq <= first_byte_q;
+
+ if (redirect_current_state = IDLE) then
+ first_byte <= '1';
+ else
+ first_byte <= '0';
+ end if;
+ end if;
+ end process FIRST_BYTE_PROC;
+
+ --*********************
+ -- DATA FLOW CONTROL
+
+ FLOW_MACHINE_PROC : process(RESET, CLK)
+ begin
+ if RESET = '1' then
+ flow_current_state <= IDLE;
+ elsif rising_edge(CLK) then
+ flow_current_state <= flow_next_state;
+ end if;
+ end process FLOW_MACHINE_PROC;
+
+ FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data)
+ begin
+ flow_state <= x"0";
+
+ case flow_current_state is
+ when IDLE =>
+ flow_state <= x"1";
+ if (ps_response_ready = '1') then
+ flow_next_state <= TRANSMIT_CTRL;
+ else
+ flow_next_state <= IDLE;
+ end if;
+
+ when TRANSMIT_CTRL =>
+ flow_state <= x"2";
+ if (tc_data(8) = '1') then
+ flow_next_state <= WAIT_FOR_FC;
+ else
+ flow_next_state <= TRANSMIT_CTRL;
+ end if;
+
+ when WAIT_FOR_FC =>
+ flow_state <= x"3";
+ if (TC_TRANSMIT_DONE_IN = '1') then
+ flow_next_state <= CLEANUP;
+ else
+ flow_next_state <= WAIT_FOR_FC;
+ end if;
+
+ when CLEANUP =>
+ flow_state <= x"4";
+ flow_next_state <= IDLE;
+
+ when others => flow_next_state <= IDLE;
+
+ end case;
+ end process FLOW_MACHINE;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (flow_current_state = IDLE and ps_response_ready = '1') then
+ TC_TRANSMIT_CTRL_OUT <= '1';
+ else
+ TC_TRANSMIT_CTRL_OUT <= '0';
+ end if;
+
+ if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then
+ mc_busy <= '1';
+ else
+ mc_busy <= '0';
+ end if;
+ end if;
+ end process;
+
+ --***********************
+ -- LINK STATE CONTROL
+
+ lsm_impl_gen : if DO_SIMULATION = 0 generate
+ LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
+ begin
+ if MC_RESET_LINK_IN = '1' then
+ link_current_state <= INACTIVE;
+ elsif rising_edge(CLK) then
+ if RX_PATH_ENABLE = 1 then
+ link_current_state <= link_next_state;
+ else
+ link_current_state <= INACTIVE;
+ end if;
+ end if;
+ end process;
+ end generate lsm_impl_gen;
+
+ lsm_sim_gen : if DO_SIMULATION = 1 generate
+ LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK)
+ begin
+ if MC_RESET_LINK_IN = '1' then
+ link_current_state <= GET_ADDRESS;
+ elsif rising_edge(CLK) then
+ if RX_PATH_ENABLE = 1 then
+ link_current_state <= link_next_state;
+ else
+ link_current_state <= ACTIVE;
+ end if;
+ end if;
+ end process;
+ end generate lsm_sim_gen;
+
+ incl_dhcp_gen : if (INCLUDE_DHCP = '1') generate
+ incl_dhcp <= '1';
+ end generate incl_dhcp_gen;
+ noincl_dhcp_gen : if (INCLUDE_DHCP = '0') generate
+ incl_dhcp <= '0';
+ end generate noincl_dhcp_gen;
+
+ LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr)
+ begin
+ link_state <= x"0";
+
+ case link_current_state is
+ when INACTIVE =>
+ link_state <= x"1";
+ if (PCS_AN_COMPLETE_IN = '1') then
+ link_next_state <= TIMEOUT;
+ else
+ link_next_state <= INACTIVE;
+ end if;
+
+ when TIMEOUT =>
+ link_state <= x"2";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ else
+ if (link_ok_timeout_ctr = x"ffff") then
+ link_next_state <= ENABLE_MAC; --FINALIZE;
+ else
+ link_next_state <= TIMEOUT;
+ end if;
+ end if;
+
+ when ENABLE_MAC =>
+ link_state <= x"3";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ elsif (MAC_READY_CONF_IN = '1') then
+ link_next_state <= FINALIZE; --INACTIVE;
+ else
+ link_next_state <= ENABLE_MAC;
+ end if;
+
+ when FINALIZE =>
+ link_state <= x"4";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ else
+ link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
+ end if;
+
+ when WAIT_FOR_BOOT =>
+ link_state <= x"5";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ else
+ if (wait_ctr = x"0000_1000") then
+ if (incl_dhcp = '1') then
+ link_next_state <= GET_ADDRESS;
+ else
+ link_next_state <= ACTIVE;
+ end if;
+ else
+ link_next_state <= WAIT_FOR_BOOT;
+ end if;
+ end if;
+
+ when GET_ADDRESS =>
+ link_state <= x"6";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ else
+ if (dhcp_done = '1') then
+ link_next_state <= ACTIVE;
+ else
+ link_next_state <= GET_ADDRESS;
+ end if;
+ end if;
+
+ when ACTIVE =>
+ link_state <= x"7";
+ if (PCS_AN_COMPLETE_IN = '0') then
+ link_next_state <= INACTIVE;
+ else
+ link_next_state <= ACTIVE;
+ end if;
+
+ when others => link_next_state <= INACTIVE;
+
+ end case;
+ end process LINK_STATE_MACHINE;
+
+ MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0';
+
+ LINK_OK_CTR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (link_current_state /= TIMEOUT) then
+ link_ok_timeout_ctr <= (others => '0');
+ elsif (link_current_state = TIMEOUT) then
+ link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
+ end if;
+
+ if (link_current_state = GET_ADDRESS) then
+ dhcp_start <= '1';
+ else
+ dhcp_start <= '0';
+ end if;
+ end if;
+ end process LINK_OK_CTR_PROC;
+
+ link_ok <= '1';
+
+ WAIT_CTR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (link_current_state = WAIT_FOR_BOOT) then
+ wait_ctr <= wait_ctr + x"1";
+ else
+ wait_ctr <= (others => '0');
+ end if;
+ end if;
+ end process WAIT_CTR_PROC;
+
+ MC_LINK_OK_OUT <= link_ok; -- or nothing_sent;
+
+ -- END OF LINK STATE CONTROL
+ --*************
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
+ tsm_reconf <= '1';
+ else
+ tsm_reconf <= '0';
+ end if;
+ end if;
+ end process;
+ MAC_RECONF_OUT <= tsm_reconf;
+
+ TSM_HADDR_OUT <= tsm_haddr;
+ TSM_HCS_N_OUT <= tsm_hcs_n;
+ TSM_HDATA_OUT <= tsm_hdata;
+ TSM_HREAD_N_OUT <= tsm_hread_n;
+ TSM_HWRITE_N_OUT <= tsm_hwrite_n;
+
+ -- END OF TRI SPEED MAC CONTROLLER
+ --***************
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ DEBUG_OUT(3 downto 0) <= redirect_state;
+ DEBUG_OUT(7 downto 4) <= flow_state;
+ DEBUG_OUT(11 downto 8) <= link_state;
+ DEBUG_OUT(31 downto 12) <= (others => '0');
+
+ DEBUG_OUT(63 downto 32) <= selector_debug(31 downto 0);
+ end if;
+ end process;
end trb_net16_gbe_main_control;
entity trb_net16_gbe_protocol_selector is
- generic(
- RX_PATH_ENABLE : integer range 0 to 1 := 1;
- DO_SIMULATION : integer range 0 to 1 := 0;
- INCLUDE_READOUT : std_logic := '0';
- INCLUDE_SLOWCTRL : std_logic := '0';
- INCLUDE_DHCP : std_logic := '0';
- INCLUDE_ARP : std_logic := '0';
- INCLUDE_PING : std_logic := '0';
- INCLUDE_FWD : std_logic := '0';
- READOUT_BUFFER_SIZE : integer range 1 to 4;
- SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
- );
- port(
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
- RESET_FOR_DHCP : in std_logic;
-
- -- signals to/from main controller
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- -- singals to/from transmit controller with constructed response
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- MC_BUSY_IN : in std_logic;
-
- -- misc signals for response constructors
- MY_MAC_IN : in std_logic_vector(47 downto 0);
- MY_IP_OUT : out std_logic_vector(31 downto 0);
- DHCP_START_IN : in std_logic;
- DHCP_DONE_OUT : out std_logic;
- GSC_CLK_IN : in std_logic;
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
- MAKE_RESET_OUT : out std_logic;
-
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
- ISSUE_REBOOT_OUT : out std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
- CTS_CODE_IN : in std_logic_vector(7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
- CFG_READOUT_CTR_VALID_IN : in std_logic;
- CFG_INSERT_TTYPE_IN : in std_logic;
- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
- CFG_ADDITIONAL_HDR_IN : in std_logic;
- CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
- CFG_AUTO_THROTTLE_IN : in std_logic;
- CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
-
--- Forwarder
-FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
-FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
-FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
-FWD_DATA_IN : in std_logic_vector(7 downto 0);
-FWD_DATA_VALID_IN : in std_logic;
-FWD_SOP_IN : in std_logic;
-FWD_EOP_IN : in std_logic;
-FWD_READY_OUT : out std_logic;
-FWD_FULL_OUT : out std_logic;
-
- -- input for statistics from outside
- STAT_DATA_IN : in std_logic_vector(31 downto 0);
- STAT_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT_DATA_RDY_IN : in std_logic;
- STAT_DATA_ACK_OUT : out std_logic;
- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
- DATA_HIST_OUT : out hist_array;
- SCTRL_HIST_OUT : out hist_array;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
- );
+ generic(
+ RX_PATH_ENABLE : integer range 0 to 1 := 1;
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ INCLUDE_READOUT : std_logic := '0';
+ INCLUDE_SLOWCTRL : std_logic := '0';
+ INCLUDE_DHCP : std_logic := '0';
+ INCLUDE_ARP : std_logic := '0';
+ INCLUDE_PING : std_logic := '0';
+ INCLUDE_FWD : std_logic := '0';
+ READOUT_BUFFER_SIZE : integer range 1 to 4;
+ SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
+ );
+ port(
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+ RESET_FOR_DHCP : in std_logic;
+
+ -- signals to/from main controller
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ -- singals to/from transmit controller with constructed response
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_RD_EN_IN : in std_logic;
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ MC_BUSY_IN : in std_logic;
+
+ -- misc signals for response constructors
+ MY_MAC_IN : in std_logic_vector(47 downto 0);
+ MY_IP_OUT : out std_logic_vector(31 downto 0);
+ DHCP_START_IN : in std_logic;
+ DHCP_DONE_OUT : out std_logic;
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ MAKE_RESET_OUT : out std_logic;
+
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+
+ -- signal for data readout
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ -- ip configurator
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ CFG_GBE_ENABLE_IN : in std_logic;
+ CFG_IPU_ENABLE_IN : in std_logic;
+ CFG_MULT_ENABLE_IN : in std_logic;
+ CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
+ CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
+ CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
+ CFG_READOUT_CTR_VALID_IN : in std_logic;
+ CFG_INSERT_TTYPE_IN : in std_logic;
+ CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
+ CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
+ CFG_ADDITIONAL_HDR_IN : in std_logic;
+ CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
+ CFG_AUTO_THROTTLE_IN : in std_logic;
+ CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+
+ -- Forwarder
+ FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
+ FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
+ FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
+ FWD_DATA_IN : in std_logic_vector(7 downto 0);
+ FWD_DATA_VALID_IN : in std_logic;
+ FWD_SOP_IN : in std_logic;
+ FWD_EOP_IN : in std_logic;
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+
+ -- input for statistics from outside
+ STAT_DATA_IN : in std_logic_vector(31 downto 0);
+ STAT_ADDR_IN : in std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_IN : in std_logic;
+ STAT_DATA_ACK_OUT : out std_logic;
+ MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ DATA_HIST_OUT : out hist_array;
+ SCTRL_HIST_OUT : out hist_array;
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
end trb_net16_gbe_protocol_selector;
architecture trb_net16_gbe_protocol_selector of trb_net16_gbe_protocol_selector is
- --attribute HGROUP : string;
- --attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group";
-
- attribute syn_encoding : string;
-
- signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0);
- signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
- signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
- signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
-
- -- plus 1 is for the outside
- signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
- signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-
- signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP);
- signal select_current_state, select_next_state : select_states;
- attribute syn_encoding of select_current_state : signal is "onehot";
-
- signal state : std_logic_vector(3 downto 0);
- signal index : integer range 0 to c_MAX_PROTOCOLS - 1;
-
- signal mult : std_logic;
-
- signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
- signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
- attribute syn_preserve : boolean;
- attribute syn_keep : boolean;
- attribute syn_keep of state, mult : signal is true;
- attribute syn_preserve of state, mult : signal is true;
-
- signal my_ip : std_logic_vector(31 downto 0);
- signal select_state : std_logic_vector(3 downto 0);
+ --attribute HGROUP : string;
+ --attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group";
+
+ attribute syn_encoding : string;
+
+ signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0);
+ signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal selected : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal tc_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
+ signal tc_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal tc_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_src_mac : std_logic_vector(c_MAX_PROTOCOLS * 48 - 1 downto 0);
+ signal tc_src_ip : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
+
+ -- plus 1 is for the outside
+ signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+ signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
+ signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+
+ signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+
+ type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP);
+ signal select_current_state, select_next_state : select_states;
+ attribute syn_encoding of select_current_state : signal is "onehot";
+
+ signal state : std_logic_vector(3 downto 0);
+ signal index : integer range 0 to c_MAX_PROTOCOLS - 1;
+
+ signal mult : std_logic;
+
+ signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+ signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_keep of state, mult : signal is true;
+ attribute syn_preserve of state, mult : signal is true;
+
+ signal my_ip : std_logic_vector(31 downto 0);
+ signal select_state : std_logic_vector(3 downto 0);
begin
- zeros <= (others => '0');
- MY_IP_OUT <= my_ip;
-
- arp_gen : if INCLUDE_ARP = '1' generate
- -- protocol Nr. 1 ARP
- ARP : trb_net16_gbe_response_constructor_ARP
- generic map(STAT_ADDRESS_BASE => 6
- )
- port map(
- CLK => CLK,
- RESET => RESET,
-
- -- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0),
- PS_RESPONSE_READY_OUT => resp_ready(0),
- PS_BUSY_OUT => busy(0),
- PS_SELECTED_IN => selected(0),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9),
- TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16),
- TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8),
- TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16),
- TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48),
- TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32),
- TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48),
- TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16),
- STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
- STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(0),
- STAT_DATA_ACK_IN => stat_ack(0),
- RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
- -- END OF INTERFACE
- );
- end generate arp_gen;
-
- no_arp_gen : if INCLUDE_ARP = '0' generate
- resp_ready(0) <= '0';
- busy(0) <= '0';
- end generate no_arp_gen;
-
- dhcp_gen : if INCLUDE_DHCP = '1' generate
- -- protocol No. 2 DHCP
- DHCP : trb_net16_gbe_response_constructor_DHCP
- generic map(
- STAT_ADDRESS_BASE => 0,
- DO_SIMULATION => DO_SIMULATION
- )
- port map(
- CLK => CLK,
- RESET => RESET_FOR_DHCP, --RESET,
-
- -- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1),
- PS_RESPONSE_READY_OUT => resp_ready(1),
- PS_BUSY_OUT => busy(1),
- PS_SELECTED_IN => selected(1),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9),
- TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16),
- TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8),
- TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16),
- TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48),
- TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32),
- TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48),
- TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16),
- STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
- STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(1),
- STAT_DATA_ACK_IN => stat_ack(1),
- RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
- SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
- -- END OF INTERFACE
-
- MY_IP_OUT => my_ip,
- DHCP_START_IN => DHCP_START_IN,
- DHCP_DONE_OUT => DHCP_DONE_OUT,
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
- );
- end generate dhcp_gen;
-
- no_dhcp_gen : if INCLUDE_DHCP = '0' generate
- resp_ready(1) <= '0';
- busy(1) <= '0';
- end generate no_dhcp_gen;
-
- ping_gen : if INCLUDE_PING = '1' generate
- --protocol No. 3 Ping
- Ping : entity work.trb_net16_gbe_response_constructor_KillPing
- generic map(STAT_ADDRESS_BASE => 3
- )
- port map(
- CLK => CLK,
- RESET => RESET,
-
- ---- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
- ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
- PS_RESPONSE_READY_OUT => resp_ready(4),
- PS_BUSY_OUT => busy(4),
- PS_SELECTED_IN => selected(4),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
- TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16),
- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
- STAT_DATA_OUT => open,
- STAT_ADDR_OUT => open,
- STAT_DATA_RDY_OUT => open,
- STAT_DATA_ACK_IN => '0',
- RECEIVED_FRAMES_OUT => open,
- SENT_FRAMES_OUT => open,
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64)
- -- END OF INTERFACE
- );
- end generate ping_gen;
-
- no_ping_gen : if INCLUDE_PING = '0' generate
- resp_ready(4) <= '0';
- busy(4) <= '0';
- end generate no_ping_gen;
-
- sctrl_gen : if INCLUDE_SLOWCTRL = '1' generate
- SCTRL : trb_net16_gbe_response_constructor_SCTRL
- generic map(STAT_ADDRESS_BASE => 8,
- SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
- )
- port map(
- CLK => CLK,
- RESET => RESET,
-
- -- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
- PS_RESPONSE_READY_OUT => resp_ready(2),
- PS_BUSY_OUT => busy(2),
- PS_SELECTED_IN => selected(2),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
- TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
- TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
- TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
- TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
- TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
- TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
- STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
- STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(2),
- STAT_DATA_ACK_IN => stat_ack(2),
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64),
- -- END OF INTERFACE
-
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
- CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
- CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
- MAKE_RESET_OUT => MAKE_RESET_OUT,
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32),
- DATA_HIST_OUT => SCTRL_HIST_OUT
- );
- end generate sctrl_gen;
-
- no_sctrl_gen : if INCLUDE_SLOWCTRL = '0' generate
- resp_ready(2) <= '0';
- busy(2) <= '0';
- MAKE_RESET_OUT <= '0';
-
- GSC_INIT_DATAREADY_OUT <= '0';
- GSC_INIT_DATA_OUT <= (others => '0');
- GSC_INIT_PACKET_NUM_OUT <= (others => '0');
- GSC_REPLY_READ_OUT <= '1';
-
- end generate no_sctrl_gen;
-
- trbnet_gen : if INCLUDE_READOUT = '1' generate
- TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
- generic map(
- RX_PATH_ENABLE => RX_PATH_ENABLE,
- DO_SIMULATION => DO_SIMULATION,
- READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE
- )
- port map(
- CLK => CLK,
- RESET => RESET,
-
- -- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
- PS_RESPONSE_READY_OUT => resp_ready(3),
- PS_BUSY_OUT => busy(3),
- PS_SELECTED_IN => selected(3),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
- TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
- TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
- TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
- TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
- TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
- TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
- TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
- STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
- STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(3),
- STAT_DATA_ACK_IN => stat_ack(3),
- DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
- -- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
- CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
- CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
- CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
- CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
- CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
- CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
- CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
- CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
- CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
- CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
- CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
- CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
- MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
- MONITOR_SELECT_DROP_IN_OUT => open,
- DATA_HIST_OUT => DATA_HIST_OUT
- );
- end generate trbnet_gen;
-
- no_readout_gen : if INCLUDE_READOUT = '0' generate
- resp_ready(3) <= '0';
- busy(3) <= '0';
- CTS_DATA_OUT <= (others => '0');
- CTS_DATAREADY_OUT <= '0';
- CTS_READOUT_FINISHED_OUT <= '0';
- CTS_LENGTH_OUT <= (others => '0');
- CTS_ERROR_PATTERN_OUT <= (others => '0');
- FEE_READ_OUT <= '0';
- end generate no_readout_gen;
-
-
- fwd_gen : if INCLUDE_FWD = '1' generate
-
- Forward : entity work.trb_net16_gbe_response_constructor_Forward
- port map(
- CLK => CLK,
- RESET => RESET,
-
- ---- INTERFACE
- MY_MAC_IN => MY_MAC_IN,
- MY_IP_IN => my_ip,
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(5),
- PS_RESPONSE_READY_OUT => resp_ready(5),
- PS_BUSY_OUT => busy(5),
- PS_SELECTED_IN => selected(5),
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(6 * 9 - 1 downto 5 * 9),
- TC_FRAME_SIZE_OUT => tc_size(6 * 16 - 1 downto 5 * 16),
- TC_FRAME_TYPE_OUT => tc_type(6 * 16 - 1 downto 5 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(6 * 8 - 1 downto 5 * 8),
- TC_IDENT_OUT => tc_ident(6 * 16 - 1 downto 5 * 16),
- TC_DEST_MAC_OUT => tc_mac(6 * 48 - 1 downto 5 * 48),
- TC_DEST_IP_OUT => tc_ip(6 * 32 - 1 downto 5 * 32),
- TC_DEST_UDP_OUT => tc_udp(6 * 16 - 1 downto 5 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(6 * 48 - 1 downto 5 * 48),
- TC_SRC_IP_OUT => tc_src_ip(6 * 32 - 1 downto 5 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(6 * 16 - 1 downto 5 * 16),
- RECEIVED_FRAMES_OUT => open,
- SENT_FRAMES_OUT => open,
-
- FWD_DST_MAC_IN => FWD_DST_MAC_IN,
- FWD_DST_IP_IN => FWD_DST_IP_IN,
- FWD_DST_UDP_IN => FWD_DST_UDP_IN,
- FWD_DATA_IN => FWD_DATA_IN,
- FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
- FWD_SOP_IN => FWD_SOP_IN,
- FWD_EOP_IN => FWD_EOP_IN,
- FWD_READY_OUT => FWD_READY_OUT,
- FWD_FULL_OUT => FWD_FULL_OUT,
+ zeros <= (others => '0');
+ MY_IP_OUT <= my_ip;
+
+ arp_gen : if INCLUDE_ARP = '1' generate
+ -- protocol Nr. 1 ARP
+ ARP : trb_net16_gbe_response_constructor_ARP
+ generic map(STAT_ADDRESS_BASE => 6
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ -- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0),
+ PS_RESPONSE_READY_OUT => resp_ready(0),
+ PS_BUSY_OUT => busy(0),
+ PS_SELECTED_IN => selected(0),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8),
+ TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16),
+ TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48),
+ TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32),
+ TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16),
+ STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
+ STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(0),
+ STAT_DATA_ACK_IN => stat_ack(0),
+ RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
+ SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
+ DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(1 * 64 - 1 downto 0 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+ -- END OF INTERFACE
+ );
+ end generate arp_gen;
+
+ no_arp_gen : if INCLUDE_ARP = '0' generate
+ resp_ready(0) <= '0';
+ busy(0) <= '0';
+ end generate no_arp_gen;
+
+ dhcp_gen : if INCLUDE_DHCP = '1' generate
+ -- protocol No. 2 DHCP
+ DHCP : trb_net16_gbe_response_constructor_DHCP
+ generic map(
+ STAT_ADDRESS_BASE => 0,
+ DO_SIMULATION => DO_SIMULATION
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET_FOR_DHCP, --RESET,
+
+ -- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1),
+ PS_RESPONSE_READY_OUT => resp_ready(1),
+ PS_BUSY_OUT => busy(1),
+ PS_SELECTED_IN => selected(1),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8),
+ TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16),
+ TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48),
+ TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32),
+ TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16),
+ STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
+ STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(1),
+ STAT_DATA_ACK_IN => stat_ack(1),
+ RECEIVED_FRAMES_OUT => open, --RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
+ SENT_FRAMES_OUT => open, --SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
+ -- END OF INTERFACE
+
+ MY_IP_OUT => my_ip,
+ DHCP_START_IN => DHCP_START_IN,
+ DHCP_DONE_OUT => DHCP_DONE_OUT,
+ DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+ );
+ end generate dhcp_gen;
+
+ no_dhcp_gen : if INCLUDE_DHCP = '0' generate
+ resp_ready(1) <= '0';
+ busy(1) <= '0';
+ end generate no_dhcp_gen;
+
+ ping_gen : if INCLUDE_PING = '1' generate
+ --protocol No. 3 Ping
+ Ping : entity work.trb_net16_gbe_response_constructor_KillPing
+ generic map(STAT_ADDRESS_BASE => 3
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ ---- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => ISSUE_REBOOT_OUT,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
+ PS_RESPONSE_READY_OUT => resp_ready(4),
+ PS_BUSY_OUT => busy(4),
+ PS_SELECTED_IN => selected(4),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
+ TC_IDENT_OUT => tc_ident(5 * 16 - 1 downto 4 * 16),
+ TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
+ TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
+ TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
+ STAT_DATA_OUT => open,
+ STAT_ADDR_OUT => open,
+ STAT_DATA_RDY_OUT => open,
+ STAT_DATA_ACK_IN => '0',
+ RECEIVED_FRAMES_OUT => open,
+ SENT_FRAMES_OUT => open,
+ DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(5 * 64 - 1 downto 4 * 64)
+ -- END OF INTERFACE
+ );
+ end generate ping_gen;
+
+ no_ping_gen : if INCLUDE_PING = '0' generate
+ resp_ready(4) <= '0';
+ busy(4) <= '0';
+ end generate no_ping_gen;
+
+ sctrl_gen : if INCLUDE_SLOWCTRL = '1' generate
+ SCTRL : trb_net16_gbe_response_constructor_SCTRL
+ generic map(STAT_ADDRESS_BASE => 8,
+ SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ -- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
+ PS_RESPONSE_READY_OUT => resp_ready(2),
+ PS_BUSY_OUT => busy(2),
+ PS_SELECTED_IN => selected(2),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
+ TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
+ TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
+ TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
+ TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
+ STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
+ STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(2),
+ STAT_DATA_ACK_IN => stat_ack(2),
+ DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(3 * 64 - 1 downto 2 * 64),
+ -- END OF INTERFACE
+
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+ CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN,
+ CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
+ MAKE_RESET_OUT => MAKE_RESET_OUT,
+ MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(3 * 32 - 1 downto 2 * 32),
+ MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
+ MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(3 * 32 - 1 downto 2 * 32),
+ MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(3 * 32 - 1 downto 2 * 32),
+ DATA_HIST_OUT => SCTRL_HIST_OUT
+ );
+ end generate sctrl_gen;
+
+ no_sctrl_gen : if INCLUDE_SLOWCTRL = '0' generate
+ resp_ready(2) <= '0';
+ busy(2) <= '0';
+ MAKE_RESET_OUT <= '0';
+
+ GSC_INIT_DATAREADY_OUT <= '0';
+ GSC_INIT_DATA_OUT <= (others => '0');
+ GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+ GSC_REPLY_READ_OUT <= '1';
+
+ end generate no_sctrl_gen;
+
+ trbnet_gen : if INCLUDE_READOUT = '1' generate
+ TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
+ generic map(
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ DO_SIMULATION => DO_SIMULATION,
+ READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ -- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
+ PS_RESPONSE_READY_OUT => resp_ready(3),
+ PS_BUSY_OUT => busy(3),
+ PS_SELECTED_IN => selected(3),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
+ TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
+ TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
+ TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
+ TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
+ STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
+ STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(3),
+ STAT_DATA_ACK_IN => stat_ack(3),
+ DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
+ -- END OF INTERFACE
+
+ -- CTS interface
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data payload interface
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- ip configurator
+ SLV_ADDR_IN => SLV_ADDR_IN,
+ SLV_READ_IN => SLV_READ_IN,
+ SLV_WRITE_IN => SLV_WRITE_IN,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT,
+ SLV_DATA_IN => SLV_DATA_IN,
+ SLV_DATA_OUT => SLV_DATA_OUT,
+ CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
+ CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
+ CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
+ CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN,
+ CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN,
+ CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN,
+ CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN,
+ CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN,
+ CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN,
+ CFG_MAX_SUB_IN => CFG_MAX_SUB_IN,
+ CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN,
+ CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN,
+ CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN,
+ CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
+ CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+ MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
+ MONITOR_SELECT_DROP_IN_OUT => open,
+ DATA_HIST_OUT => DATA_HIST_OUT
+ );
+ end generate trbnet_gen;
+
+ no_readout_gen : if INCLUDE_READOUT = '0' generate
+ resp_ready(3) <= '0';
+ busy(3) <= '0';
+ CTS_DATA_OUT <= (others => '0');
+ CTS_DATAREADY_OUT <= '0';
+ CTS_READOUT_FINISHED_OUT <= '0';
+ CTS_LENGTH_OUT <= (others => '0');
+ CTS_ERROR_PATTERN_OUT <= (others => '0');
+ FEE_READ_OUT <= '0';
+ end generate no_readout_gen;
+
+
+ fwd_gen : if INCLUDE_FWD = '1' generate
+
+ Forward : entity work.trb_net16_gbe_response_constructor_Forward
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ ---- INTERFACE
+ MY_MAC_IN => MY_MAC_IN,
+ MY_IP_IN => my_ip,
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(5),
+ PS_RESPONSE_READY_OUT => resp_ready(5),
+ PS_BUSY_OUT => busy(5),
+ PS_SELECTED_IN => selected(5),
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(6 * 9 - 1 downto 5 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(6 * 16 - 1 downto 5 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(6 * 16 - 1 downto 5 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(6 * 8 - 1 downto 5 * 8),
+ TC_IDENT_OUT => tc_ident(6 * 16 - 1 downto 5 * 16),
+ TC_DEST_MAC_OUT => tc_mac(6 * 48 - 1 downto 5 * 48),
+ TC_DEST_IP_OUT => tc_ip(6 * 32 - 1 downto 5 * 32),
+ TC_DEST_UDP_OUT => tc_udp(6 * 16 - 1 downto 5 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(6 * 48 - 1 downto 5 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(6 * 32 - 1 downto 5 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(6 * 16 - 1 downto 5 * 16),
+ RECEIVED_FRAMES_OUT => open,
+ SENT_FRAMES_OUT => open,
+
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN,
+ FWD_DST_IP_IN => FWD_DST_IP_IN,
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
- DEBUG_OUT => open
- -- END OF INTERFACE
- );
-
- end generate fwd_gen;
-
- no_fwd_gen : if INCLUDE_FWD = '0' generate
- resp_ready(5) <= '0';
- busy(5) <= '0';
- end generate no_fwd_gen;
-
- --stat_gen : if g_SIMULATE = 0 generate
- --Stat : trb_net16_gbe_response_constructor_Stat
- --generic map( STAT_ADDRESS_BASE => 10
- --)
- --port map (
- -- CLK => CLK,
- -- RESET => RESET,
- --
- ---- INTERFACE
- -- PS_DATA_IN => PS_DATA_IN,
- -- PS_WR_EN_IN => PS_WR_EN_IN,
- -- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
- -- PS_RESPONSE_READY_OUT => resp_ready(4),
- -- PS_BUSY_OUT => busy(4),
- -- PS_SELECTED_IN => selected(4),
- --
- -- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- -- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- -- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- -- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- -- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- -- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- --
- -- TC_WR_EN_OUT => TC_WR_EN_OUT,
- -- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
- -- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
- -- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
- -- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
- --
- -- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
- -- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
- -- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
- -- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
- -- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
- -- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
- --
- -- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16),
- -- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16),
- -- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16),
- --
- -- TC_BUSY_IN => TC_BUSY_IN,
- --
- -- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
- -- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
- -- STAT_DATA_RDY_OUT => stat_rdy(4),
- -- STAT_DATA_ACK_IN => stat_ack(4),
- --
- -- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
- -- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
- -- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32),
- --
- -- STAT_DATA_IN => stat_data,
- -- STAT_ADDR_IN => stat_addr,
- -- STAT_DATA_RDY_IN => stat_rdy,
- -- STAT_DATA_ACK_OUT => stat_ack
- --);
- --end generate;
-
- --***************
- -- DO NOT TOUCH, response selection logic
-
- --stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN;
- --stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN;
- --stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN;
- --STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS);
-
- --mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3));
-
- PS_BUSY_OUT <= busy;
-
- SELECT_MACHINE_PROC : process(RESET, CLK)
- begin
- if RESET = '1' then
- select_current_state <= IDLE;
- elsif rising_edge(CLK) then
- -- if (RESET = '1') then
- -- select_current_state <= IDLE;
- -- else
- select_current_state <= select_next_state;
- -- end if;
- end if;
- end process SELECT_MACHINE_PROC;
-
- SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy)
- begin
- select_state <= x"0";
-
- case (select_current_state) is
- when IDLE =>
- select_state <= x"1";
- if (MC_BUSY_IN = '0') then
- select_next_state <= LOOP_OVER;
- else
- select_next_state <= IDLE;
- end if;
-
- when LOOP_OVER =>
- select_state <= x"2";
- if (resp_ready /= zeros) then
- if (resp_ready(index) = '1') then
- select_next_state <= SELECT_ONE;
- elsif (index = c_MAX_PROTOCOLS) then
- select_next_state <= CLEANUP;
- else
- select_next_state <= LOOP_OVER;
- end if;
- else
- select_next_state <= CLEANUP;
- end if;
-
- when SELECT_ONE =>
- select_state <= x"3";
- if (MC_BUSY_IN = '1') then
- select_next_state <= PROCESS_REQUEST;
- else
- select_next_state <= SELECT_ONE;
- end if;
-
- when PROCESS_REQUEST =>
- select_state <= x"4";
- if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then
- select_next_state <= CLEANUP;
- else
- select_next_state <= PROCESS_REQUEST;
- end if;
-
- when CLEANUP =>
- select_state <= x"5";
- select_next_state <= IDLE;
-
- when others => select_next_state <= IDLE;
-
- end case;
-
- end process SELECT_MACHINE;
-
- INDEX_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (select_current_state = IDLE) then
- index <= 0;
- elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then
- index <= index + 1;
- else
- index <= index;
- end if;
- end if;
- end process INDEX_PROC;
-
- SELECTOR_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then
- TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9);
- TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16);
- TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16);
- TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48);
- TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32);
- TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16);
- TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48);
- TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32);
- TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16);
- TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8);
- TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16);
- if (select_current_state = SELECT_ONE) then
- PS_RESPONSE_READY_OUT <= '1';
- selected(index) <= '0';
- else
- PS_RESPONSE_READY_OUT <= '0';
- selected(index) <= '1';
- end if;
- else
- TC_DATA_OUT <= (others => '0');
- TC_FRAME_SIZE_OUT <= (others => '0');
- TC_FRAME_TYPE_OUT <= (others => '0');
- TC_DEST_MAC_OUT <= (others => '0');
- TC_DEST_IP_OUT <= (others => '0');
- TC_DEST_UDP_OUT <= (others => '0');
- TC_SRC_MAC_OUT <= (others => '0');
- TC_SRC_IP_OUT <= (others => '0');
- TC_SRC_UDP_OUT <= (others => '0');
- TC_IP_PROTOCOL_OUT <= (others => '0');
- TC_IDENT_OUT <= (others => '0');
- PS_RESPONSE_READY_OUT <= '0';
- selected <= (others => '0');
- end if;
- end if;
- end process SELECTOR_PROC;
-
- process(CLK)
- begin
- if rising_edge(CLK) then
- DEBUG_OUT(3 downto 0) <= select_state;
- DEBUG_OUT(11 downto 4) <= std_logic_vector(to_unsigned(index, 8));
- DEBUG_OUT(19 downto 12) <= "00" & resp_ready; -- 4:0
- DEBUG_OUT(27 downto 20) <= "00" & busy; -- 4:0
- DEBUG_OUT(63 downto 28) <= (others => '0');
- end if;
- end process;
+ DEBUG_OUT => open
+ -- END OF INTERFACE
+ );
+
+ end generate fwd_gen;
+
+ no_fwd_gen : if INCLUDE_FWD = '0' generate
+ resp_ready(5) <= '0';
+ busy(5) <= '0';
+ end generate no_fwd_gen;
+
+ PS_BUSY_OUT <= busy;
+
+ SELECT_MACHINE_PROC : process(RESET, CLK)
+ begin
+ if RESET = '1' then
+ select_current_state <= IDLE;
+ elsif rising_edge(CLK) then
+ -- if (RESET = '1') then
+ -- select_current_state <= IDLE;
+ -- else
+ select_current_state <= select_next_state;
+ -- end if;
+ end if;
+ end process SELECT_MACHINE_PROC;
+
+ SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy)
+ begin
+ select_state <= x"0";
+
+ case (select_current_state) is
+ when IDLE =>
+ select_state <= x"1";
+ if (MC_BUSY_IN = '0') then
+ select_next_state <= LOOP_OVER;
+ else
+ select_next_state <= IDLE;
+ end if;
+
+ when LOOP_OVER =>
+ select_state <= x"2";
+ if (resp_ready /= zeros) then
+ if (resp_ready(index) = '1') then
+ select_next_state <= SELECT_ONE;
+ elsif (index = c_MAX_PROTOCOLS) then
+ select_next_state <= CLEANUP;
+ else
+ select_next_state <= LOOP_OVER;
+ end if;
+ else
+ select_next_state <= CLEANUP;
+ end if;
+
+ when SELECT_ONE =>
+ select_state <= x"3";
+ if (MC_BUSY_IN = '1') then
+ select_next_state <= PROCESS_REQUEST;
+ else
+ select_next_state <= SELECT_ONE;
+ end if;
+
+ when PROCESS_REQUEST =>
+ select_state <= x"4";
+ if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then
+ select_next_state <= CLEANUP;
+ else
+ select_next_state <= PROCESS_REQUEST;
+ end if;
+
+ when CLEANUP =>
+ select_state <= x"5";
+ select_next_state <= IDLE;
+
+ when others => select_next_state <= IDLE;
+
+ end case;
+
+ end process SELECT_MACHINE;
+
+ INDEX_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (select_current_state = IDLE) then
+ index <= 0;
+ elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then
+ index <= index + 1;
+ else
+ index <= index;
+ end if;
+ end if;
+ end process INDEX_PROC;
+
+ SELECTOR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then
+ TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9);
+ TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16);
+ TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16);
+ TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48);
+ TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32);
+ TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16);
+ TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48);
+ TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32);
+ TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16);
+ TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8);
+ TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16);
+ if (select_current_state = SELECT_ONE) then
+ PS_RESPONSE_READY_OUT <= '1';
+ selected(index) <= '0';
+ else
+ PS_RESPONSE_READY_OUT <= '0';
+ selected(index) <= '1';
+ end if;
+ else
+ TC_DATA_OUT <= (others => '0');
+ TC_FRAME_SIZE_OUT <= (others => '0');
+ TC_FRAME_TYPE_OUT <= (others => '0');
+ TC_DEST_MAC_OUT <= (others => '0');
+ TC_DEST_IP_OUT <= (others => '0');
+ TC_DEST_UDP_OUT <= (others => '0');
+ TC_SRC_MAC_OUT <= (others => '0');
+ TC_SRC_IP_OUT <= (others => '0');
+ TC_SRC_UDP_OUT <= (others => '0');
+ TC_IP_PROTOCOL_OUT <= (others => '0');
+ TC_IDENT_OUT <= (others => '0');
+ PS_RESPONSE_READY_OUT <= '0';
+ selected <= (others => '0');
+ end if;
+ end if;
+ end process SELECTOR_PROC;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ DEBUG_OUT(3 downto 0) <= select_state;
+ DEBUG_OUT(11 downto 4) <= std_logic_vector(to_unsigned(index, 8));
+ DEBUG_OUT(19 downto 12) <= "00" & resp_ready; -- 4:0
+ DEBUG_OUT(27 downto 20) <= "00" & busy; -- 4:0
+ DEBUG_OUT(63 downto 28) <= (others => '0');
+ end if;
+ end process;
end trb_net16_gbe_protocol_selector;
use work.trb_net_gbe_components.all;
--********
--- Response Constructor which forwards received frame back ceating a loopback
+-- Response Constructor which forwards received frame back creating a loopback
--
entity trb_net16_gbe_response_constructor_Forward is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- MY_MAC_IN : in std_logic_vector(47 downto 0);
- MY_IP_IN : in std_logic_vector(31 downto 0);
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
- FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
- FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
- FWD_DATA_IN : in std_logic_vector(7 downto 0);
- FWD_DATA_VALID_IN : in std_logic;
- FWD_SOP_IN : in std_logic;
- FWD_EOP_IN : in std_logic;
- FWD_READY_OUT : out std_logic;
- FWD_FULL_OUT : out std_logic;
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+ -- INTERFACE
+ MY_MAC_IN : in std_logic_vector(47 downto 0);
+ MY_IP_IN : in std_logic_vector(31 downto 0);
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ -- END OF INTERFACE
+
+ FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
+ FWD_DST_IP_IN : in std_logic_vector(31 downto 0);
+ FWD_DST_UDP_IN : in std_logic_vector(15 downto 0);
+ FWD_DATA_IN : in std_logic_vector(7 downto 0);
+ FWD_DATA_VALID_IN : in std_logic;
+ FWD_SOP_IN : in std_logic;
+ FWD_EOP_IN : in std_logic;
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+
+ -- debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
end trb_net16_gbe_response_constructor_Forward;
DISSECT_MACHINE_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ dissect_current_state <= IDLE;
+ else
+ dissect_current_state <= dissect_next_state;
+ end if;
+ end if;
end process DISSECT_MACHINE_PROC;
DISSECT_MACHINE : process(dissect_current_state, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN)
begin
- case dissect_current_state is
-
- when IDLE =>
- state <= x"1";
- if (FWD_SOP_IN = '1') then
- dissect_next_state <= SAVE;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when SAVE =>
- state <= x"2";
- if (FWD_EOP_IN = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= SAVE;
- end if;
-
- when WAIT_FOR_LOAD =>
- state <= x"3";
- if (PS_SELECTED_IN = '0') then
- dissect_next_state <= LOAD;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- state <= x"4";
- if (ff_q(8) = '1') and (ff_rd_lock = '0') then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD;
- end if;
-
- when CLEANUP =>
- state <= x"5";
- dissect_next_state <= IDLE;
-
- end case;
+ case dissect_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if (FWD_SOP_IN = '1') then
+ dissect_next_state <= SAVE;
+ else
+ dissect_next_state <= IDLE;
+ end if;
+
+ when SAVE =>
+ state <= x"2";
+ if (FWD_EOP_IN = '1') then
+ dissect_next_state <= WAIT_FOR_LOAD;
+ else
+ dissect_next_state <= SAVE;
+ end if;
+
+ when WAIT_FOR_LOAD =>
+ state <= x"3";
+ if (PS_SELECTED_IN = '0') then
+ dissect_next_state <= LOAD;
+ else
+ dissect_next_state <= WAIT_FOR_LOAD;
+ end if;
+
+ when LOAD =>
+ state <= x"4";
+ if (ff_q(8) = '1') and (ff_rd_lock = '0') then
+ dissect_next_state <= CLEANUP;
+ else
+ dissect_next_state <= LOAD;
+ end if;
+
+ when CLEANUP =>
+ state <= x"5";
+ dissect_next_state <= IDLE;
+
+ end case;
end process DISSECT_MACHINE;
---PS_BUSY_OUT <= '1' when ff_wr_en = '1' else '0';
PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
---ff_wr_en <= '1' when (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') else '0';
ff_wr_en <= '1' when (FWD_DATA_VALID_IN = '1') else '0';
local_eop <= '1' when (dissect_current_state = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0';
FF_RD_LOCK_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- ff_rd_lock <= '1';
- elsif (dissect_current_state = LOAD and ff_rd_en = '1') then
- ff_rd_lock <= '0';
- else
- ff_rd_lock <= '1';
- end if;
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ ff_rd_lock <= '1';
+ elsif (dissect_current_state = LOAD and ff_rd_en = '1') then
+ ff_rd_lock <= '0';
+ else
+ ff_rd_lock <= '1';
+ end if;
+ end if;
end process FF_RD_LOCK_PROC;
FRAME_FIFO: fifo_4096x9
port map(
- Data(7 downto 0) => FWD_DATA_IN,
- Data(8) => local_eop,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => ff_wr_en,
- RdEn => ff_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => ff_q,
- Empty => ff_empty,
- Full => ff_full
+ Data(7 downto 0) => FWD_DATA_IN,
+ Data(8) => local_eop,
+ WrClock => CLK,
+ RdClock => CLK,
+ WrEn => ff_wr_en,
+ RdEn => ff_rd_en,
+ Reset => RESET,
+ RPReset => RESET,
+ Q => ff_q,
+ Empty => ff_empty,
+ Full => ff_full
);
ff_rd_en <= '1' when (TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') else '0';
RESP_BYTES_CTR_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) then
- resp_bytes_ctr <= (others => '0');
- elsif (dissect_current_state = SAVE and FWD_DATA_VALID_IN = '1') then
- resp_bytes_ctr <= resp_bytes_ctr + x"1";
- end if;
-
- FWD_FULL_OUT <= ff_full;
-
- if (dissect_current_state = IDLE) then
- FWD_READY_OUT <= '1';
- else
- FWD_READY_OUT <= '0';
- end if;
-
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') or (dissect_current_state = IDLE) then
+ resp_bytes_ctr <= (others => '0');
+ elsif (dissect_current_state = SAVE and FWD_DATA_VALID_IN = '1') then
+ resp_bytes_ctr <= resp_bytes_ctr + x"1";
+ end if;
+
+ FWD_FULL_OUT <= ff_full;
+
+ if (dissect_current_state = IDLE) then
+ FWD_READY_OUT <= '1';
+ else
+ FWD_READY_OUT <= '0';
+ end if;
+
+ end if;
end process RESP_BYTES_CTR_PROC;
REC_FRAMES_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- rec_frames <= (others => '0');
- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- rec_frames <= rec_frames + x"1";
- end if;
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
end process REC_FRAMES_PROC;
SENT_FRAMES_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '0') then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ sent_frames <= (others => '0');
+ elsif (dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '0') then
+ sent_frames <= sent_frames + x"1";
+ end if;
+ end if;
end process SENT_FRAMES_PROC;
RECEIVED_FRAMES_OUT <= rec_frames;
jspc29 / trbnet.git / commitdiff