-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2014-01-22
+-- Last update: 2014-01-23
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
wr_header_fsm <= '1';
readout_fsm <= '1';
else -- the other triggers
- data_finished_fsm <= '1';
RD_NEXT <= SEND_TRIG_RELEASE_A;
+ data_finished_fsm <= '1';
end if;
elsif INVALID_TRG_IN = '1' then -- invalid trigger
RD_NEXT <= SEND_TRIG_RELEASE_A;
if DEBUG_MODE_EN_IN = '1' then -- send status after channel data
RD_NEXT <= SEND_STATUS;
else
- RD_NEXT <= WAIT_FOR_DATA_FINISHED; -- WAIT_FOR_LVL1_TRIG_A;
+ RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
end if;
else -- go to the next channel
fifo_nr_rd_fsm <= fifo_nr_rd + 1;
readout_fsm <= '1';
rd_fsm_debug_fsm <= x"4";
- when WAIT_FOR_DATA_FINISHED => -- wait until the end of the data transfer
- if finished_i = '1' then
- RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
- end if;
- wait_fsm <= '1';
- rd_fsm_debug_fsm <= x"5";
+ --when WAIT_FOR_DATA_FINISHED => -- wait until the end of the data transfer
+ -- if finished_i = '1' then
+ -- RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
+ -- end if;
+ -- wait_fsm <= '1';
+ -- rd_fsm_debug_fsm <= x"5";
when WAIT_FOR_LVL1_TRIG_A => -- wait for trigger data valid
if TRG_DATA_VALID_IN = '1' then
if SPURIOUS_TRG_IN = '1' then
wrong_readout_fsm <= '1';
end if;
- RD_NEXT <= SEND_TRIG_RELEASE_A;
- wait_fsm <= '1';
- rd_fsm_debug_fsm <= x"8";
+ RD_NEXT <= SEND_TRIG_RELEASE_A;
+ data_finished_fsm <= '1';
+ wait_fsm <= '1';
+ rd_fsm_debug_fsm <= x"8";
when SEND_STATUS =>
if stop_status_i = '1' then
if DEBUG_MODE_EN_IN = '1' then
RD_NEXT <= WAIT_FOR_LVL1_TRIG_A;
else
- RD_NEXT <= SEND_TRIG_RELEASE_A;
- end if;
- data_finished_fsm <= '1';
+ RD_NEXT <= SEND_TRIG_RELEASE_A;
+ data_finished_fsm <= '1';
+ end if;
else
wr_status_fsm <= '1';
end if;
DATA_OUT <= data_out_reg;
DATA_WRITE_OUT <= data_wr_reg;
finished_i <= (data_finished or wr_finished_2reg) when rising_edge(CLK_100);
- DATA_FINISHED_OUT <= finished_i;
+ DATA_FINISHED_OUT <= data_finished; --finished_i;
TRG_RELEASE_OUT <= trig_release_reg;
TRG_STATUSBIT_OUT <= (others => '0');
READOUT_DEBUG(3 downto 0) <= rd_fsm_debug;
-- Logic analyser
signal logic_anal_data_i : std_logic_vector(3*32-1 downto 0);
-- Hit signals
- signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+ signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
signal hit_latch : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
signal hit_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
signal hit_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
end process;
end generate GEN_Channel_Enable;
+ -- purpose: Calibration trigger for the reference channel
+ process (calibration_on, HIT_CALIBRATION) is
+ begin -- process
+ if calibration_on = '1' then
+ hit_in_i(0) <= HIT_CALIBRATION;
+ else
+ hit_in_i(0) <= REFERENCE_TIME;
+ end if;
+ end process;
+
CalibrationSwitch : process (CLK_READOUT)
begin
if rising_edge(CLK_READOUT) then
RESET_COUNTERS => reset_counters_i,
CLK_200 => CLK_TDC,
CLK_100 => CLK_READOUT,
- HIT_IN => REFERENCE_TIME,
+ HIT_IN => hit_in_i(0), --REFERENCE_TIME,
TRIGGER_WIN_END_TDC => trig_win_end_tdc,
TRIGGER_WIN_END_RDO => trig_win_end_rdo,
EPOCH_COUNTER_IN => epoch_cntr,