+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
--- Module Version: 5.5
---/home/soft/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_4kx18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -e
-
--- Wed Jun 26 14:33:30 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4kx18x9 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4kx18x9;
-
-architecture Structure of fifo_4kx18x9 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_12: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co5: std_logic;
- signal co4: std_logic;
- signal wcount_11: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6: std_logic;
- signal co5_1: std_logic;
- signal rcount_12: std_logic;
- signal mdout1_1_0: std_logic;
- signal mdout1_0_0: std_logic;
- signal mdout1_1_1: std_logic;
- signal mdout1_0_1: std_logic;
- signal mdout1_1_2: std_logic;
- signal mdout1_0_2: std_logic;
- signal mdout1_1_3: std_logic;
- signal mdout1_0_3: std_logic;
- signal mdout1_1_4: std_logic;
- signal mdout1_0_4: std_logic;
- signal mdout1_1_5: std_logic;
- signal mdout1_0_5: std_logic;
- signal mdout1_1_6: std_logic;
- signal mdout1_0_6: std_logic;
- signal mdout1_1_7: std_logic;
- signal mdout1_0_7: std_logic;
- signal rptr_11_ff: std_logic;
- signal mdout1_1_8: std_logic;
- signal mdout1_0_8: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r1: std_logic;
- signal wcount_r2: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r3: std_logic;
- signal wcount_r4: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r5: std_logic;
- signal wcount_r6: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r7: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r9: std_logic;
- signal wcount_r10: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w1: std_logic;
- signal rcount_w2: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w3: std_logic;
- signal rcount_w4: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w5: std_logic;
- signal rcount_w6: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w7: std_logic;
- signal rcount_w8: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w10: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w11: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_10: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component MUX21
- port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
- Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4kx18x9.lpc";
- attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is "";
- attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t25: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t24: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t23: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t22: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t21: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t20: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t19: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t18: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t17: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t16: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t15: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t14: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t13: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t12: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>w_gcount_r211,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>w_gcount_r27,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_1_0_0: DP16KC
- generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
- DATA_WIDTH_A=> 18)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
- DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
- DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
- DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
- ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
- ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
- ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
- CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
- CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
- CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_127: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_118: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_117: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_116: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_106: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_105: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_104: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_103: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_102: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_101: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_100: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_99: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_98: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_97: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_96: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_95: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_94: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_93: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_92: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_91: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_90: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_89: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_88: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_87: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_86: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_85: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_84: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_83: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_82: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_81: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_80: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_79: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_66: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_65: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_64: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_63: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_62: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_61: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_60: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_59: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_58: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_57: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_56: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_55: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_54: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_53: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_52: FD1P3DX
- port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo,
- Q=>rptr_11_ff);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>ircount_12, NC1=>open);
-
- mux_8: MUX21
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff,
- Z=>Q(0));
-
- mux_7: MUX21
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff,
- Z=>Q(1));
-
- mux_6: MUX21
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff,
- Z=>Q(2));
-
- mux_5: MUX21
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff,
- Z=>Q(3));
-
- mux_4: MUX21
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff,
- Z=>Q(4));
-
- mux_3: MUX21
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff,
- Z=>Q(5));
-
- mux_2: MUX21
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff,
- Z=>Q(6));
-
- mux_1: MUX21
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff,
- Z=>Q(7));
-
- mux_0: MUX21
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff,
- Z=>Q(8));
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>wcount_r0, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1,
- B1=>wcount_r2, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3,
- B1=>wcount_r4, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5,
- B1=>wcount_r6, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9,
- B1=>wcount_r10, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1,
- B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3,
- B1=>rcount_w4, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5,
- B1=>rcount_w6, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7,
- B1=>rcount_w8, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w10, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w11,
- B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4kx18x9 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:MUX21 use entity ecp3.MUX21(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Tue Apr 23 14:34:09 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_4kx8_ecp3 is
- port (
- Data: in std_logic_vector(7 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_4kx8_ecp3;
-
-architecture Structure of fifo_4kx8_ecp3 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_2_1: std_logic;
- signal w_g2b_xor_cluster_2: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal w_gdata_9: std_logic;
- signal w_gdata_10: std_logic;
- signal w_gdata_11: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal wptr_10: std_logic;
- signal wptr_11: std_logic;
- signal wptr_12: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal r_gdata_11: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal rptr_12: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal w_gcount_10: std_logic;
- signal w_gcount_11: std_logic;
- signal w_gcount_12: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal r_gcount_12: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal w_gcount_r210: std_logic;
- signal w_gcount_r10: std_logic;
- signal w_gcount_r211: std_logic;
- signal w_gcount_r11: std_logic;
- signal w_gcount_r212: std_logic;
- signal w_gcount_r12: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal r_gcount_w212: std_logic;
- signal r_gcount_w12: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co3: std_logic;
- signal iwcount_10: std_logic;
- signal iwcount_11: std_logic;
- signal co4: std_logic;
- signal iwcount_12: std_logic;
- signal co6: std_logic;
- signal wcount_12: std_logic;
- signal co5: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co4_1: std_logic;
- signal ircount_12: std_logic;
- signal co6_1: std_logic;
- signal rcount_12: std_logic;
- signal co5_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r6: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r10: std_logic;
- signal wcount_r11: std_logic;
- signal rcount_10: std_logic;
- signal rcount_11: std_logic;
- signal co5_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co4_3: std_logic;
- signal rcount_w10: std_logic;
- signal rcount_w11: std_logic;
- signal wcount_10: std_logic;
- signal wcount_11: std_logic;
- signal co5_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component DP16KC
- generic (GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx8_ecp3.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
- attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_4kx8_ecp3.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
- attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t26: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t25: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t24: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t23: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t22: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t21: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t20: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t19: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t18: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t17: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t16: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t15: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t14: XOR2
- port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
-
- XOR2_t13: XOR2
- port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
-
- XOR2_t12: XOR2
- port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
-
- XOR2_t11: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t10: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t9: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t8: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t7: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t6: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t5: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t4: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t3: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t2: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t1: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- XOR2_t0: XOR2
- port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11);
-
- LUT4_33: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
- AD1=>w_gcount_r211, AD0=>w_gcount_r212,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_32: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>w_gcount_r28,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_31: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24,
- DO0=>w_g2b_xor_cluster_2);
-
- LUT4_30: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r11);
-
- LUT4_29: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
- AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
-
- LUT4_28: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
- AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>scuba_vlo,
- DO0=>w_g2b_xor_cluster_2_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>r_gcount_w212,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_gcount_w28,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w11);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211,
- AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_1: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- pdp_ram_0_1_0: DP16KC
- generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
- WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 4)
- port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
- DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
- ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
- ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
- OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1,
- ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5,
- ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9,
- ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_131: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_130: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_129: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_128: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_127: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_126: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_125: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_124: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_123: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_122: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_121: FD1P3DX
- port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_10);
-
- FF_120: FD1P3DX
- port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_11);
-
- FF_119: FD1P3DX
- port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_12);
-
- FF_118: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_117: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_116: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_115: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_114: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_113: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_112: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_111: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_110: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_109: FD1P3DX
- port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_108: FD1P3DX
- port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_10);
-
- FF_107: FD1P3DX
- port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_11);
-
- FF_106: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_12);
-
- FF_105: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_104: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_103: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_102: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_101: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_100: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_99: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_98: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_97: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_96: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_95: FD1P3DX
- port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_10);
-
- FF_94: FD1P3DX
- port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_11);
-
- FF_93: FD1P3DX
- port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_12);
-
- FF_92: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_91: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_90: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_89: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_88: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_87: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_86: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_85: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_84: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_83: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_82: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_81: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_80: FD1P3DX
- port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_12);
-
- FF_79: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_78: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_77: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_76: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_75: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_74: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_73: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_72: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_71: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_70: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_67: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_12);
-
- FF_66: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_65: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_64: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_63: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_62: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_61: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_60: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_59: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_58: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_57: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_56: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_55: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_54: FD1P3DX
- port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_12);
-
- FF_53: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_52: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_51: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_50: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_49: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_48: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_47: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_46: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r10);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r11);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r12);
-
- FF_40: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_39: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_38: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_37: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_36: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12);
-
- FF_27: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_26: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_25: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_24: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r210);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r211);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r212);
-
- FF_14: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w212);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- w_gctr_5: CU2
- port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
- NC0=>iwcount_10, NC1=>iwcount_11);
-
- w_gctr_6: CU2
- port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
- NC0=>iwcount_12, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1,
- NC0=>ircount_10, NC1=>ircount_11);
-
- r_gctr_6: CU2
- port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1,
- NC0=>ircount_12, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8,
- B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10,
- B1=>wcount_r11, CI=>co4_2, GE=>co5_2);
-
- empty_cmp_6: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8,
- B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3);
-
- full_cmp_5: AGEB2
- port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10,
- B1=>rcount_w11, CI=>co4_3, GE=>co5_3);
-
- full_cmp_6: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_4kx8_ecp3 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 8 -no_enable -pe -1 -pf -1 -e
-
--- Tue Jun 11 11:02:45 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_512x32x8 is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(7 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_512x32x8;
-
-architecture Structure of fifo_512x32x8 is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal rcount_w1: std_logic;
- signal r_g2b_xor_cluster_2_1: std_logic;
- signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_2: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal r_gdata_9: std_logic;
- signal r_gdata_10: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal rptr_10: std_logic;
- signal rptr_11: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal r_gcount_10: std_logic;
- signal r_gcount_11: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal r_gcount_w210: std_logic;
- signal r_gcount_w10: std_logic;
- signal r_gcount_w211: std_logic;
- signal r_gcount_w11: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co3_1: std_logic;
- signal ircount_10: std_logic;
- signal ircount_11: std_logic;
- signal co5: std_logic;
- signal rcount_11: std_logic;
- signal co4_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co4_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_10: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w6: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w9: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w10: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_512x32x8.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t22: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t21: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t20: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t19: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t18: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t17: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t16: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t15: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t14: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t13: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t12: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t11: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t10: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t9: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t8: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t7: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t6: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t5: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t4: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t3: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t2: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- XOR2_t1: XOR2
- port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
-
- XOR2_t0: XOR2
- port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10);
-
- LUT4_27: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_26: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_25: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_24: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
- AD1=>r_gcount_w210, AD0=>r_gcount_w211,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>r_gcount_w27,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23,
- DO0=>r_g2b_xor_cluster_2);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w10);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210,
- AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>scuba_vlo,
- DO0=>r_g2b_xor_cluster_2_1);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w211,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>scuba_vlo, DI9=>Data(8), DI10=>Data(9), DI11=>Data(10),
- DI12=>Data(11), DI13=>Data(12), DI14=>Data(13),
- DI15=>Data(14), DI16=>Data(15), DI17=>scuba_vlo,
- DI18=>Data(16), DI19=>Data(17), DI20=>Data(18),
- DI21=>Data(19), DI22=>Data(20), DI23=>Data(21),
- DI24=>Data(22), DI25=>Data(23), DI26=>scuba_vlo,
- DI27=>Data(24), DI28=>Data(25), DI29=>Data(26),
- DI30=>Data(27), DI31=>Data(28), DI32=>Data(29),
- DI33=>Data(30), DI34=>Data(31), DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
- ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
- ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
- ADR13=>rptr_10, CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo,
- CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0),
- DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
- DO6=>Q(6), DO7=>Q(7), DO8=>open, DO9=>open, DO10=>open,
- DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
- DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
- DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
- DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
- DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
-
- FF_111: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_110: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_109: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_108: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_107: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_106: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_105: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_104: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_103: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_102: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_101: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_100: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_99: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_98: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_97: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_96: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_95: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_94: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_93: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_92: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_91: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_90: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_89: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_88: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_87: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_86: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_85: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_84: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_83: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_81: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_80: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_79: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_78: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_77: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_76: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_75: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_74: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_73: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_72: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_71: FD1P3DX
- port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_10);
-
- FF_70: FD1P3DX
- port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_11);
-
- FF_69: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_68: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_67: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_66: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_65: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_64: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_63: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_62: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_10);
-
- FF_58: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_11);
-
- FF_57: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_56: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_55: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_54: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_53: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_52: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_51: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_50: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_49: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_48: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_47: FD1P3DX
- port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_10);
-
- FF_46: FD1P3DX
- port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_11);
-
- FF_45: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_44: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_43: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_42: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_35: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_34: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_33: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_32: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11);
-
- FF_23: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_22: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_13: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_12: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w210);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst,
- Q=>r_gcount_w211);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- r_gctr_5: CU2
- port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5,
- NC0=>ircount_10, NC1=>ircount_11);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r0,
- B1=>wcount_r1, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co3_2, GE=>co4_2);
-
- empty_cmp_5: AGEB2
- port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w2,
- B1=>rcount_w3, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w6,
- B1=>rcount_w7, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w9, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w10,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_512x32x8 is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
-- Loop the transmissions
-------------------------------------------------------------------------------
trigger_counter := x"4710";
- trigger_loop := 0;
+ trigger_loop := 1;
wait until rising_edge(test_clk);
--test_data_len := INTEGER(TRUNC(rand * 800.0)) + 1;
--test_data_len := 9685;
- test_data_len := 29; -- + (1 - J) * 200;
+ test_data_len := 200;
-- calculate the needed variables
test_loop_len := 2*(test_data_len - 1) + 1;
--attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group";
-component tsmac35 --tsmac36 --tsmac35
+component tsmac35
port(
--------------- clock and reset port declarations ------------------
hclk : in std_logic;
);
end component;
+component slv_mac_memory is
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ BUSY_IN : in std_logic;
+ -- Slave bus
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- I/O to the backend
+ MEM_CLK_IN : in std_logic;
+ MEM_ADDR_IN : in std_logic_vector(7 downto 0);
+ MEM_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- Status lines
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG
+);
+end component;
+
component fifo_4096x9 is
port(
Data : in std_logic_vector(8 downto 0);
signal tc_pc_h_ready : std_logic;
signal mc_ctrl_frame_req : std_logic;
signal mc_data : std_logic_vector(8 downto 0);
-signal mc_wr_en : std_logic;
+signal mc_rd_en : std_logic;
signal fc_wr_en : std_logic;
signal fc_data : std_logic_vector(7 downto 0);
signal fc_ip_size : std_logic_vector(15 downto 0);
attribute syn_keep of timeout_noticed : signal is true;
attribute syn_preserve of timeout_noticed : signal is true;
-signal dummy_size : std_logic_vector(15 downto 0);
-signal dummy_pause : std_logic_vector(31 downto 0);
-
-signal make_reset : std_logic;
-signal idle_too_long : std_logic;
-
-signal tc_data_not_valid : std_logic;
-
-signal mc_fc_h_ready, mc_fc_ready, mc_fc_wr_en : std_logic;
-signal mc_ident, mc_size_left : std_logic_vector(15 downto 0);
-
-
begin
stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
-- gk 23.04.10
-LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
-LED_AN_DONE_N_OUT <= '0'; --not link_ok; --not pcs_an_complete;
+LED_PACKET_SENT_OUT <= timeout_noticed; --pc_ready;
+LED_AN_DONE_N_OUT <= not link_ok; --not pcs_an_complete;
fc_ihl_version <= x"45";
fc_tos <= x"10";
fc_ttl <= x"ff";
+
MAIN_CONTROL : trb_net16_gbe_main_control
port map(
CLK => CLK,
RESET => RESET,
MC_LINK_OK_OUT => link_ok,
- MC_RESET_LINK_IN => '0',
- MC_IDLE_TOO_LONG_OUT => idle_too_long,
+ MC_RESET_LINK_IN => MR_RESTART_IN,
-- signals to/from receive controller
RC_FRAME_WAITING_IN => rc_frame_ready,
-- signals to/from transmit controller
TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
+ TC_TRANSMIT_DATA_OUT => mc_transmit_data,
TC_DATA_OUT => mc_data,
- TC_RD_EN_IN => mc_wr_en,
- --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
+ TC_RD_EN_IN => mc_rd_en,
TC_FRAME_SIZE_OUT => mc_frame_size,
TC_FRAME_TYPE_OUT => mc_type,
TC_IP_PROTOCOL_OUT => mc_ip_proto,
- TC_IDENT_OUT => mc_ident,
TC_DEST_MAC_OUT => mc_dest_mac,
TC_DEST_IP_OUT => mc_dest_ip,
TC_SRC_MAC_OUT => mc_src_mac,
TC_SRC_IP_OUT => mc_src_ip,
TC_SRC_UDP_OUT => mc_src_udp,
+
+ TC_IP_SIZE_OUT => mc_ip_size,
+ TC_UDP_SIZE_OUT => mc_udp_size,
+ TC_FLAGS_OFFSET_OUT => mc_flags,
+
+ TC_BUSY_IN => mc_busy,
TC_TRANSMIT_DONE_IN => mc_transmit_done,
+ -- signals to/from packet constructor
+ PC_READY_IN => pc_ready,
+ PC_TRANSMIT_ON_IN => pc_transmit_on,
+ PC_SOD_IN => tc_sod,
+
-- signals to/from sgmii/gbe pcs_an_complete
PCS_AN_COMPLETE_IN => pcs_an_complete,
GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
GSC_BUSY_IN => GSC_BUSY_IN,
- MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT,
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => use_gbe,
- CFG_IPU_ENABLE_IN => use_trbnet,
- CFG_MULT_ENABLE_IN => use_multievents,
+ MAKE_RESET_OUT => MAKE_RESET_OUT,
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT => mac_haddr,
DEBUG_OUT => dbg_mc
);
-
- MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
-TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
+TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
port map(
CLK => CLK,
RESET => RESET,
+-- signals to/from packet constructor
+ PC_READY_IN => pc_ready,
+ PC_DATA_IN => tc_data,
+ PC_WR_EN_IN => tc_wr_en,
+ PC_IP_SIZE_IN => tc_ip_size,
+ PC_UDP_SIZE_IN => tc_udp_size,
+ PC_FLAGS_OFFSET_IN => tc_flags_offset,
+ PC_SOD_IN => tc_sod,
+ PC_EOD_IN => tc_eod,
+ PC_FC_READY_OUT => tc_pc_ready,
+ PC_FC_H_READY_OUT => tc_pc_h_ready,
+ PC_TRANSMIT_ON_IN => pc_transmit_on,
+
+ -- signals from ip_configurator used by packet constructor
+ IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
+ IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
+ IC_DEST_UDP_PORT_IN => ic_dest_udp,
+ IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
+ IC_SRC_IP_ADDRESS_IN => ic_src_ip,
+ IC_SRC_UDP_PORT_IN => ic_src_udp,
+
-- signal to/from main controller
- TC_DATAREADY_IN => mc_transmit_ctrl,
- TC_RD_EN_OUT => mc_wr_en,
- TC_DATA_IN => mc_data(7 downto 0),
- TC_FRAME_SIZE_IN => mc_frame_size,
- TC_FRAME_TYPE_IN => mc_type,
- TC_IP_PROTOCOL_IN => mc_ip_proto,
- TC_DEST_MAC_IN => mc_dest_mac,
- TC_DEST_IP_IN => mc_dest_ip,
- TC_DEST_UDP_IN => mc_dest_udp,
- TC_SRC_MAC_IN => mc_src_mac,
- TC_SRC_IP_IN => mc_src_ip,
- TC_SRC_UDP_IN => mc_src_udp,
- TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
- TC_IDENT_IN => mc_ident,
+ MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
+ MC_TRANSMIT_DATA_IN => mc_transmit_data,
+ MC_DATA_IN => mc_data,
+ MC_RD_EN_OUT => mc_rd_en,
+ MC_FRAME_SIZE_IN => mc_frame_size,
+ MC_FRAME_TYPE_IN => mc_type,
+ MC_IP_PROTOCOL_IN => mc_ip_proto,
+
+ MC_DEST_MAC_IN => mc_dest_mac,
+ MC_DEST_IP_IN => mc_dest_ip,
+ MC_DEST_UDP_IN => mc_dest_udp,
+ MC_SRC_MAC_IN => mc_src_mac,
+ MC_SRC_IP_IN => mc_src_ip,
+ MC_SRC_UDP_IN => mc_src_udp,
+
+ MC_IP_SIZE_IN => mc_ip_size,
+ MC_UDP_SIZE_IN => mc_udp_size,
+ MC_FLAGS_OFFSET_IN => mc_flags,
+
+ MC_BUSY_OUT => mc_busy,
+ MC_TRANSMIT_DONE_OUT => mc_transmit_done,
-- signal to/from frame constructor
FC_DATA_OUT => fc_data,
DBG_SELECT_SENT_IN => dbg_select_sent,
DBG_SELECT_PROTOS_IN => dbg_select_protos,
- SCTRL_DUMMY_SIZE_OUT => dummy_size,
- SCTRL_DUMMY_PAUSE_OUT => dummy_pause,
-
DBG_FIFO_Q_IN => dbg_q
--DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
GBE_MAX_PACKET_OUT => max_packet,
GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
GBE_MAX_FRAME_OUT => pc_max_frame_size,
- GBE_USE_GBE_OUT => open, --use_gbe,
+ GBE_USE_GBE_OUT => use_gbe,
GBE_USE_TRBNET_OUT => use_trbnet,
GBE_USE_MULTIEVENTS_OUT => use_multievents,
GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
MONITOR_RX_FRAMES_IN => rc_frames_rec_ctr,
MONITOR_RX_BYTES_IN => rc_bytes_rec,
MONITOR_RX_BYTES_R_IN => rc_debug(31 downto 0),
-
- SCTRL_DUMMY_SIZE_OUT => dummy_size,
- SCTRL_DUMMY_PAUSE_OUT => dummy_pause,
-
-- gk 01.06.10
DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
DBG_FC2_IN => dbg_fc2,
DBG_FT1_IN => dbg_ft1,
DBG_FT2_IN => dbg_ft(31 downto 0),
- DBG_FR_IN => dbg_fr(63 downto 0),
+ DBG_FR_IN => dbg_fr,
DBG_RC_IN => dbg_rc,
DBG_MC_IN => dbg_mc,
DBG_TC_IN => dbg_tc(31 downto 0),
--DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
);
-use_gbe <= '1';
-
allow_rx <= '1';
allow_large <= '0';
end generate;
+
+-- IP configurator: allows IP config to change for each event builder
+THE_IP_CONFIGURATOR: ip_configurator
+port map(
+ CLK => CLK,
+ RESET => RESET,
+ -- configuration interface
+ START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10
+ BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10
+ CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10
+ MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10
+ MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10
+ MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10
+ -- information for IP cores
+ DEST_MAC_OUT => ic_dest_mac,
+ DEST_IP_OUT => ic_dest_ip,
+ DEST_UDP_OUT => ic_dest_udp,
+ SRC_MAC_OUT => ic_src_mac,
+ SRC_IP_OUT => ic_src_ip,
+ SRC_UDP_OUT => ic_src_udp,
+ MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10
+ -- Debug
+ DEBUG_OUT => open
+);
+
+-- gk 27.03.01
+MB_IP_CONFIG: slv_mac_memory
+port map(
+ CLK => CLK, -- clk_100,
+ RESET => RESET, --reset_i,
+ BUSY_IN => '0',
+ -- Slave bus
+ SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0),
+ SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read,
+ SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack,
+ SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr,
+ SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd,
+ -- I/O to the backend
+ MEM_CLK_IN => ip_cfg_mem_clk,
+ MEM_ADDR_IN => ip_cfg_mem_addr,
+ MEM_DATA_OUT => ip_cfg_mem_data,
+ -- Status lines
+ STAT => open
+);
+
+-- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
+THE_IPU_INTERFACE: trb_net16_ipu2gbe
+port map(
+ CLK => CLK,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => cts_data,
+ CTS_DATAREADY_OUT => cts_dataready,
+ CTS_READOUT_FINISHED_OUT => cts_readout_finished,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => cts_length,
+ CTS_ERROR_PATTERN_OUT => cts_error_pattern,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => fee_read,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10
+ BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10
+ CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10
+ DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10
+ DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
+ MULT_EVT_ENABLE_IN => use_multievents,
+ MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
+ MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10
+ READOUT_CTR_IN => readout_ctr, -- gk 26.04.10
+ READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10
+ ALLOW_LARGE_IN => allow_large, -- gk 21.07.10
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => pc_wr_en,
+ PC_DATA_OUT => pc_data,
+ PC_READY_IN => pc_ready,
+ PC_SOS_OUT => pc_sos,
+ PC_EOS_OUT => pc_eos, -- gk 07.10.10
+ PC_EOD_OUT => pc_eod,
+ PC_SUB_SIZE_OUT => pc_sub_size,
+ PC_TRIG_NR_OUT => pc_trig_nr,
+ PC_PADDING_OUT => pc_padding,
+ MONITOR_OUT(31 downto 0) => monitor_sent,
+ MONITOR_OUT(63 downto 32) => monitor_dropped,
+ MONITOR_OUT(95 downto 64) => monitor_hr,
+ MONITOR_OUT(127 downto 96) => monitor_sm,
+ MONITOR_OUT(159 downto 128) => monitor_lr,
+ MONITOR_OUT(191 downto 160) => monitor_fifos,
+ MONITOR_OUT(223 downto 192) => monitor_empty,
+ DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
+ DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
+ DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
+ DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4,
+ DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5,
+ DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6,
+ DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7,
+ DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8,
+ DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9,
+ DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10,
+ DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11,
+ DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12
+);
+
+-- Second stage: Packet constructor
+PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
+port map(
+ -- ports for user logic
+ RESET => RESET,
+ CLK => CLK,
+ MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
+ PC_WR_EN_IN => pc_wr_en,
+ PC_DATA_IN => pc_data,
+ PC_READY_OUT => pc_ready,
+ PC_START_OF_SUB_IN => pc_sos, --CHANGED TO SLOW CONTROL PULSE
+ PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10
+ PC_END_OF_DATA_IN => pc_eod,
+ PC_TRANSMIT_ON_OUT => pc_transmit_on,
+ -- queue and subevent layer headers
+ PC_SUB_SIZE_IN => pc_sub_size,
+ PC_PADDING_IN => pc_padding, -- gk 29.03.10
+ PC_DECODING_IN => pc_decoding,
+ PC_EVENT_ID_IN => pc_event_id,
+ PC_TRIG_NR_IN => pc_trig_nr,
+ PC_QUEUE_DEC_IN => pc_queue_dec,
+ PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
+ PC_DELAY_IN => pc_delay, -- gk 28.04.10
+ -- NEW PORTS
+ TC_WR_EN_OUT => tc_wr_en,
+ TC_DATA_OUT => tc_data,
+ TC_H_READY_IN => tc_pc_h_ready,
+ TC_READY_IN => tc_pc_ready,
+ TC_IP_SIZE_OUT => tc_ip_size,
+ TC_UDP_SIZE_OUT => tc_udp_size,
+ --FC_IDENT_OUT => fc_ident,
+ TC_FLAGS_OFFSET_OUT => tc_flags_offset,
+ TC_SOD_OUT => tc_sod,
+ TC_EOD_OUT => tc_eod,
+ DEBUG_OUT(31 downto 0) => dbg_pc1,
+ DEBUG_OUT(63 downto 32) => dbg_pc2
+);
+
-- Third stage: Frame Constructor
FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
port map(
-- MAC part
- MAC: tsmac35 --tsmac36 --tsmac35
+ MAC: tsmac35
port map(
----------------- clock and reset port declarations ------------------
hclk => CLK,
--***************
-- LOGIC ANALYZER SIGNALS
--***************
---ANALYZER_DEBUG_OUT <= dbg_mc or dbg_tc or (dbg_fc1 & dbg_fc2) or rc_debug or dbg_ft or dbg_fr(63 downto 0) or (dbg_fr(95 downto 64) & x"00000000");
---ANALYZER_DEBUG_OUT(3 downto 0) <= dbg_select_protos(99 downto 96);
---ANALYZER_DEBUG_OUT(63 downto 4) <= (others => '0');
+ANALYZER_DEBUG_OUT <= dbg_mc or dbg_tc or (dbg_fc1 & dbg_fc2) or rc_debug or dbg_ft or dbg_fr(63 downto 0) or (dbg_fr(95 downto 64) & x"00000000");
-- Outputs
---FEE_READ_OUT <= fee_read;
+FEE_READ_OUT <= fee_read;
CTS_READOUT_FINISHED_OUT <= cts_readout_finished;
CTS_DATAREADY_OUT <= cts_dataready;
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_event_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_MAX_QUEUE_SIZE_IN : in std_logic_vector(31 downto 0);
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end entity trb_net16_gbe_event_constr;
-
-architecture RTL of trb_net16_gbe_event_constr is
-
-attribute syn_encoding : string;
-
---type saveStates is (IDLE, SAVE_DATA, CLEANUP);
---signal save_current_state, save_next_state : saveStates;
---attribute syn_encoding of save_current_state : signal is "onehot";
-
-type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP);
-signal load_current_state, load_next_state : loadStates;
-attribute syn_encoding of load_current_state : signal is "onehot";
-
-type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR);
-signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates;
-attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot";
-
-signal df_eod, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic;
-signal df_q, df_qq : std_logic_vector(7 downto 0);
-
-signal header_ctr : integer range 0 to 31;
-
-signal shf_data, shf_q, shf_qq : std_logic_vector(7 downto 0);
-signal shf_wr_en, shf_rd_en, shf_empty, shf_full : std_logic;
-signal sub_int_ctr : integer range 0 to 3;
-signal sub_size_to_save : std_logic_vector(31 downto 0);
-
-signal fc_data : std_logic_vector(7 downto 0);
-
-signal qsf_data : std_logic_vector(31 downto 0);
-signal qsf_q, qsf_qq : std_logic_vector(7 downto 0);
-signal qsf_wr, qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq, qsf_rd_en, qsf_rd_en_q, qsf_empty : std_logic;
-
-signal queue_size : std_logic_vector(31 downto 0);
-
-signal termination : std_logic_vector(255 downto 0);
-signal term_ctr : integer range 0 to 33;
-signal size_for_padding : std_logic_vector(7 downto 0);
-
-signal actual_q_size : std_logic_vector(15 downto 0);
-signal tc_data : std_logic_vector(7 downto 0);
-signal df_data : std_logic_vector(7 downto 0);
-signal df_eod_q, df_eod_qq : std_logic;
-signal df_wr_en_q, df_wr_en_qq : std_logic;
-signal qsf_full : std_logic;
-
-begin
-
---*******
--- SAVING PART
---*******
-
---SAVE_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- save_current_state <= IDLE;
--- else
--- save_current_state <= save_next_state;
--- end if;
--- end if;
---end process SAVE_MACHINE_PROC;
---
---SAVE_MACHINE : process(save_current_state, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN)
---begin
--- case (save_current_state) is
---
--- when IDLE =>
--- if (PC_START_OF_SUB_IN = '1') then
--- save_next_state <= SAVE_DATA;
--- else
--- save_next_state <= IDLE;
--- end if;
---
--- when SAVE_DATA =>
--- if (PC_END_OF_DATA_IN = '1') then
--- save_next_state <= CLEANUP;
--- else
--- save_next_state <= SAVE_DATA;
--- end if;
---
--- when CLEANUP =>
--- save_next_state <= IDLE;
---
--- when others => save_next_state <= IDLE;
---
--- end case;
---end process SAVE_MACHINE;
-
-DF_EOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PC_END_OF_DATA_IN = '1') then
- df_eod <= '1';
- else
- df_eod <= '0';
- end if;
-
- df_eod_q <= df_eod;
- df_eod_qq <= df_eod_q;
- end if;
-end process DF_EOD_PROC;
-
-DF_WR_EN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PC_WR_EN_IN = '1') then
- df_wr_en <= '1';
- else
- df_wr_en <= '0';
- end if;
-
- df_wr_en_q <= df_wr_en;
- df_wr_en_qq <= df_wr_en_q;
-
- df_data <= PC_DATA_IN;
- end if;
-end process DF_WR_EN_PROC;
-
-DATA_FIFO : fifo_64kx9
-port map(
- Data(7 downto 0) => df_data, --PC_DATA_IN,
- Data(8) => df_eod_qq,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => df_wr_en_qq,
- RdEn => df_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q(7 downto 0) => df_q,
- Q(8) => load_eod,
- Empty => df_empty,
- Full => df_full
-);
-
-DF_QQ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- df_qq <= df_q;
- end if;
-end process DF_QQ_PROC;
-
-READY_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- --if (save_current_state = IDLE and df_full = '0') then
--- if (df_full = '0') then
--- PC_READY_OUT <= '1';
--- else
--- PC_READY_OUT <= '0';
--- end if;
- PC_READY_OUT <= not qsf_full;
- end if;
-end process READY_PROC;
-
---*****
--- subevent headers
-SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3
-port map(
- Data => shf_data,
- --Clock => CLK,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => shf_wr_en,
- RdEn => shf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => shf_q,
- Empty => shf_empty,
- Full => shf_full
-);
-
-SHF_WR_EN_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (save_sub_hdr_current_state = IDLE) then
- shf_wr_en <= '0';
- else
- shf_wr_en <= '1';
- end if;
- end if;
-end process SHF_WR_EN_PROC;
-
-SHF_Q_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- shf_qq <= shf_q;
- end if;
-end process SHF_Q_PROC;
-
-SAVE_SUB_HDR_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- save_sub_hdr_current_state <= IDLE;
- else
- save_sub_hdr_current_state <= save_sub_hdr_next_state;
- end if;
- end if;
-end process SAVE_SUB_HDR_MACHINE_PROC;
-
-SAVE_SUB_HDR_MACHINE : process(save_sub_hdr_current_state, PC_START_OF_SUB_IN, sub_int_ctr)
-begin
- case (save_sub_hdr_current_state) is
-
- when IDLE =>
- if (PC_START_OF_SUB_IN = '1') then
- save_sub_hdr_next_state <= SAVE_SIZE;
- else
- save_sub_hdr_next_state <= IDLE;
- end if;
-
- when SAVE_SIZE =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_DECODING;
- else
- save_sub_hdr_next_state <= SAVE_SIZE;
- end if;
-
- when SAVE_DECODING =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_ID;
- else
- save_sub_hdr_next_state <= SAVE_DECODING;
- end if;
-
- when SAVE_ID =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= SAVE_TRG_NR;
- else
- save_sub_hdr_next_state <= SAVE_ID;
- end if;
-
- when SAVE_TRG_NR =>
- if (sub_int_ctr = 0) then
- save_sub_hdr_next_state <= IDLE;
- else
- save_sub_hdr_next_state <= SAVE_TRG_NR;
- end if;
-
- when others => save_sub_hdr_next_state <= IDLE;
-
- end case;
-end process SAVE_SUB_HDR_MACHINE;
-
-SUB_INT_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (save_sub_hdr_current_state = IDLE) then
- sub_int_ctr <= 3;
- else
- if (sub_int_ctr = 0) then
- sub_int_ctr <= 3;
- else
- sub_int_ctr <= sub_int_ctr - 1;
- end if;
- end if;
- end if;
-end process SUB_INT_CTR_PROC;
-
-SUB_SIZE_TO_SAVE_PROC : process (CLK)
-begin
- if rising_edge(CLK) then
- if (PC_PADDING_IN = '0') then
- sub_size_to_save <= PC_SUB_SIZE_IN + x"10";
- else
- sub_size_to_save <= PC_SUB_SIZE_IN + x"c";
- end if;
- end if;
-end process SUB_SIZE_TO_SAVE_PROC;
-
-SHF_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case (save_sub_hdr_current_state) is
-
- when IDLE =>
- shf_data <= x"ac";
-
- when SAVE_SIZE =>
- shf_data <= sub_size_to_save(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when SAVE_DECODING =>
- --shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
- if (sub_int_ctr = 0) then
- shf_data(3 downto 0) <= PC_DECODING_IN(3 downto 0);
- shf_data(7 downto 4) <= PC_TRIGGER_TYPE_IN;
- else
- shf_data <= PC_DECODING_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
- end if;
-
- when SAVE_ID =>
- shf_data <= PC_EVENT_ID_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when SAVE_TRG_NR =>
- shf_data <= PC_TRIG_NR_IN(sub_int_ctr * 8 + 7 downto sub_int_ctr * 8);
-
- when others => shf_data <= x"00";
-
- end case;
- end if;
-end process SHF_DATA_PROC;
-
---*******
--- queue sizes
-
-QUEUE_SIZE_FIFO : fifo_512x32x8
-port map(
- Data => qsf_data,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => qsf_wr,
- RdEn => qsf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => qsf_q,
- Empty => qsf_empty,
- Full => qsf_full
-);
-
-qsf_wr <= qsf_wr_en or qsf_wr_en_q or qsf_wr_en_qq;
-
-QSF_DATA_PROC : process(qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq)
-begin
- -- queue size is saved twice in a row to facilitate readout and packet construction
- if (qsf_wr_en = '1' or qsf_wr_en_q = '1') then
- qsf_data(7 downto 0) <= queue_size(31 downto 24);
- qsf_data(15 downto 8) <= queue_size(23 downto 16);
- qsf_data(23 downto 16) <= queue_size(15 downto 8);
- qsf_data(31 downto 24) <= queue_size(7 downto 0);
- elsif (qsf_wr_en_qq = '1') then
- qsf_data(7 downto 0) <= PC_QUEUE_DEC_IN(31 downto 24);
- qsf_data(15 downto 8) <= PC_QUEUE_DEC_IN(23 downto 16);
- qsf_data(23 downto 16) <= PC_QUEUE_DEC_IN(15 downto 8);
- qsf_data(31 downto 24) <= PC_QUEUE_DEC_IN(7 downto 0);
- else
- qsf_data <= (others => '1');
- end if;
-end process QSF_DATA_PROC;
-
-QSF_WR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
-
- qsf_wr_en_q <= qsf_wr_en;
- qsf_wr_en_qq <= qsf_wr_en_q;
-
- if (MULT_EVT_ENABLE_IN = '1') then
- if (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
- if (queue_size + x"10" + PC_SUB_SIZE_IN > PC_MAX_QUEUE_SIZE_IN) then
- qsf_wr_en <= '1';
- else
- qsf_wr_en <= '0';
- end if;
- else
- qsf_wr_en <= '0';
- end if;
- else
- if (PC_END_OF_DATA_IN = '1') then
- qsf_wr_en <= '1';
- else
- qsf_wr_en <= '0';
- end if;
- end if;
- end if;
-end process QSF_WR_PROC;
-
-QUEUE_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (MULT_EVT_ENABLE_IN = '1') then
- if (save_sub_hdr_next_state = SAVE_DECODING and sub_int_ctr = 3) then
- queue_size <= x"0000_0000"; --queue_size <= x"0000_0028";
- elsif (save_sub_hdr_current_state = SAVE_DECODING and sub_int_ctr = 2) then
- if (PC_SUB_SIZE_IN(2) = '1') then
- queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"4" + x"8";
- else
- queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"8";
- end if;
- else
- queue_size <= queue_size;
- end if;
- else
- --if (save_current_state = IDLE) then
- if (PC_START_OF_SUB_IN = '1') then
- queue_size <= x"0000_0000"; --queue_size <= x"0000_0028";
- elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
- if (PC_SUB_SIZE_IN(2) = '1') then
- queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"4" + x"8";
- else
- queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"8";
- end if;
- end if;
- end if;
- end if;
-end process QUEUE_SIZE_PROC;
-
-
-
---*******
--- LOADING PART
---*******
-
-LOAD_MACHINE_PROC : process(CLK) is
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- load_current_state <= IDLE;
- else
- load_current_state <= load_next_state;
- end if;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod, term_ctr)
-begin
- case (load_current_state) is
-
- when IDLE =>
- if (qsf_empty = '0') then -- something in queue sizes fifo means entire queue is waiting
- load_next_state <= GET_Q_SIZE; --PUT_Q_HEADERS;
- else
- load_next_state <= IDLE;
- end if;
-
- when GET_Q_SIZE =>
- if (header_ctr = 0) then
- load_next_state <= START_TRANSFER;
- else
- load_next_state <= GET_Q_SIZE;
- end if;
-
- when START_TRANSFER =>
- load_next_state <= LOAD_Q_HEADERS;
-
- when LOAD_Q_HEADERS =>
- if (header_ctr = 0) then
- load_next_state <= LOAD_SUB;
- else
- load_next_state <= LOAD_Q_HEADERS;
- end if;
-
- when LOAD_SUB =>
- if (header_ctr = 0) then
- load_next_state <= LOAD_DATA;
- else
- load_next_state <= LOAD_SUB;
- end if;
-
- when LOAD_DATA =>
- if (load_eod = '1' and term_ctr = 33) then
- if (size_for_padding(2) = '1') then
- load_next_state <= LOAD_PADDING;
- else
- load_next_state <= LOAD_TERM;
- end if;
- else
- load_next_state <= LOAD_DATA;
- end if;
-
- when LOAD_PADDING =>
- if (header_ctr = 0) then
- load_next_state <= LOAD_TERM;
- else
- load_next_state <= LOAD_PADDING;
- end if;
-
- when LOAD_TERM =>
- if (header_ctr = 0) then
- load_next_state <= CLEANUP;
- else
- load_next_state <= LOAD_TERM;
- end if;
-
- when CLEANUP =>
- load_next_state <= IDLE;
-
- end case;
-end process LOAD_MACHINE;
-
-HEADER_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- header_ctr <= 3;
- elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then
- header_ctr <= 8;
- elsif (load_current_state = LOAD_Q_HEADERS and header_ctr = 0) then
- header_ctr <= 15;
- elsif (load_current_state = LOAD_SUB and header_ctr = 0) then
- if (size_for_padding(2) = '1') then
- header_ctr <= 3;
- else
- header_ctr <= 31;
- end if;
- elsif (load_current_state = LOAD_PADDING and header_ctr = 0) then
- header_ctr <= 31;
- elsif (load_current_state = LOAD_TERM and header_ctr = 0) then
- header_ctr <= 3;
- elsif (TC_RD_EN_IN = '1') then
- if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_SUB or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then
- header_ctr <= header_ctr - 1;
- else
- header_ctr <= header_ctr;
- end if;
- elsif (load_current_state = GET_Q_SIZE) then
- header_ctr <= header_ctr - 1;
- else
- header_ctr <= header_ctr;
- end if;
- end if;
-end process HEADER_CTR_PROC;
-
-SIZE_FOR_PADDING_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = LOAD_SUB and header_ctr = 12) then
- size_for_padding <= shf_q;
- else
- size_for_padding <= size_for_padding;
- end if;
- end if;
-end process SIZE_FOR_PADDING_PROC;
-
-TC_SOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = START_TRANSFER) then
- TC_SOD_OUT <= '1';
- else
- TC_SOD_OUT <= '0';
- end if;
- end if;
-end process TC_SOD_PROC;
-
---*****
--- read from fifos
-
-df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1') or
- (load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1')
- --(load_current_state = LOAD_SUB and header_ctr = 1 and TC_RD_EN_IN = '1')
- else '0';
-
-shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1') or
- (load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1')
- else '0';
-
-QUEUE_FIFO_RD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = GET_Q_SIZE and header_ctr /= 0) then
- qsf_rd_en_q <= '1';
- elsif (load_current_state = IDLE and qsf_empty = '0') then
- qsf_rd_en_q <= '1';
- else
- qsf_rd_en_q <= '0';
- end if;
- end if;
-end process QUEUE_FIFO_RD_PROC;
-
-qsf_rd_en <= '1' when load_current_state = LOAD_Q_HEADERS and TC_RD_EN_IN = '1' else qsf_rd_en_q;
-
-ACTUAL_Q_SIZE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = START_TRANSFER) then
- actual_q_size(7 downto 0) <= qsf_q;
- elsif (load_current_state = GET_Q_SIZE and header_ctr = 0) then
- actual_q_size(15 downto 8) <= qsf_q;
- end if;
- end if;
-end process ACTUAL_Q_SIZE_PROC;
-
-TC_EVENT_SIZE_OUT <= actual_q_size;
-
-TERMINATION_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- termination <= (others => '0');
- elsif (TC_RD_EN_IN = '1' and term_ctr /= 33 and term_ctr /= 0) then
- termination(255 downto 8) <= termination(247 downto 0);
-
- for I in 0 to 7 loop
- case (load_current_state) is
- when LOAD_Q_HEADERS => termination(I) <= qsf_q(I);
- when LOAD_SUB => termination(I) <= shf_q(I);
- when LOAD_DATA => termination(I) <= df_q(I);
- when others => termination(I) <= '0';
- end case;
- end loop;
-
- else
- termination <= termination;
- end if;
- end if;
-end process TERMINATION_PROC;
-
-TERM_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = IDLE) then
- term_ctr <= 0;
- elsif (TC_RD_EN_IN = '1' and term_ctr /= 33) then
- term_ctr <= term_ctr + 1;
- end if;
- end if;
-end process TERM_CTR_PROC;
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- case (load_current_state) is
- when LOAD_Q_HEADERS => tc_data <= qsf_q;
- when LOAD_SUB => tc_data <= shf_q;
- when LOAD_DATA => tc_data <= df_q;
- when LOAD_PADDING => tc_data <= x"aa";
- when LOAD_TERM => tc_data <= termination((header_ctr + 1) * 8 - 1 downto header_ctr * 8);
- when others => tc_data <= x"cc";
- end case;
- end if;
-end process TC_DATA_PROC;
-
-TC_DATA_OUT(7 downto 0) <= tc_data;
-TC_DATA_8_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (load_current_state = LOAD_TERM and header_ctr = 0) then
- TC_DATA_OUT(8) <= '1';
- else
- TC_DATA_OUT(8) <= '0';
- end if;
- end if;
-end process TC_DATA_8_PROC;
-
---*****
--- outputs
-
-
-
-DEBUG_OUT <= (others => '0');
-
-end architecture RTL;
);\r
end component;\r
\r
-attribute syn_encoding : string;\r
+attribute sys_encoding : string;\r
\r
type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
signal constructCurrentState, constructNextState : constructStates;\r
signal bsm_constr : std_logic_vector(7 downto 0);\r
-attribute syn_encoding of constructCurrentState: signal is "onehot";\r
+attribute sys_encoding of constructCurrentState: signal is "safe,gray";\r
\r
type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState : signal is "onehot";\r
-\r
signal bsm_trans : std_logic_vector(3 downto 0);\r
\r
signal headers_int_counter : integer range 0 to 6;\r
signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10\r
\r
signal fpf_reset : std_logic; -- gk 01.01.01\r
-signal link_ok_125, link_ok_q : std_logic;\r
\r
-- gk 09.12.10\r
signal delay_ctr : std_logic_vector(31 downto 0);\r
signal frame_delay_reg : std_logic_vector(31 downto 0);\r
-signal fpf_data_q : std_logic_vector(7 downto 0);\r
-signal fpf_wr_en_q, fpf_eod : std_logic;\r
\r
begin\r
\r
udp_checksum <= x"0000"; -- no checksum test needed\r
--debug <= (others => '0');\r
\r
-process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if constructCurrentState = IDLE then\r
- ready <= '1';\r
- else\r
- ready <= '0';\r
- end if;\r
- \r
- if (constructCurrentState = SAVE_DATA) then\r
- headers_ready <= '1';\r
- else\r
- headers_ready <= '0';\r
- end if;\r
- end if;\r
-end process;\r
---ready <= '1' when (constructCurrentState = IDLE)\r
--- else '0';\r
---headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
--- else '0';\r
- \r
-sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN)\r
+ready <= '1' when (constructCurrentState = IDLE)\r
+ else '0';\r
+headers_ready <= '1' when (constructCurrentState = SAVE_DATA)\r
+ else '0';\r
+\r
+sizeProc: process( put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN)\r
begin\r
- if rising_edge(CLK) then\r
- if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
- ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
- udp_size <= UDP_P_SIZE_IN + x"8";\r
- else\r
- ip_size <= IP_F_SIZE_IN + x"14";\r
- udp_size <= UDP_P_SIZE_IN;\r
- end if;\r
+ if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
+ ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
+ udp_size <= UDP_P_SIZE_IN + x"8";\r
+ else\r
+ ip_size <= IP_F_SIZE_IN + x"14";\r
+ udp_size <= UDP_P_SIZE_IN;\r
end if;\r
end process sizeProc;\r
\r
end if;\r
end process putUdpHeadersProc;\r
\r
+\r
fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN)\r
begin\r
if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
end case;\r
end process fpfDataProc;\r
\r
-syncProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- fpf_data_q <= fpf_data;\r
- fpf_wr_en_q <= fpf_wr_en;\r
- fpf_eod <= END_OF_DATA_IN;\r
- end if;\r
-end process syncProc;\r
- \r
-\r
\r
readyFramesCtrProc: process( CLK )\r
begin\r
end if;\r
end process readyFramesCtrProc;\r
\r
-fpfResetProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (RESET = '1' or LINK_OK_IN = '0') then\r
- fpf_reset <= '1';\r
- else\r
- fpf_reset <= '0';\r
- end if;\r
- end if;\r
-end process fpfResetProc;\r
---fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
+fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
\r
FINAL_PACKET_FIFO: fifo_4096x9\r
port map( \r
- Data(7 downto 0) => fpf_data_q,\r
- Data(8) => fpf_eod, --END_OF_DATA_IN,\r
+ Data(7 downto 0) => fpf_data,\r
+ Data(8) => END_OF_DATA_IN,\r
WrClock => CLK,\r
RdClock => RD_CLK,\r
- WrEn => fpf_wr_en_q,\r
+ WrEn => fpf_wr_en,\r
RdEn => fpf_rd_en, --FT_TX_RD_EN_IN,\r
Reset => fpf_reset,\r
RPReset => fpf_reset,\r
Full => fpf_full\r
);\r
\r
---fpf_rd_en <= FT_TX_RD_EN_IN;\r
-fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1'))\r
- or (link_ok_125 = '0') -- clear the fifo if link is down\r
+fpf_rd_en <= '1' when ((LINK_OK_IN = '1') and (FT_TX_RD_EN_IN = '1'))\r
+ or (LINK_OK_IN = '0') -- clear the fifo if link is down\r
else '0';\r
\r
transferToRdClock : signal_sync\r
D_OUT => ready_frames_ctr_q\r
);\r
\r
-process(RD_CLK)\r
-begin\r
- if rising_edge(RD_CLK) then\r
- link_ok_q <= LINK_OK_IN;\r
- link_ok_125 <= link_ok_q;\r
- end if;\r
-end process;\r
-\r
transmitMachineProc: process( RD_CLK )\r
begin\r
if( rising_edge(RD_CLK) ) then\r
- if( RESET = '1' ) or (link_ok_125 = '0') then -- gk 01.10.10\r
+ if( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
transmitCurrentState <= T_IDLE;\r
else\r
transmitCurrentState <= transmitNextState;\r
end if;\r
end process transmitMachineProc;\r
\r
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
+transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
begin\r
case transmitCurrentState is\r
when T_IDLE =>\r
when T_TRANSMIT =>\r
bsm_trans <= x"2";\r
-- gk 03.08.10\r
- if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
+ if ((LINK_OK_IN = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
transmitNextState <= T_CLEANUP;\r
- elsif (link_ok_125 = '0') then\r
+ elsif (LINK_OK_IN = '0') then\r
transmitNextState <= T_PAUSE;\r
else\r
transmitNextState <= T_TRANSMIT;\r
sopProc: process( RD_CLK )\r
begin\r
if rising_edge(RD_CLK) then\r
- if ( RESET = '1' ) or (link_ok_125 = '0') then -- gk 01.10.10\r
+ if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10\r
ft_sop <= '0';\r
elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then\r
ft_sop <= '1';\r
attribute syn_encoding : string;
type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME, REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);
signal filter_current_state, filter_next_state : filter_states;
-attribute syn_encoding of filter_current_state : signal is "onehot";
+attribute syn_encoding of filter_current_state : signal is "safe,gray";
signal fifo_wr_en : std_logic;
signal rx_bytes_ctr : std_logic_vector(15 downto 0);
signal parsed_frames_ctr : std_logic_vector(15 downto 0);
signal ok_frames_ctr : std_logic_vector(15 downto 0);
-signal rx_data, fr_q : std_logic_vector(8 downto 0);
-
-signal fr_src_ip, fr_dest_ip : std_logic_vector(31 downto 0);
-signal fr_dest_udp, fr_src_udp, fr_frame_size, fr_frame_proto : std_logic_vector(15 downto 0);
-signal fr_dest_mac, fr_src_mac : std_logic_vector(47 downto 0);
-signal fr_ip_proto : std_logic_vector(7 downto 0);
+signal rx_data : std_logic_vector(8 downto 0);
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
begin
+DEBUG_OUT(0) <= rec_fifo_empty;
+DEBUG_OUT(1) <= rec_fifo_full;
+DEBUG_OUT(2) <= sizes_fifo_empty;
+DEBUG_OUT(3) <= sizes_fifo_full;
+DEBUG_OUT(7 downto 4) <= state;
+-- DEBUG_OUT(19 downto 8) <= dbg_rec_frames(11 downto 0);
+-- DEBUG_OUT(31 downto 20) <= parsed_frames_ctr(11 downto 0);
+--
+-- DEBUG_OUT(47 downto 32) <= dbg_ack_frames;
+-- DEBUG_OUT(63 downto 48) <= dbg_drp_frames;
+-- DEBUG_OUT(79 downto 64) <= error_frames_ctr;
+-- DEBUG_OUT(95 downto 80) <= ok_frames_ctr;
+
+
-- new_frame is asserted when first byte of the frame arrives
NEW_FRAME_PROC : process(RX_MAC_CLK)
begin
end if;
end process FILTER_MACHINE_PROC;
-FILTER_MACHINE : process(filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
+FILTER_MACHINE : process(filter_current_state, saved_frame_type, saved_proto, g_MY_MAC, saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)
begin
case filter_current_state is
when IDLE =>
state <= x"1";
- if (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') then
+ if (new_frame = '1') and (ALLOW_RX_IN = '1') then
filter_next_state <= REMOVE_DEST;
else
filter_next_state <= IDLE;
state <= x"6";
if (frame_type_valid = '1') then
filter_next_state <= SAVE_FRAME;
- elsif (saved_frame_type = x"0806") then
- filter_next_state <= SAVE_FRAME;
else
filter_next_state <= DROP_FRAME;
end if;
type_validator : trb_net16_gbe_type_validator
port map(
- CLK => RX_MAC_CLK,
- RESET => RESET,
- FRAME_TYPE_IN => saved_frame_type,
- SAVED_VLAN_ID_IN => saved_vid,
- ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
- VLAN_ID_IN => FR_VLAN_ID_IN,
+ CLK => RX_MAC_CLK,
+ RESET => RESET,
+ FRAME_TYPE_IN => saved_frame_type,
+ SAVED_VLAN_ID_IN => saved_vid,
+ ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,
+ VLAN_ID_IN => FR_VLAN_ID_IN,
-- IP level
- IP_PROTOCOLS_IN => saved_proto,
+ IP_PROTOCOLS_IN => saved_proto,
ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,
-- UDP level
- UDP_PROTOCOL_IN => saved_dest_udp,
+ UDP_PROTOCOL_IN => saved_dest_udp,
ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,
- VALID_OUT => frame_type_valid
+ VALID_OUT => frame_type_valid
);
+--TODO put here a larger fifo maybe (for sure!)
receive_fifo : fifo_4096x9
port map(
--- Data(7 downto 0) => MAC_RXD_IN,
--- Data(8) => MAC_RX_EOF_IN,
- Data => rx_data,
+ Data(7 downto 0) => MAC_RXD_IN,
+ Data(8) => MAC_RX_EOF_IN,
+-- Data => rx_data,
WrClock => RX_MAC_CLK,
RdClock => CLK,
WrEn => fifo_wr_en,
RdEn => FR_RD_EN_IN,
Reset => RESET,
RPReset => RESET,
- Q => fr_q, --FR_Q_OUT,
+ Q => FR_Q_OUT,
Empty => rec_fifo_empty,
Full => rec_fifo_full
);
-- BUG HERE, probably more lost bytes in the fifo in other conditions
---fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
--- --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
--- ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
--- (filter_current_state = DECIDE and frame_type_valid = '1')))
--- else '0';
-
-RX_FIFO_SYNC : process(RX_MAC_CLK)
-begin
- if rising_edge(RX_MAC_CLK) then
-
- rx_data(8) <= MAC_RX_EOF_IN;
- rx_data(7 downto 0) <= MAC_RXD_IN;
-
- if (MAC_RX_EN_IN = '1') then
- if (filter_current_state = SAVE_FRAME) then
- fifo_wr_en <= '1';
- elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then
- fifo_wr_en <= '1';
- elsif (filter_current_state = DECIDE and frame_type_valid = '1') then
- fifo_wr_en <= '1';
- else
- fifo_wr_en <= '0';
- end if;
- else
- fifo_wr_en <= '0';
- end if;
-
- MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
- end if;
-end process RX_FIFO_SYNC;
+fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
+ --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
+ ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
+ (filter_current_state = DECIDE and frame_type_valid = '1')))
+ else '0';
+
+--RX_FIFO_SYNC : process(RX_MAC_CLK)
+--begin
+-- if rising_edge(RX_MAC_CLK) then
+--
+-- rx_data(8) <= MAC_RX_EOF_IN;
+-- rx_data(7 downto 0) <= MAC_RXD_IN;
+--
+-- if (MAC_RX_EN_IN = '1') then
+-- if (filter_current_state = SAVE_FRAME) then
+-- fifo_wr_en <= '1';
+-- elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then
+-- fifo_wr_en <= '1';
+-- elsif (filter_current_state = DECIDE and frame_type_valid = '1') then
+-- fifo_wr_en <= '1';
+-- else
+-- fifo_wr_en <= '0';
+-- end if;
+-- else
+-- fifo_wr_en <= '0';
+-- end if;
+--
+-- end if;
+--end process RX_FIFO_SYNC;
+MAC_RX_FIFO_FULL_OUT <= rec_fifo_full;
sizes_fifo : fifo_512x32
port map(
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(15 downto 0) => fr_frame_size, --FR_FRAME_SIZE_OUT,
- Q(31 downto 16) => fr_frame_proto, --FR_FRAME_PROTO_OUT,
+ Q(15 downto 0) => FR_FRAME_SIZE_OUT,
+ Q(31 downto 16) => FR_FRAME_PROTO_OUT,
Empty => sizes_fifo_empty,
Full => sizes_fifo_full
);
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(47 downto 0) => fr_src_mac, --FR_SRC_MAC_ADDRESS_OUT,
- Q(63 downto 48) => fr_src_udp, --FR_SRC_UDP_PORT_OUT,
+ Q(47 downto 0) => FR_SRC_MAC_ADDRESS_OUT,
+ Q(63 downto 48) => FR_SRC_UDP_PORT_OUT,
Q(71 downto 64) => dump2,
Empty => open,
Full => open
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(47 downto 0) => fr_dest_mac, --FR_DEST_MAC_ADDRESS_OUT,
- Q(63 downto 48) => fr_dest_udp, --FR_DEST_UDP_PORT_OUT,
+ Q(47 downto 0) => FR_DEST_MAC_ADDRESS_OUT,
+ Q(63 downto 48) => FR_DEST_UDP_PORT_OUT,
Q(71 downto 64) => dump,
Empty => open,
Full => open
RdEn => FR_GET_FRAME_IN,
Reset => RESET,
RPReset => RESET,
- Q(31 downto 0) => fr_src_ip, --FR_SRC_IP_ADDRESS_OUT,
- Q(63 downto 32) => fr_dest_ip, --FR_DEST_IP_ADDRESS_OUT,
- Q(71 downto 64) => fr_ip_proto, --FR_IP_PROTOCOL_OUT,
+ Q(31 downto 0) => FR_SRC_IP_ADDRESS_OUT,
+ Q(63 downto 32) => FR_DEST_IP_ADDRESS_OUT,
+ Q(71 downto 64) => FR_IP_PROTOCOL_OUT,
Empty => open,
Full => open
);
-process(CLK)
-begin
- if rising_edge(CLK) then
- FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;
- FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;
- FR_IP_PROTOCOL_OUT <= fr_ip_proto;
- FR_DEST_UDP_PORT_OUT <= fr_dest_udp;
- FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;
- FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;
- FR_SRC_UDP_PORT_OUT <= fr_src_udp;
- FR_FRAME_PROTO_OUT <= fr_frame_proto;
- FR_FRAME_SIZE_OUT <= fr_frame_size;
- FR_Q_OUT <= fr_q;
- end if;
-end process;
-
FRAME_VALID_PROC : process(RX_MAC_CLK)
begin
if rising_edge(RX_MAC_CLK) then
if rising_edge(RX_MAC_CLK) then
if (RESET = '1') or (delayed_frame_valid_q = '1') then
--if (RESET = '1') or (frame_valid_q = '1') then
- rx_bytes_ctr <= x"0001";
+ rx_bytes_ctr <= (others => '0');
elsif (fifo_wr_en = '1') then
rx_bytes_ctr <= rx_bytes_ctr + x"1";
end if;
\r
type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);\r
signal macInitState, macInitNextState : macInitStates;\r
-attribute syn_encoding of macInitState: signal is "onehot";\r
+attribute syn_encoding of macInitState: signal is "safe,gray";\r
signal bsm_init : std_logic_vector(3 downto 0);\r
\r
type macStates is (M_RESETING, M_IDLE, M_INIT);\r
signal macCurrentState, macNextState : macStates;\r
-attribute syn_encoding of macCurrentState : signal is "onehot";\r
signal bsm_mac : std_logic_vector(3 downto 0);\r
\r
type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState: signal is "onehot";\r
+attribute syn_encoding of transmitCurrentState: signal is "safe,gray";\r
signal bsm_trans : std_logic_vector(3 downto 0);\r
\r
signal tx_fifoavail_i : std_logic;\r
signal FifoEmpty : std_logic;\r
signal debug : std_logic_vector(63 downto 0);\r
signal sent_ctr : std_logic_vector(31 downto 0);\r
-signal link_ok_125 : std_logic;\r
\r
begin\r
\r
-linkOkSync : pulse_sync\r
-port map(\r
- CLK_A_IN => CLK,\r
- RESET_A_IN => RESET,\r
- PULSE_A_IN => LINK_OK_IN,\r
- CLK_B_IN => TX_MAC_CLK,\r
- RESET_B_IN => RESET,\r
- PULSE_B_OUT => link_ok_125\r
-);\r
-\r
-- Fakes\r
debug(63 downto 32) <= (others => '0');\r
--debug(31 downto 0) <= sent_ctr;\r
end if;\r
end process TransmitStatemachineProc;\r
\r
+--TransmitStateMachine : process (transmitCurrentState, macCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN)\r
begin\r
case transmitCurrentState is\r
when T_IDLE =>\r
bsm_trans <= x"0";\r
- if (START_OF_PACKET_IN = '1') then\r
+ if (START_OF_PACKET_IN = '1') then --and (macCurrentState = M_IDLE)) then\r
transmitNextState <= T_TRANSMIT;\r
else\r
transmitNextState <= T_IDLE;\r
end if;\r
when T_WAITFORFIFO =>\r
bsm_trans <= x"2";\r
- if (TX_DONE_IN = '1') then\r
+ if (TX_DONE_IN = '1') then --or (TX_DISCFRM_IN = '1') then\r
transmitNextState <= T_IDLE;\r
else\r
transmitNextState <= T_WAITFORFIFO;\r
READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0);
- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0);
+ SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0) := (others => '0');
-- PacketConstructor interface
ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
+++ /dev/null
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_ipu_interface is
- port (
- CLK_IPU : in std_logic;
- CLK_GBE : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
- );
-end entity trb_net16_gbe_ipu_interface;
-
-architecture RTL of trb_net16_gbe_ipu_interface is
-
-attribute syn_encoding : string;
-
-type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, RESET_FIFO, CLEANUP, DROP_SUBEVENT);
-signal save_current_state, save_next_state : saveStates;
-attribute syn_encoding of save_current_state : signal is "onehot";
-
---type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, CALC_PADDING, WAIT_FOR_LOAD, LOAD, LOAD_LAST_ONE, LOAD_LAST_TWO, DROP, CLOSE);
-type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, WAIT_FOR_LOAD, LOAD, CLOSE);
-signal load_current_state, load_next_state : loadStates;
-attribute syn_encoding of load_current_state : signal is "onehot";
-
-signal sf_data : std_Logic_vector(15 downto 0);
-signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eod, sf_eod_q, sf_eod_qq : std_logic;
-signal sf_q, pc_data : std_logic_vector(7 downto 0);
-
-signal cts_rnd, cts_trg : std_logic_vector(15 downto 0);
-signal save_ctr : std_logic_vector(15 downto 0);
-
-signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(7 downto 0);
-signal loaded_bytes_ctr : std_Logic_vector(15 downto 0);
-
-signal trigger_random : std_logic_vector(7 downto 0);
-signal trigger_number : std_logic_vector(15 downto 0);
-signal subevent_size : std_logic_vector(17 downto 0);
-signal trigger_type : std_logic_vector(3 downto 0);
-
-signal bank_select : std_logic_vector(3 downto 0);
-signal readout_ctr : std_logic_vector(23 downto 0);
-
-begin
-
---*********
--- RECEIVING PART
---*********
-
-SAVE_MACHINE_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (RESET = '1') then
- save_current_state <= IDLE;
- else
- save_current_state <= save_next_state;
- end if;
- end if;
-end process SAVE_MACHINE_PROC;
-
-SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
-begin
- case (save_current_state) is
-
- when IDLE =>
- if (CTS_START_READOUT_IN = '1') then
- save_next_state <= SAVE_EVT_ADDR;
- else
- save_next_state <= IDLE;
- end if;
-
- when SAVE_EVT_ADDR =>
- save_next_state <= WAIT_FOR_DATA;
-
- when WAIT_FOR_DATA =>
- if (FEE_BUSY_IN = '1') then
- save_next_state <= SAVE_DATA;
- else
- save_next_state <= WAIT_FOR_DATA;
- end if;
-
- when SAVE_DATA =>
- if (FEE_BUSY_IN = '0') then
- save_next_state <= TERMINATE;
- else
- save_next_state <= SAVE_DATA;
- end if;
-
- when TERMINATE =>
- if (CTS_READ_IN = '1') then
- save_next_state <= CLOSE;
- else
- save_next_state <= TERMINATE;
- end if;
-
- when CLOSE =>
- if (CTS_START_READOUT_IN = '0') then
- if (sf_afull = '0') then
- save_next_state <= ADD_SUBSUB1;
- else
- save_next_state <= DROP_SUBEVENT;
- end if;
- else
- save_next_state <= CLOSE;
- end if;
-
- when ADD_SUBSUB1 =>
- save_next_state <= ADD_SUBSUB2;
-
- when ADD_SUBSUB2 =>
- save_next_state <= ADD_SUBSUB3;
-
- when ADD_SUBSUB3 =>
- save_next_state <= ADD_SUBSUB4;
-
- when ADD_SUBSUB4 =>
- save_next_state <= CLEANUP;
-
- when CLEANUP =>
- save_next_state <= IDLE;
-
- when DROP_SUBEVENT =>
- save_next_state <= IDLE;
-
- --TODO: complete with reset fifo state
-
- when others => save_next_state <= IDLE;
-
- end case;
-end process SAVE_MACHINE;
-
-SF_WR_EN_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (sf_afull = '0') then
- if (save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then
- sf_wr_en <= '1';
- elsif (save_current_state = SAVE_EVT_ADDR) then
- sf_wr_en <= '1';
- elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then
- sf_wr_en <= '1';
- else
- sf_wr_en <= '0';
- end if;
- else
- sf_wr_en <= '0';
- end if;
- end if;
-end process SF_WR_EN_PROC;
-
-SF_DATA_EOD_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- case (save_current_state) is
-
- when SAVE_EVT_ADDR =>
- sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0);
- sf_data(7 downto 4) <= CTS_READOUT_TYPE_IN;
- sf_data(15 downto 8) <= x"ab";
- save_eod <= '0';
-
- when SAVE_DATA =>
- sf_data <= FEE_DATA_IN;
- save_eod <= '0';
-
- when ADD_SUBSUB1 =>
- sf_data <= x"0001";
- save_eod <= '0';
-
- when ADD_SUBSUB2 =>
- sf_data <= x"5555";
- save_eod <= '0';
-
- when ADD_SUBSUB3 =>
- sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
- save_eod <= '1';
-
- when ADD_SUBSUB4 =>
- sf_data <= FEE_STATUS_BITS_IN(15 downto 0);
- save_eod <= '0';
-
- when others => sf_data <= (others => '0'); save_eod <= '0';
-
- end case;
- end if;
-end process SF_DATA_EOD_PROC;
-
-SAVED_EVENTS_CTR_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (RESET = '1') then
- saved_events_ctr <= (others => '0');
- elsif (save_current_state = ADD_SUBSUB4) then
- saved_events_ctr <= saved_events_ctr + x"1";
- else
- saved_events_ctr <= saved_events_ctr;
- end if;
- end if;
-end process SAVED_EVENTS_CTR_PROC;
-
-CTS_DATAREADY_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then
- CTS_DATAREADY_OUT <= '1';
- elsif (save_current_state = TERMINATE) then
- CTS_DATAREADY_OUT <= '1';
- else
- CTS_DATAREADY_OUT <= '0';
- end if;
- end if;
-end process CTS_DATAREADY_PROC;
-
-CTS_READOUT_FINISHED_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = CLOSE) then
- CTS_READOUT_FINISHED_OUT <= '1';
- else
- CTS_READOUT_FINISHED_OUT <= '0';
- end if;
- end if;
-end process CTS_READOUT_FINISHED_PROC;
-
-CTS_LENGTH_OUT <= (others => '0');
-CTS_ERROR_PATTERN_OUT <= (others => '0');
-
-CTS_DATA_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg;
- end if;
-end process CTS_DATA_PROC;
-
-CTS_RND_TRG_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = SAVE_DATA and save_ctr = x"0000") then
- cts_rnd <= sf_data;
- cts_trg <= cts_trg;
- elsif (save_current_state = SAVE_DATA and save_ctr = x"0001") then
- cts_rnd <= cts_rnd;
- cts_trg <= sf_data;
- else
- cts_rnd <= cts_rnd;
- cts_trg <= cts_trg;
- end if;
- end if;
-end process CTS_RND_TRG_PROC;
-
-SAVE_CTR_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (save_current_state = IDLE) then
- save_ctr <= (others => '0');
- elsif (save_current_state = SAVE_DATA and sf_wr_en = '1') then
- save_ctr <= save_ctr + x"1";
- else
- save_ctr <= save_ctr;
- end if;
- end if;
-end process SAVE_CTR_PROC;
-
-FEE_READ_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (sf_afull = '0') then
- if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then
- FEE_READ_OUT <= '1';
- else
- FEE_READ_OUT <= '0';
- end if;
- else
- FEE_READ_OUT <= '0';
- end if;
- end if;
-end process FEE_READ_PROC;
-
-
-THE_SPLIT_FIFO: fifo_32kx16x8_mb2 --fifo_16kx18x9
-port map(
- -- Byte swapping for correct byte order on readout side of FIFO
- Data(7 downto 0) => sf_data(15 downto 8),
- Data(8) => '0',
- Data(16 downto 9) => sf_data(7 downto 0),
- Data(17) => save_eod,
- WrClock => CLK_IPU,
- RdClock => CLK_GBE,
- WrEn => sf_wr_en,
- RdEn => sf_rd_en,
- Reset => sf_reset,
- RPReset => sf_reset,
- AmEmptyThresh => b"0000_0000_0000_0010", --b"0000_0000_0000_0010", -- one byte ahead
- AmFullThresh => b"111_1111_1110_1111", --b"111_1111_1110_1111", -- 0x7fef = 32751
- Q(7 downto 0) => sf_q,
- Q(8) => sf_eod,
- --WCNT => open,
- --RCNT => open,
- Empty => sf_empty,
- AlmostEmpty => open,
- Full => open, --sf_afull -- WARNING, JUST FOR DEBUG
- AlmostFull => sf_afull
-);
-
-SF_RESET_PROC : process(CLK_IPU)
-begin
- if rising_edge(CLK_IPU) then
- if (RESET = '1') then
- sf_reset <= '1';
- elsif (save_current_state = DROP_SUBEVENT) then
- sf_reset <= '1';
- else
- sf_reset <= '0';
- end if;
- end if;
-end process SF_RESET_PROC;
-
---*********
--- LOADING PART
---*********
-
-PC_DATA_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- pc_data <= sf_q;
- end if;
-end process PC_DATA_PROC;
-
-LOAD_MACHINE_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (RESET = '1') then
- load_current_state <= IDLE;
- else
- load_current_state <= load_next_state;
- end if;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eod, MULT_EVT_ENABLE_IN)
-begin
- case (load_current_state) is
-
- when IDLE =>
- if (saved_events_ctr /= loaded_events_ctr) then
- load_next_state <= REMOVE;
- else
- load_next_state <= IDLE;
- end if;
-
- when REMOVE =>
- if (loaded_bytes_ctr = x"0008") then
- load_next_state <= WAIT_ONE;
- else
- load_next_state <= REMOVE;
- end if;
-
- when WAIT_ONE =>
- load_next_state <= DECIDE;
-
- when DECIDE =>
- load_next_state <= WAIT_FOR_LOAD;
-
- when WAIT_FOR_LOAD =>
- if (PC_READY_IN = '1') then
- load_next_state <= LOAD;
- else
- load_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- if (sf_eod = '1') then
- load_next_state <= CLOSE; --LOAD_LAST_ONE;
- else
- load_next_state <= LOAD;
- end if;
-
--- when LOAD_LAST_ONE =>
--- load_next_state <= LOAD_LAST_TWO;
---
--- when LOAD_LAST_TWO =>
--- load_next_state <= CLOSE;
- --when DROP =>
-
- when CLOSE =>
- load_next_state <= IDLE;
-
- when others => load_next_state <= IDLE;
-
- end case;
-end process LOAD_MACHINE;
-
-saved_ctr_sync : signal_sync
-generic map(
- WIDTH => 8,
- DEPTH => 2
-)
-port map(
- RESET => RESET,
- CLK0 => CLK_GBE,
- CLK1 => CLK_GBE,
- D_IN => saved_events_ctr,
- D_OUT => saved_events_ctr_gbe
-);
-
-
---TODO: create a proper read signal here
-SF_RD_EN_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = REMOVE) then
- sf_rd_en <= '1';
- elsif (load_current_state = LOAD) then
- sf_rd_en <= '1';
- else
- sf_rd_en <= '0';
- end if;
- end if;
-end process SF_RD_EN_PROC;
-
---*****
--- information extraction
-
-TRIGGER_RANDOM_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_random <= (others => '0');
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0005") then
- trigger_random <= pc_data;
- else
- trigger_random <= trigger_random;
- end if;
- end if;
-end process TRIGGER_RANDOM_PROC;
-
-TRIGGER_NUMBER_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_number <= (others => '0');
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0007") then
- trigger_number(7 downto 0) <= pc_data;
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0006") then
- trigger_number(15 downto 8) <= pc_data;
- else
- trigger_number <= trigger_number;
- end if;
- end if;
-end process TRIGGER_NUMBER_PROC;
-
-SUBEVENT_SIZE_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- subevent_size <= (others => '0');
- elsif (load_current_state = WAIT_ONE and sf_rd_en = '1' and loaded_bytes_ctr = x"0009") then
- subevent_size(9 downto 2) <= pc_data;
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then
- subevent_size(17 downto 10) <= pc_data;
- elsif (load_current_state = DECIDE) then
- subevent_size <= subevent_size + x"8";
- else
- subevent_size <= subevent_size;
- end if;
- end if;
-end process SUBEVENT_SIZE_PROC;
-
-TRIGGER_TYPE_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- trigger_type <= x"0";
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- trigger_type <= pc_data(7 downto 4);
- else
- trigger_type <= trigger_type;
- end if;
- end if;
-end process TRIGGER_TYPE_PROC;
-
--- end of extraction
---*****
-
---*****
--- counters
-
-LOADED_EVENTS_CTR_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (RESET = '1') then
- loaded_events_ctr <= (others => '0');
- elsif (load_current_state = CLOSE) then
- loaded_events_ctr <= loaded_events_ctr + x"1";
- else
- loaded_events_ctr <= loaded_events_ctr;
- end if;
- end if;
-end process LOADED_EVENTS_CTR_PROC;
-
-LOADED_BYTES_CTR_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE or load_current_state = DECIDE) then
- loaded_bytes_ctr <= (others => '0');
- elsif (sf_rd_en = '1') then
- if (load_current_state = REMOVE or load_current_state = LOAD) then
- loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
- end if;
- end if;
-end process LOADED_BYTES_CTR_PROC;
-
-READOUT_CTR_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (RESET = '1' or READOUT_CTR_VALID_IN = '1') then
- readout_ctr <= READOUT_CTR_IN;
- elsif (load_current_state = DECIDE) then
- readout_ctr <= readout_ctr + x"1";
- else
- readout_ctr <= readout_ctr;
- end if;
- end if;
-end process READOUT_CTR_PROC;
-
--- end of counters
---*****
-
---*****
--- event builder selection
-
---TODO: close the current multievent packet in case event builder address changes
-
-BANK_SELECT_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = IDLE) then
- bank_select <= x"0";
- elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- bank_select <= pc_data(3 downto 0);
- else
- bank_select <= bank_select;
- end if;
- end if;
-end process BANK_SELECT_PROC;
-
-BANK_SELECT_OUT <= bank_select;
-
-START_CONFIG_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0003") then
- START_CONFIG_OUT <= '1';
- elsif (CONFIG_DONE_IN = '1') then
- START_CONFIG_OUT <= '0';
- else
- START_CONFIG_OUT <= '0';
- end if;
- end if;
-end process START_CONFIG_PROC;
-
--- end of event builder selection
---*****
-
-
-PC_WR_EN_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = LOAD) then
- PC_WR_EN_OUT <= '1';
--- elsif (load_current_state = LOAD_LAST_ONE or load_current_state = LOAD_LAST_TWO) then
--- PC_WR_EN_OUT <= '1';
- else
- PC_WR_EN_OUT <= '0';
- end if;
- end if;
-end process PC_WR_EN_PROC;
-
-PC_SOS_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (load_current_state = DECIDE) then
- PC_SOS_OUT <= '1';
- else
- PC_SOS_OUT <= '0';
- end if;
- end if;
-end process PC_SOS_PROC;
-
-PC_EOD_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- if (sf_eod = '1') then
- sf_eod_q <= '1';
- else
- sf_eod_q <= '0';
- end if;
-
- --sf_eod_qq <= sf_eod_q;
- --PC_EOD_OUT <= sf_eod_qq;
- PC_EOD_OUT <= sf_eod; --_q;
- end if;
-end process PC_EOD_PROC;
-
-PC_EOS_PROC : process(CLK_GBE)
-begin
- if rising_edge(CLK_GBE) then
- PC_EOS_OUT <= '0';
- end if;
-end process PC_EOS_PROC;
-
---*******
--- outputs
-
-PC_DATA_OUT <= pc_data;
-
-PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & subevent_size;
-
-PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random;
-
-PC_TRIGGER_TYPE_OUT <= trigger_type;
-
-PC_PADDING_OUT <= '0'; --padding_needed; not used anymore
-
-DEBUG_OUT <= (others => '0');
-MONITOR_OUT <= (others => '0');
-
-end architecture RTL;
architecture trb_net16_gbe_mac_control of trb_net16_gbe_mac_control is
-attribute syn_encoding : string;
+--attribute HGROUP : string;
+--attribute HGROUP of trb_net16_gbe_mac_control : architecture is "GBE_BUF_group";
-type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL1, WRITE_TX_RX_CTRL2, ENABLE, READY);
+type mac_conf_states is (IDLE, DISABLE, WRITE_TX_RX_CTRL, WRITE_MAX_PKT_SIZE, SKIP, WRITE_IPG,
+ WRITE_MAC0, WRITE_MAC1, WRITE_MAC2, ENABLE, READY);
signal mac_conf_current_state, mac_conf_next_state : mac_conf_states;
-attribute syn_encoding of mac_conf_current_state : signal is "onehot";
signal tsmac_ready : std_logic;
-signal reg_mode : std_logic_vector(7 downto 0);
-signal reg_tx_rx_ctrl1, reg_tx_rx_ctrl2 : std_logic_vector(7 downto 0);
+signal reg_mode : std_logic_vector(15 downto 0);
+signal reg_tx_rx_ctrl : std_logic_vector(15 downto 0);
signal reg_max_pkt_size : std_logic_vector(15 downto 0);
signal reg_ipg : std_logic_vector(15 downto 0);
signal reg_mac0 : std_logic_vector(15 downto 0);
begin
-reg_mode(7 downto 4) <= x"0";
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(7 downto 4) <= haddr(3 downto 0);
+DEBUG_OUT(8) <= hcs_n;
+DEBUG_OUT(9) <= hwrite_n;
+DEBUG_OUT(63 downto 11) <= (others => '0');
+
+reg_mode(15 downto 4) <= (others => '0'); -- reserved
reg_mode(3) <= '1'; -- tx_en
reg_mode(2) <= '1'; -- rx_en
reg_mode(1) <= '1'; -- flow_control en
reg_mode(0) <= MC_GBE_EN_IN; -- gbe en
-reg_tx_rx_ctrl2(7 downto 1) <= (others => '0'); -- reserved
-reg_tx_rx_ctrl2(0) <= '1'; -- receive short
-reg_tx_rx_ctrl1(7) <= '1'; -- receive broadcast
-reg_tx_rx_ctrl1(6) <= '1'; -- drop control
-reg_tx_rx_ctrl1(5) <= '0'; -- half_duplex en
-reg_tx_rx_ctrl1(4) <= '1'; -- receive multicast
-reg_tx_rx_ctrl1(3) <= '1'; -- receive pause
-reg_tx_rx_ctrl1(2) <= '0'; -- transmit disable FCS
-reg_tx_rx_ctrl1(1) <= '1'; -- receive discard FCS and padding
-reg_tx_rx_ctrl1(0) <= MC_PROMISC_IN; -- promiscuous mode
+reg_tx_rx_ctrl(15 downto 9) <= (others => '0'); -- reserved
+reg_tx_rx_ctrl(8) <= '1'; -- receive short
+reg_tx_rx_ctrl(7) <= '1'; -- receive broadcast
+reg_tx_rx_ctrl(6) <= '1'; -- drop control
+reg_tx_rx_ctrl(5) <= '0'; -- half_duplex en
+reg_tx_rx_ctrl(4) <= '1'; -- receive multicast
+reg_tx_rx_ctrl(3) <= '1'; -- receive pause
+reg_tx_rx_ctrl(2) <= '0'; -- transmit disable FCS
+reg_tx_rx_ctrl(1) <= '1'; -- receive discard FCS and padding
+reg_tx_rx_ctrl(0) <= MC_PROMISC_IN; -- promiscuous mode
+
+reg_max_pkt_size(15 downto 0) <= x"05EE"; -- 1518 default value
+
+reg_ipg(15 downto 5) <= (others => '0');
+reg_ipg(4 downto 0) <= "01100"; -- default value inter-packet-gap in byte time
+
+reg_mac0(7 downto 0) <= MC_MAC_ADDR_IN(7 downto 0);
+reg_mac0(15 downto 8) <= MC_MAC_ADDR_IN(15 downto 8);
+reg_mac1(7 downto 0) <= MC_MAC_ADDR_IN(23 downto 16);
+reg_mac1(15 downto 8) <= MC_MAC_ADDR_IN(31 downto 24);
+reg_mac2(7 downto 0) <= MC_MAC_ADDR_IN(39 downto 32);
+reg_mac2(15 downto 8) <= MC_MAC_ADDR_IN(47 downto 40);
MAC_CONF_MACHINE_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (MC_RECONF_IN = '1') then
mac_conf_current_state <= IDLE;
else
mac_conf_current_state <= mac_conf_next_state;
end if;
end process MAC_CONF_MACHINE_PROC;
-MAC_CONF_MACHINE : process(mac_conf_current_state, MC_RECONF_IN, TSM_HREADY_N_IN)
+MAC_CONF_MACHINE : process(mac_conf_current_state, tsmac_ready, haddr)
begin
case mac_conf_current_state is
when IDLE =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= IDLE;
- end if;
+ state <= x"1";
+ if (tsmac_ready = '0') then
+ mac_conf_next_state <= DISABLE;
+ else
+ mac_conf_next_state <= IDLE;
+ end if;
when DISABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- else
- mac_conf_next_state <= DISABLE;
- end if;
-
- when WRITE_TX_RX_CTRL1 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL1;
- end if;
-
- when WRITE_TX_RX_CTRL2 =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= ENABLE;
- else
- mac_conf_next_state <= WRITE_TX_RX_CTRL2;
- end if;
+ state <= x"2";
+ if (haddr = x"01") then
+ mac_conf_next_state <= WRITE_TX_RX_CTRL;
+ else
+ mac_conf_next_state <= DISABLE;
+ end if;
+
+ when WRITE_TX_RX_CTRL =>
+ state <= x"3";
+ if (haddr = x"03") then
+ mac_conf_next_state <= WRITE_MAX_PKT_SIZE;
+ else
+ mac_conf_next_state <= WRITE_TX_RX_CTRL;
+ end if;
+
+ when WRITE_MAX_PKT_SIZE =>
+ state <= x"4";
+ if (haddr = x"05") then
+ mac_conf_next_state <= SKIP;
+ else
+ mac_conf_next_state <= WRITE_MAX_PKT_SIZE;
+ end if;
+
+ when SKIP =>
+ state <= x"5";
+ if (haddr = x"07") then
+ mac_conf_next_state <= WRITE_IPG;
+ else
+ mac_conf_next_state <= SKIP;
+ end if;
+
+ when WRITE_IPG =>
+ state <= x"6";
+ if (haddr = x"09") then
+ mac_conf_next_state <= WRITE_MAC0;
+ else
+ mac_conf_next_state <= WRITE_IPG;
+ end if;
+
+ when WRITE_MAC0 =>
+ state <= x"7";
+ if (haddr = x"0B") then
+ mac_conf_next_state <= WRITE_MAC1;
+ else
+ mac_conf_next_state <= WRITE_MAC0;
+ end if;
+
+ when WRITE_MAC1 =>
+ state <= x"8";
+ if (haddr = x"0D") then
+ mac_conf_next_state <= WRITE_MAC2;
+ else
+ mac_conf_next_state <= WRITE_MAC1;
+ end if;
+
+ when WRITE_MAC2 =>
+ state <= x"9";
+ if (haddr = x"0F") then
+ mac_conf_next_state <= ENABLE;
+ else
+ mac_conf_next_state <= WRITE_MAC2;
+ end if;
when ENABLE =>
- if (TSM_HREADY_N_IN = '0') then
- mac_conf_next_state <= READY;
- else
- mac_conf_next_state <= ENABLE;
- end if;
+ state <= x"a";
+ if (haddr = x"01") then
+ mac_conf_next_state <= READY;
+ else
+ mac_conf_next_state <= ENABLE;
+ end if;
when READY =>
- if (MC_RECONF_IN = '1') then
- mac_conf_next_state <= DISABLE;
- else
- mac_conf_next_state <= READY;
- end if;
+ state <= x"b";
+ if (MC_RECONF_IN = '1') then
+ mac_conf_next_state <= IDLE;
+ else
+ mac_conf_next_state <= READY;
+ end if;
end case;
HADDR_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HADDR_OUT <= x"00";
- when DISABLE =>
- TSM_HADDR_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HADDR_OUT <= x"02";
- when WRITE_TX_RX_CTRL2 =>
- TSM_HADDR_OUT <= x"03";
- when ENABLE =>
- TSM_HADDR_OUT <= x"00";
- when READY =>
- TSM_HADDR_OUT <= x"00";
- end case;
- end if;
+ if rising_edge(CLK) then
+ if (RESET = '1') or (mac_conf_current_state = IDLE) then
+ haddr <= (others => '0');
+ elsif (mac_conf_current_state /= IDLE) and (hcs_n = '0') and (TSM_HREADY_N_IN = '0') then
+ haddr <= haddr + x"1";
+ elsif (mac_conf_current_state = SKIP) then
+ haddr <= haddr + x"1";
+ elsif (mac_conf_current_state = WRITE_MAC2) and (haddr = x"0F") and (TSM_HREADY_N_IN = '0') then
+ haddr <= (others => '0');
+ end if;
+ end if;
end process HADDR_PROC;
-HDATA_PROC : process(CLK)
+HDATA_PROC : process(mac_conf_current_state)
begin
- if rising_edge(CLK) then
- case mac_conf_current_state is
- when IDLE =>
- TSM_HDATA_OUT <= x"00";
- when DISABLE =>
- TSM_HDATA_OUT <= x"00";
- when WRITE_TX_RX_CTRL1 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl1;
- when WRITE_TX_RX_CTRL2 =>
- TSM_HDATA_OUT <= reg_tx_rx_ctrl2;
- when ENABLE =>
- TSM_HDATA_OUT <= reg_mode;
- when READY =>
- TSM_HDATA_OUT <= x"00";
- end case;
- end if;
+
+ case mac_conf_current_state is
+
+ when WRITE_TX_RX_CTRL =>
+ TSM_HDATA_OUT <= reg_tx_rx_ctrl(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when WRITE_MAX_PKT_SIZE =>
+ TSM_HDATA_OUT <= reg_max_pkt_size(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when WRITE_IPG =>
+ TSM_HDATA_OUT <= reg_ipg(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when WRITE_MAC0 =>
+ TSM_HDATA_OUT <= reg_mac0(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when WRITE_MAC1 =>
+ TSM_HDATA_OUT <= reg_mac1(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when WRITE_MAC2 =>
+ TSM_HDATA_OUT <= reg_mac2(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when ENABLE =>
+ TSM_HDATA_OUT <= reg_mode(7 + 8 * hdata_pointer downto 8 * hdata_pointer);
+
+ when others =>
+ TSM_HDATA_OUT <= (others => '0');
+
+ end case;
+
end process HDATA_PROC;
-process(CLK)
+-- delay hready by one clock cycle to keep hcs and hwrite active during hready
+HREADY_Q_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (mac_conf_current_state = IDLE or mac_conf_current_state = READY) then
- hcs_n <= '1';
- hwrite_n <= '1';
- elsif (TSM_HREADY_N_IN = '1') then
- hcs_n <= '0';
- hwrite_n <= '0';
- else
- hcs_n <= '1';
- hwrite_n <= '1';
- end if;
-
- if (mac_conf_current_state = READY) then
- tsmac_ready <= '1';
- else
- tsmac_ready <= '0';
- end if;
- end if;
-end process;
+ if rising_edge(CLK) then
+ hready_n_q <= TSM_HREADY_N_IN;
+ end if;
+end process HREADY_Q_PROC;
+
+hdata_pointer <= 1 when haddr(0) = '1' else 0;
+
+hcs_n <= '0' when (mac_conf_current_state /= IDLE) and (mac_conf_current_state /= SKIP) and (mac_conf_current_state /= READY) and (hready_n_q = '1')
+ else '1'; -- should also support reading
+
+hwrite_n <= hcs_n when (mac_conf_current_state /= IDLE) else '1'; -- active only during writing
+
+tsmac_ready <= '1' when (mac_conf_current_state = READY) else '0';
+TSM_HADDR_OUT <= haddr;
TSM_HCS_N_OUT <= hcs_n;
TSM_HWRITE_N_OUT <= hwrite_n;
-TSM_HREAD_N_OUT <= '1';
+TSM_HREAD_N_OUT <= '1'; -- for the moment no reading
MC_TSMAC_READY_OUT <= tsmac_ready;
MC_LINK_OK_OUT : out std_logic;
MC_RESET_LINK_IN : in std_logic;
- MC_IDLE_TOO_LONG_OUT : out std_logic;
-- signals to/from receive controller
RC_FRAME_WAITING_IN : in std_logic;
RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT : out std_logic;
+ TC_TRANSMIT_CTRL_OUT : out std_logic; -- slow control frame is waiting to be built and sent
+ TC_TRANSMIT_DATA_OUT : out std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_RD_EN_IN : in std_logic;
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
TC_TRANSMIT_DONE_IN : in std_logic;
+-- signals to/from packet constructor
+ PC_READY_IN : in std_logic;
+ PC_TRANSMIT_ON_IN : in std_logic;
+ PC_SOD_IN : in std_logic;
+
-- signals to/from sgmii/gbe pcs_an_complete
PCS_AN_COMPLETE_IN : in std_logic;
GSC_REPLY_READ_OUT : out std_logic;
GSC_BUSY_IN : in std_logic;
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-
MAKE_RESET_OUT : out std_logic;
-- signal to/from Host interface of TriSpeed MAC
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
-attribute syn_encoding : string;
-
signal tsm_ready : std_logic;
signal tsm_reconf : std_logic;
signal tsm_haddr : std_logic_vector(7 downto 0);
type link_states is (ACTIVE, INACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS);
signal link_current_state, link_next_state : link_states;
-attribute syn_encoding of link_current_state : signal is "onehot";
signal link_down_ctr : std_logic_vector(15 downto 0);
signal link_down_ctr_lock : std_logic;
signal mac_control_debug : std_logic_vector(63 downto 0);
-type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP);
+type flow_states is (IDLE, TRANSMIT_DATA, TRANSMIT_CTRL, CLEANUP);
signal flow_current_state, flow_next_state : flow_states;
-attribute syn_encoding of flow_current_state : signal is "onehot";
signal state : std_logic_vector(3 downto 0);
signal link_state : std_logic_vector(3 downto 0);
signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP);
+type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, FINISH, CLEANUP);
signal redirect_current_state, redirect_next_state : redirect_states;
-attribute syn_encoding of redirect_current_state : signal is "onehot";
-signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic;
+signal frame_type : std_logic_vector(15 downto 0);
+signal disable_redirect, ps_wr_en_q : std_logic;
type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
signal dbg_ps : std_Logic_vector(63 downto 0);
-signal tc_data : std_logic_vector(8 downto 0);
-
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
-attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
-attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true;
+attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state : signal is true;
+attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state : signal is true;
signal mc_busy : std_logic;
RESET => RESET,
PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
- PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en,
+ PS_WR_EN_IN => ps_wr_en_q, --ps_wr_en,
PS_PROTO_SELECT_IN => proto_select,
PS_BUSY_OUT => ps_busy,
PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN,
PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN,
- TC_DATA_OUT => tc_data,
- TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => TC_DATA_OUT,
+ TC_RD_EN_IN => TC_RD_EN_IN,
TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT,
- TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT,
+ TC_FRAME_TYPE_OUT => frame_type, --TC_FRAME_TYPE_OUT,
TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT,
- TC_IDENT_OUT => TC_IDENT_OUT,
+
TC_DEST_MAC_OUT => TC_DEST_MAC_OUT,
TC_DEST_IP_OUT => TC_DEST_IP_OUT,
TC_DEST_UDP_OUT => TC_DEST_UDP_OUT,
TC_SRC_IP_OUT => TC_SRC_IP_OUT,
TC_SRC_UDP_OUT => TC_SRC_UDP_OUT,
+ TC_IP_SIZE_OUT => TC_IP_SIZE_OUT,
+ TC_UDP_SIZE_OUT => TC_UDP_SIZE_OUT,
+ TC_FLAGS_OFFSET_OUT => TC_FLAGS_OFFSET_OUT,
+
+ TC_BUSY_IN => TC_BUSY_IN,
MC_BUSY_IN => mc_busy,
RECEIVED_FRAMES_OUT => SELECT_REC_FRAMES_OUT,
MAKE_RESET_OUT => MAKE_RESET_OUT,
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
-
-- input for statistics from outside
STAT_DATA_IN => stat_data,
STAT_ADDR_IN => stat_addr,
DEBUG_OUT => dbg_ps
);
-TC_DATA_OUT <= tc_data;
+TC_FRAME_TYPE_OUT <= frame_type when flow_current_state = TRANSMIT_CTRL else x"0008";
-- gk 07.11.11
-- do not select any response constructors when dropping a frame
else
disable_redirect <= '0';
end if;
- else
- disable_redirect <= disable_redirect;
end if;
end if;
end process DISABLE_REDIRECT_PROC;
end if;
-- gk 16.11.11
when CHECK_TYPE =>
- if (link_current_state = ACTIVE) then
+ redirect_state <= x"1";
+ if (link_current_state = ACTIVE) then
redirect_next_state <= CHECK_BUSY;
elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
redirect_next_state <= CHECK_BUSY;
when DROP =>
redirect_state <= x"7";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE; --FINISH;
+ redirect_next_state <= FINISH;
else
redirect_next_state <= DROP;
end if;
when LOAD =>
redirect_state <= x"2";
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
- redirect_next_state <= WAIT_ONE; --FINISH;
+ redirect_next_state <= FINISH;
else
redirect_next_state <= LOAD;
end if;
else
redirect_next_state <= BUSY;
end if;
-
- when WAIT_ONE =>
- redirect_state <= x"f";
- redirect_next_state <= FINISH;
when FINISH =>
redirect_state <= x"4";
if rising_edge(CLK) then
if (RESET = '1') then
RC_LOADING_DONE_OUT <= '0';
- elsif (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then
+ elsif (RC_DATA_IN(8) = '1' and ps_wr_en = '1') then
RC_LOADING_DONE_OUT <= '1';
else
RC_LOADING_DONE_OUT <= '0';
PS_WR_EN_PROC : process(CLK)
begin
if rising_edge(CLK) then
- ps_wr_en <= rc_rd_en;
- ps_wr_en_q <= ps_wr_en;
- ps_wr_en_qq <= ps_wr_en_q;
+ ps_wr_en <= rc_rd_en;
+ ps_wr_en_q <= ps_wr_en;
end if;
end process PS_WR_EN_PROC;
loaded_bytes_ctr <= (others => '0');
elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
- else
- loaded_bytes_ctr <= loaded_bytes_ctr;
end if;
end if;
end process LOADED_BYTES_CTR_PROC;
end if;
end process FLOW_MACHINE_PROC;
-FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data)
+FLOW_MACHINE : process(flow_current_state, PC_TRANSMIT_ON_IN, PC_SOD_IN, TC_TRANSMIT_DONE_IN, ps_response_ready)
begin
- case flow_current_state is
+ case flow_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if (ps_response_ready = '1') and (PC_TRANSMIT_ON_IN = '0') then
+ flow_next_state <= TRANSMIT_CTRL;
+ elsif (PC_SOD_IN = '1') then -- pottential loss of frames
+ flow_next_state <= TRANSMIT_DATA;
+ else
+ flow_next_state <= IDLE;
+ end if;
+
+ when TRANSMIT_DATA =>
+ state <= x"2";
+ if (TC_TRANSMIT_DONE_IN = '1') then
+ flow_next_state <= CLEANUP;
+ else
+ flow_next_state <= TRANSMIT_DATA;
+ end if;
+
+ when TRANSMIT_CTRL =>
+ state <= x"3";
+ if (TC_TRANSMIT_DONE_IN = '1') then
+ flow_next_state <= CLEANUP;
+ else
+ flow_next_state <= TRANSMIT_CTRL;
+ end if;
+
+ when CLEANUP =>
+ state <= x"4";
+ flow_next_state <= IDLE;
- when IDLE =>
- if (ps_response_ready = '1') then
- flow_next_state <= TRANSMIT_CTRL;
- else
- flow_next_state <= IDLE;
- end if;
-
- when TRANSMIT_CTRL =>
- if (tc_data(8) = '1') then
- flow_next_state <= WAIT_FOR_FC;
- else
- flow_next_state <= TRANSMIT_CTRL;
- end if;
-
- when WAIT_FOR_FC =>
- if (TC_TRANSMIT_DONE_IN = '1') then
- flow_next_state <= CLEANUP;
- else
- flow_next_state <= WAIT_FOR_FC;
- end if;
+ end case;
+end process FLOW_MACHINE;
- when CLEANUP =>
- flow_next_state <= IDLE;
+TC_TRANSMIT_DATA_OUT <= '1' when (flow_current_state = TRANSMIT_DATA) else '0';
+TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0';
- end case;
-end process FLOW_MACHINE;
+mc_busy <= '0' when flow_current_state = IDLE else '1';
-process(CLK)
+NOTHING_SENT_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (flow_current_state = IDLE and ps_response_ready = '1') then
- TC_TRANSMIT_CTRL_OUT <= '1';
- else
- TC_TRANSMIT_CTRL_OUT <= '0';
- end if;
-
- if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then
- mc_busy <= '1';
+ if (RESET = '1' or TC_TRANSMIT_DONE_IN = '1') then
+ nothing_sent_ctr <= (others => '0');
else
- mc_busy <= '0';
+ nothing_sent_ctr <= nothing_sent_ctr + x"1";
end if;
end if;
-end process;
---TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0';
---TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = IDLE and ps_response_ready = '1') else '0';
+end process NOTHING_SENT_CTR_PROC;
---mc_busy <= '0' when flow_current_state = IDLE else '1';
---mc_busy <= '1' when flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC else '0';
+NOTHING_SENT_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ nothing_sent <= '0';
+ elsif (nothing_sent_ctr = x"ffff_ffff") then
+ nothing_sent <= '1';
+ end if;
+ end if;
+end process NOTHING_SENT_PROC;
--***********************
-- LINK STATE CONTROL
if (g_SIMULATE = 0) then
link_current_state <= INACTIVE;
else
- link_current_state <= ACTIVE; --GET_ADDRESS; --ACTIVE;
+ link_current_state <= GET_ADDRESS; --ACTIVE;
end if;
else
link_current_state <= link_next_state;
end if;
end process;
-LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr)
+LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, tsm_ready, link_ok_timeout_ctr, PC_READY_IN)
begin
case link_current_state is
if (PCS_AN_COMPLETE_IN = '0') then
link_next_state <= INACTIVE;
else
- link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
+ if (PC_READY_IN = '1') then
+ link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
+ else
+ link_next_state <= FINALIZE;
+ end if;
end if;
when WAIT_FOR_BOOT =>
elsif (link_current_state = TIMEOUT) then
link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1";
end if;
-
- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then
- link_ok <= '1';
- else
- link_ok <= '0';
- end if;
-
- if (link_current_state = GET_ADDRESS) then
- dhcp_start <= '1';
- else
- dhcp_start <= '0';
- end if;
end if;
end process LINK_OK_CTR_PROC;
---link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0';
+link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) or (link_current_state = WAIT_FOR_BOOT) else '0';
WAIT_CTR_PROC : process(CLK)
begin
end if;
end process WAIT_CTR_PROC;
---dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
-
---LINK_DOWN_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- link_down_ctr <= (others => '0');
--- link_down_ctr_lock <= '0';
--- elsif (PCS_AN_COMPLETE_IN = '1') then
--- link_down_ctr_lock <= '0';
--- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then
--- link_down_ctr <= link_down_ctr + x"1";
--- link_down_ctr_lock <= '1';
--- end if;
--- end if;
---end process LINK_DOWN_CTR_PROC;
-
-MC_LINK_OK_OUT <= link_ok; -- or nothing_sent;
+dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0';
+
+LINK_DOWN_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ link_down_ctr <= (others => '0');
+ link_down_ctr_lock <= '0';
+ elsif (PCS_AN_COMPLETE_IN = '1') then
+ link_down_ctr_lock <= '0';
+ elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then
+ link_down_ctr <= link_down_ctr + x"1";
+ link_down_ctr_lock <= '1';
+ end if;
+ end if;
+end process LINK_DOWN_CTR_PROC;
+
+MC_LINK_OK_OUT <= link_ok or nothing_sent;
-- END OF LINK STATE CONTROL
--*************
-- GENERATE MAC_ADDRESS
g_MY_MAC <= unique_id(31 downto 8) & x"be0002";
---g_MAX_FRAME_SIZE <= x"0578";
+g_MAX_FRAME_SIZE <= x"0578";
--g_MAX_PACKET_SIZE <= x"fa00" when g_SIMULATE = 0 else x"0600";
--
TSMAC_CONTROLLER : trb_net16_gbe_mac_control
port map(
- CLK => CLK,
+ CLK => CLK,
RESET => RESET,
-- signals to/from main controller
TSM_HREADY_N_IN => TSM_HREADY_N_IN,
TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN,
- DEBUG_OUT => open
+ DEBUG_OUT => mac_control_debug
);
--DEBUG_OUT <= mac_control_debug;
-process(CLK)
-begin
- if rising_edge(CLK) then
- if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then
- tsm_reconf <= '1';
- else
- tsm_reconf <= '0';
- end if;
- end if;
-end process;
---tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0';
+
+tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '1') else '0';
TSM_HADDR_OUT <= tsm_haddr;
TSM_HCS_N_OUT <= tsm_hcs_n;
-- STATISTICS
-- *****
---
---CTRS_GEN : for n in 0 to 15 generate
---
--- CTR_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- arr(n) <= (others => '0');
--- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then
--- arr(n) <= arr(n) + x"1";
--- end if;
--- end if;
--- end process CTR_PROC;
---
---end generate CTRS_GEN;
---
---STAT_VEC_SYNC : signal_sync
---generic map (
--- WIDTH => 32,
--- DEPTH => 2
---)
---port map (
--- RESET => RESET,
--- CLK0 => CLK,
--- CLK1 => CLK,
--- D_IN => TSM_RX_STAT_VEC_IN,
--- D_OUT => rx_stat_vec_q
---);
---
---
---STAT_VEC_EN_SYNC : pulse_sync
---port map(
--- CLK_A_IN => CLK_125,
--- RESET_A_IN => RESET,
--- PULSE_A_IN => TSM_RX_STAT_EN_IN,
--- CLK_B_IN => CLK,
--- RESET_B_IN => RESET,
--- PULSE_B_OUT => rx_stat_en_q
---);
---
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (rx_stat_en_q = '1') then
--- stats_next_state <= LOAD_VECTOR;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_VECTOR =>
--- --if (stat_ack = '1') then
--- if (stats_ctr = 15) then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_VECTOR;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---STATS_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (stats_current_state = IDLE) then
--- stats_ctr <= 0;
--- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then
--- stats_ctr <= stats_ctr + 1;
--- end if;
--- end if;
---end process STATS_CTR_PROC;
---
-----stat_data <= arr(stats_ctr);
---
---stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8));
---
---stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
---stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24);
---stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16);
---stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8);
---stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0);
+
+CTRS_GEN : for n in 0 to 15 generate
+
+ CTR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ arr(n) <= (others => '0');
+ elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then
+ arr(n) <= arr(n) + x"1";
+ end if;
+ end if;
+ end process CTR_PROC;
+
+end generate CTRS_GEN;
+
+STAT_VEC_SYNC : signal_sync
+generic map (
+ WIDTH => 32,
+ DEPTH => 2
+)
+port map (
+ RESET => RESET,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_IN => TSM_RX_STAT_VEC_IN,
+ D_OUT => rx_stat_vec_q
+);
+
+
+STAT_VEC_EN_SYNC : pulse_sync
+port map(
+ CLK_A_IN => CLK_125,
+ RESET_A_IN => RESET,
+ PULSE_A_IN => TSM_RX_STAT_EN_IN,
+ CLK_B_IN => CLK,
+ RESET_B_IN => RESET,
+ PULSE_B_OUT => rx_stat_en_q
+);
+
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (rx_stat_en_q = '1') then
+ stats_next_state <= LOAD_VECTOR;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_VECTOR =>
+ --if (stat_ack = '1') then
+ if (stats_ctr = 15) then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_VECTOR;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+STATS_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (stats_current_state = IDLE) then
+ stats_ctr <= 0;
+ elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then
+ stats_ctr <= stats_ctr + 1;
+ end if;
+ end if;
+end process STATS_CTR_PROC;
+
+--stat_data <= arr(stats_ctr);
+
+stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8));
+
+stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
+
+stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24);
+stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16);
+stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8);
+stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0);
-- **** debug
---FRAME_WAITING_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- frame_waiting_ctr <= (others => '0');
--- elsif (RC_FRAME_WAITING_IN = '1') then
--- frame_waiting_ctr <= frame_waiting_ctr + x"1";
--- end if;
--- end if;
---end process FRAME_WAITING_CTR_PROC;
---
---SAVE_VALUES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- ps_busy_q <= (others => '0');
--- rc_frame_proto_q <= (others => '0');
--- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then
--- ps_busy_q <= ps_busy;
--- rc_frame_proto_q <= RC_FRAME_PROTO_IN;
--- end if;
--- end if;
---end process SAVE_VALUES_PROC;
---
---
---DEBUG_OUT(3 downto 0) <= link_state;
---DEBUG_OUT(7 downto 4) <= state;
---DEBUG_OUT(11 downto 8) <= redirect_state;
---DEBUG_OUT(15 downto 12) <= link_state;
---DEBUG_OUT(23 downto 16) <= frame_waiting_ctr(7 downto 0);
---DEBUG_OUT(27 downto 24) <= (others => '0'); --ps_busy_q;
---DEBUG_OUT(31 downto 28) <= (others => '0'); --rc_frame_proto_q;
---DEBUG_OUT(63 downto 32) <= dbg_ps(31 downto 0) or dbg_ps(63 downto 32);
+FRAME_WAITING_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ frame_waiting_ctr <= (others => '0');
+ elsif (RC_FRAME_WAITING_IN = '1') then
+ frame_waiting_ctr <= frame_waiting_ctr + x"1";
+ end if;
+ end if;
+end process FRAME_WAITING_CTR_PROC;
+
+SAVE_VALUES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ ps_busy_q <= (others => '0');
+ rc_frame_proto_q <= (others => '0');
+ elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then
+ ps_busy_q <= ps_busy;
+ rc_frame_proto_q <= RC_FRAME_PROTO_IN;
+ end if;
+ end if;
+end process SAVE_VALUES_PROC;
+
+
+DEBUG_OUT(3 downto 0) <= link_state;
+DEBUG_OUT(7 downto 4) <= state;
+DEBUG_OUT(11 downto 8) <= redirect_state;
+DEBUG_OUT(15 downto 12) <= link_state;
+DEBUG_OUT(23 downto 16) <= frame_waiting_ctr(7 downto 0);
+DEBUG_OUT(27 downto 24) <= (others => '0'); --ps_busy_q;
+DEBUG_OUT(31 downto 28) <= (others => '0'); --rc_frame_proto_q;
+DEBUG_OUT(63 downto 32) <= dbg_ps(31 downto 0) or dbg_ps(63 downto 32);
-- ****
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use IEEE.std_logic_arith.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
-
-entity trb_net16_gbe_packet_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_WR_EN_OUT : out std_logic;
- TC_DATA_OUT : out std_logic_vector(7 downto 0);
- TC_H_READY_IN : in std_logic;
- TC_READY_IN : in std_logic;
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- TC_EOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_packet_constr;
-
-architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_GBE_group";
-
-component fifo_64kx9
-port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
--- FIFO for SubEventHeader information
-component fifo_16kx8 is
-port (
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-signal df_wr_en : std_logic;
-signal df_rd_en : std_logic;
-signal df_q : std_logic_vector(7 downto 0);
-signal df_q_reg : std_logic_vector(7 downto 0);
-signal df_empty : std_logic;
-signal df_full : std_logic;
-
-signal fc_data : std_logic_vector(7 downto 0);
-signal fc_wr_en : std_logic;
-signal fc_sod : std_logic;
-signal fc_eod : std_logic;
-signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!
-signal fc_flags_offset : std_logic_vector(15 downto 0);
-
-signal shf_data : std_logic_vector(7 downto 0);
-signal shf_wr_en : std_logic;
-signal shf_rd_en : std_logic;
-signal shf_q : std_logic_vector(7 downto 0);
-signal shf_empty : std_logic;
-signal shf_full : std_logic;
-
-type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);
-signal constructCurrentState, constructNextState : constructStates;
-signal constr_state : std_logic_vector(3 downto 0);
-signal all_int_ctr : integer range 0 to 31;
-signal all_ctr : std_logic_vector(4 downto 0);
-
-type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);
-signal saveSubCurrentState, saveSubNextState : saveSubStates;
-signal save_state : std_logic_vector(3 downto 0);
-signal sub_int_ctr : integer range 0 to 31;
-signal sub_ctr : std_logic_vector(4 downto 0);
-signal my_int_ctr : integer range 0 to 3;
-signal my_ctr : std_logic_vector(1 downto 0);
-
-type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);
-signal loadCurrentState, loadNextState: loadStates;
-signal load_state : std_logic_vector(3 downto 0);
-
-signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination
-signal queue_size_temp : std_logic_vector(31 downto 0);
-signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid
-signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame
-signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf
-signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted
-signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent
-signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet
-signal size_left : std_logic_vector(31 downto 0);
-signal fc_ip_size : std_logic_vector(15 downto 0);
-signal fc_udp_size : std_logic_vector(15 downto 0);
-signal max_frame_size : std_logic_vector(15 downto 0);
-signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term
-signal debug : std_logic_vector(63 downto 0);
-signal pc_ready : std_logic;
-
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-signal rst_after_sub_comb : std_logic; -- gk 08.04.10
-signal rst_after_sub : std_logic; -- gk 08.04.10
-signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10
-signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10
-signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10
-
--- gk 26.07.10
-signal load_eod : std_logic;
-signal load_eod_q : std_logic;
-
--- gk 07.10.10
-signal df_eod : std_logic;
-
--- gk 04.12.10
-signal first_sub_in_multi : std_logic;
-signal from_divide_state : std_logic;
-signal disable_prep : std_logic;
-
-begin
-
-
-PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0';
-
-my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order
-load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10
-
-all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging
-sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging
-my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging
-
-max_frame_size <= PC_MAX_FRAME_SIZE_IN;
-
--- Ready signal for PacketConstructor
-pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';
-
--- store event information on Start_of_Subevent
-THE_EVT_INFO_STORE_PROC: process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if (RESET = '1') then -- gk 31.05.10
- pc_sub_size <= (others => '0');
- pc_trig_nr <= (others => '0');
- elsif( PC_START_OF_SUB_IN = '1' ) then
- pc_sub_size <= PC_SUB_SIZE_IN;
- pc_trig_nr <= PC_TRIG_NR_IN;
- end if;
- end if;
-end process;
-
--- gk 07.10.10
-df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))
- or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))
- else '0';
-
--- Data FIFO for incoming packet data from IPU buffer
--- gk 26.07.10
-DATA_FIFO : fifo_64kx9
-port map(
- Data(7 downto 0) => PC_DATA_IN,
- Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10
- WrClock => CLK,
- RdClock => CLK,
- WrEn => df_wr_en,
- RdEn => df_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q(7 downto 0) => df_q,
- Q(8) => load_eod,
- Empty => df_empty,
- Full => df_full
-);
-
-LOAD_EOD_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- load_eod_q <= '0';
- else
- load_eod_q <= load_eod;
- end if;
- end if;
-end process LOAD_EOD_PROC;
-
--- Write enable for the data FIFO
--- !!!combinatorial signal!!!
--- could be avoided as IPU2GBE does only send data in case of PC_READY.
-df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD))
- else '0';
-
--- Output register for data FIFO
-dfQProc : process(CLK)
-begin
- if rising_edge(CLK) then
- df_q_reg <= df_q;
- end if;
-end process dfQProc;
-
--- Construction state machine
-constructMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- constructCurrentState <= CIDLE;
- else
- constructCurrentState <= constructNextState;
- end if;
- end if;
-end process constructMachineProc;
-
-constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)
-begin
- case constructCurrentState is
- when CIDLE =>
- constr_state <= x"0";
- --if( PC_WR_EN_IN = '1' ) then
- -- gk 04.12.10
- if (PC_START_OF_SUB_IN = '1') then
-
- constructNextState <= SAVE_DATA;
- else
- constructNextState <= CIDLE;
- end if;
- when SAVE_DATA =>
- constr_state <= x"1";
- if( PC_END_OF_DATA_IN = '1') then
- constructNextState <= WAIT_FOR_LOAD;
- else
- constructNextState <= SAVE_DATA;
- end if;
- when WAIT_FOR_LOAD =>
- constr_state <= x"2";
- if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted
- constructNextState <= CIDLE;
- else
- constructNextState <= WAIT_FOR_LOAD;
- end if;
- when others =>
- constr_state <= x"f";
- constructNextState <= CIDLE;
- end case;
-end process constructMachine;
-
---***********************
--- SIZE COUNTERS FOR SAVING SIDE
---***********************
-
--- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size
--- that's why they are removed if pc_padding flag is asserted
-sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')
- else (x"c" + pc_sub_size); -- subevent headers + data
-
--- BUG HERE BUG HERE BUG HERE BUG HERE
--- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents
-queueSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then
- if (RESET = '1') or (loadCurrentState = CLEANUP) then
- queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination
- elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then
- queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers
- end if;
- end if;
-end process queueSizeProc;
-
-
---***********************
--- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION
---***********************
-
-loadMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- loadCurrentState <= LIDLE;
- else
- loadCurrentState <= loadNextState;
- end if;
- end if;
-end process loadMachineProc;
-
-loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,
- sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN,
- max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,
- delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)
-begin
- case loadCurrentState is
- when LIDLE =>
- load_state <= x"0";
- if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then
- loadNextState <= WAIT_FOR_FC;
- else
- loadNextState <= LIDLE;
- end if;
- when WAIT_FOR_FC =>
- load_state <= x"1";
- if (TC_H_READY_IN = '1') then
- loadNextState <= PUT_Q_LEN;
- else
- loadNextState <= WAIT_FOR_FC;
- end if;
- when PUT_Q_LEN =>
- load_state <= x"2";
- if (all_int_ctr = 3) then
- loadNextState <= PUT_Q_DEC;
- else
- loadNextState <= PUT_Q_LEN;
- end if;
- when PUT_Q_DEC =>
- load_state <= x"3";
- if (all_int_ctr = 3) then
- loadNextState <= LOAD_SUB;
- else
- loadNextState <= PUT_Q_DEC;
- end if;
- when LOAD_SUB =>
- load_state <= x"4";
- if (bytes_loaded = max_frame_size - 1) then
- loadNextState <= DIVIDE;
- elsif (all_int_ctr = 15) then
- loadNextState <= PREP_DATA;
- else
- loadNextState <= LOAD_SUB;
- end if;
- when PREP_DATA =>
- load_state <= x"5";
- loadNextState <= LOAD_DATA;
- when LOAD_DATA =>
- load_state <= x"6";
--- if (bytes_loaded = max_frame_size - 1) then
--- loadNextState <= DIVIDE;
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '1') then
--- if (size_left = x"0000_0023") then
--- loadNextState <= LOAD_TERM;
--- elsif (load_eod_q = '1') then
--- loadNextState <= LOAD_SUB;
--- else
--- loadNextState <= LOAD_DATA;
--- end if;
--- else
--- if (load_eod_q = '1') then
--- loadNextState <= LOAD_TERM;
--- else
--- loadNextState <= LOAD_DATA;
--- end if;
--- end if;
- if (bytes_loaded = max_frame_size - 1) then
- loadNextState <= DIVIDE;
- -- gk 07.10.10
- elsif (load_eod_q = '1') then
- if (MULT_EVT_ENABLE_IN = '1') then
- if (size_left < x"0000_0030") then
- loadNextState <= LOAD_TERM;
- else
- loadNextState <= LOAD_SUB;
- end if;
- else
- loadNextState <= LOAD_TERM;
- end if;
- else
- loadNextState <= LOAD_DATA;
- end if;
- when DIVIDE =>
- load_state <= x"7";
- if (TC_H_READY_IN = '1') then
- if (divide_position = "00") then
- loadNextState <= PREP_DATA;
- elsif (divide_position = "01") then
- loadNextState <= LOAD_SUB;
- else
- loadNextState <= LOAD_TERM;
- end if;
- else
- loadNextState <= DIVIDE;
- end if;
- when LOAD_TERM =>
- load_state <= x"8";
- if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then
- loadNextState <= DIVIDE;
- elsif (all_int_ctr = 31) then
- loadNextState <= CLEANUP;
- else
- loadNextState <= LOAD_TERM;
- end if;
- -- gk 28.04.10
- when CLEANUP =>
- load_state <= x"9";
- if (PC_DELAY_IN = x"0000_0000") then
- loadNextState <= LIDLE;
- else
- loadNextState <= DELAY;
- end if;
- -- gk 28.04.10
- when DELAY =>
- load_state <= x"a";
- if (delay_ctr = x"0000_0000") then
- loadNextState <= LIDLE;
- else
- loadNextState <= DELAY;
- end if;
- when others =>
- load_state <= x"f";
- loadNextState <= LIDLE;
- end case;
-end process loadMachine;
-
--- gk 04.12.10
-firstSubInMultiProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LOAD_TERM) then
- first_sub_in_multi <= '1';
- elsif (loadCurrentState = LOAD_DATA) then
- first_sub_in_multi <= '0';
- end if;
- end if;
-end process;
-
--- gk 04.12.10
-fromDivideStateProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- from_divide_state <= '0';
- elsif (loadCurrentState = DIVIDE) then
- from_divide_state <= '1';
- elsif (loadCurrentState = PREP_DATA) then
- from_divide_state <= '0';
- end if;
- end if;
-end process fromDivideStateProc;
-
-
-dividePositionProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- divide_position <= "00";
- elsif (bytes_loaded = max_frame_size - 1) then
- if (loadCurrentState = LIDLE) then
- divide_position <= "00";
- disable_prep <= '0'; -- gk 05.12.10
- elsif (loadCurrentState = LOAD_DATA) then
- -- gk 05.12.10
- -- gk 26.07.10
- if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then
- if (size_left > x"0000_0028") then
- divide_position <= "01";
- disable_prep <= '0'; -- gk 05.12.10
- else
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- end if;
- else
- divide_position <= "00"; -- still data loaded divide on data
- disable_prep <= '1'; -- gk 05.12.10
- end if;
- elsif (loadCurrentState = LOAD_SUB) then
- if (all_int_ctr = 15) then
- divide_position <= "00";
- disable_prep <= '1'; -- gk 05.12.10
- else
- divide_position <= "01";
- disable_prep <= '0'; -- gk 05.12.10
- end if;
- elsif (loadCurrentState = LOAD_TERM) then
- divide_position <= "11";
- disable_prep <= '0'; -- gk 05.12.10
- end if;
- elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep
- disable_prep <= '0';
- end if;
-
- end if;
-end process dividePositionProc;
-
-allIntCtrProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then -- gk 31.05.10
- all_int_ctr <= 0;
- else
- case loadCurrentState is
-
- when LIDLE => all_int_ctr <= 0;
-
- when WAIT_FOR_FC => all_int_ctr <= 0;
-
- when PUT_Q_LEN =>
- if (all_int_ctr = 3) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when PUT_Q_DEC =>
- if (all_int_ctr = 3) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when LOAD_SUB =>
- if (all_int_ctr = 15) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when LOAD_DATA => all_int_ctr <= 0;
-
- when LOAD_TERM =>
- if (all_int_ctr = 31) then
- all_int_ctr <= 0;
- else
- all_int_ctr <= all_int_ctr + 1;
- end if;
-
- when DIVIDE => null;
-
- when CLEANUP => all_int_ctr <= 0;
-
- when PREP_DATA => all_int_ctr <= 0;
-
- when DELAY => all_int_ctr <= 0;
- end case;
- end if;
- end if;
-end process allIntCtrProc;
-
-dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded,
- sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q)
-begin
- if (RESET = '1') then
- df_rd_en <= '0';
- elsif (loadCurrentState = LOAD_DATA) then
--- if (bytes_loaded = max_frame_size - x"1") then
--- df_rd_en <= '0';
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then
--- df_rd_en <= '0';
--- -- gk 07.10.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then
--- df_rd_en <= '0';
--- else
--- df_rd_en <= '1';
--- end if;
- if (bytes_loaded = max_frame_size - x"1") then
- df_rd_en <= '0';
- -- gk 26.07.10
- --elsif (load_eod = '1') or (load_eod_q = '1') then
- elsif (load_eod_q = '1') then
- df_rd_en <= '0';
--- elsif (sub_bytes_loaded = sub_size_loaded) then
--- df_rd_en <= '0';
- else
- df_rd_en <= '1';
- end if;
-
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then
- df_rd_en <= '1';
- elsif (loadCurrentState = PREP_DATA) then
- df_rd_en <= '1';
- else
- df_rd_en <= '0';
- end if;
-end process dfRdEnProc;
-
-shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)
-begin
- if (RESET = '1') then -- gk 31.05.10
- shf_rd_en <= '0';
- elsif (loadCurrentState = LOAD_SUB) then
- shf_rd_en <= '1';
- elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then
- shf_rd_en <= '1';
- elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then
- shf_rd_en <= '1';
- else
- shf_rd_en <= '0';
- end if;
-end process shfRdEnProc;
-
-
-fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)
-begin
- if (RESET = '1') then -- gk 31.05.10
- fc_wr_en <= '0';
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
- fc_wr_en <= '1';
- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then
- fc_wr_en <= '1';
- -- gk 04.12.10
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
- fc_wr_en <= '1';
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
- fc_wr_en <= '1';
- else
- fc_wr_en <= '0';
- end if;
-end process fcWrEnProc;
-
-
--- was all_int_ctr
-fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)
-begin
- case loadCurrentState is
- when LIDLE => fc_data <= x"af";
- when WAIT_FOR_FC => fc_data <= x"bf";
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
- when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
- when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);
- when LOAD_SUB => fc_data <= shf_q;
- when PREP_DATA => fc_data <= df_q_reg;
- when LOAD_DATA => fc_data <= df_q_reg;
- when LOAD_TERM => fc_data <= shf_q;
- when DIVIDE => fc_data <= x"cf";
- when CLEANUP => fc_data <= x"df";
- when others => fc_data <= x"00";
- end case;
-end process fcDataProc;
-
--- delay counters
--- gk 28.04.10
-DELAY_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (loadCurrentState = LIDLE)) then
- delay_ctr <= PC_DELAY_IN;
- elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then
- delay_ctr <= delay_ctr - x"1";
- end if;
- end if;
-end process DELAY_CTR_PROC;
-
--- gk 28.04.10
-TICKS_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then
- ticks_ctr <= x"00";
- elsif (loadCurrentState = DELAY) then
- ticks_ctr <= ticks_ctr + x"1";
- end if;
- end if;
-end process TICKS_CTR_PROC;
-
-
---***********************
--- SIZE COUNTERS FOR LOADING SIDE
---***********************
-
-queue_size_temp <= queue_size - x"20"; -- size of data without termination
-
--- gk 08.04.10
-rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or
- ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded)
- else '0';
-
--- gk 08.04.10
-RST_AFTER_SUB_PROC : process(CLK)
-begin
- if(rising_edge(CLK)) then
- if(RESET = '1') then
- rst_after_sub <= '0';
- else
- rst_after_sub <= rst_after_sub_comb;
- end if;
- end if;
-end process RST_AFTER_SUB_PROC;
-
--- counts all bytes loaded to divide data into frames
-bytesLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then
- bytes_loaded <= x"0000";
- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then
- bytes_loaded <= bytes_loaded + x"1";
- -- gk 05.12.10
--- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then
--- bytes_loaded <= bytes_loaded + x"1";
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then
- bytes_loaded <= bytes_loaded + x"1";
- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then
- bytes_loaded <= bytes_loaded + x"1";
- end if;
- end if;
-end process bytesLoadedProc;
-
--- size of subevent loaded from memory
-subSizeLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10
- sub_size_loaded <= x"00000000";
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then
- -- was all_int_ctr
- -- gk 08.04.10 my_int_ctr changed to load_int_ctr
- sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;
- -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo
- elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then
- sub_size_loaded <= sub_size_loaded + x"4";
- end if;
- end if;
-end process subSizeLoadedProc;
-
--- counts only raw data bytes being loaded
-subBytesLoadedProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10
- sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count
- elsif (loadCurrentState = LOAD_DATA) then
- sub_bytes_loaded <= sub_bytes_loaded + x"1";
- end if;
- end if;
-end process subBytesLoadedProc;
-
--- counts the size of the large udp packet
-actualPacketProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- actual_packet_size <= x"0008";
- elsif (fc_wr_en = '1') then
- actual_packet_size <= actual_packet_size + x"1";
- end if;
- end if;
-end process actualPacketProc;
-
-actualQueueSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = CLEANUP) then
- actual_queue_size <= (others => '0');
- elsif (loadCurrentState = LIDLE) then
- actual_queue_size <= queue_size;
- end if;
- end if;
-end process actualQueueSizeProc;
-
--- amount of bytes left to send in current packet
-sizeLeftProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = CLEANUP) then
- size_left <= (others => '0');
- elsif (loadCurrentState = LIDLE) then
- size_left <= queue_size;
- elsif (fc_wr_en = '1') then
- size_left <= size_left - 1;
- end if;
- end if;
-end process sizeLeftProc;
-
--- HOT FIX: don't rely on CTS information, count the packets on your own.
--- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.
-THE_FC_IDENT_COUNTER_PROC: process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- fc_ident <= (others => '0');
- elsif (PC_END_OF_DATA_IN = '1') then
- fc_ident <= fc_ident + 1;
- end if;
- end if;
-end process THE_FC_IDENT_COUNTER_PROC;
-
-fc_flags_offset(15 downto 14) <= "00";
-
-moreFragmentsProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- fc_flags_offset(13) <= '0';
- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
- if ((actual_queue_size - actual_packet_size) < max_frame_size) then
- fc_flags_offset(13) <= '0'; -- no more fragments
- else
- fc_flags_offset(13) <= '1'; -- more fragments
- end if;
- end if;
- end if;
-end process moreFragmentsProc;
-
-eodProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- fc_eod <= '0';
- elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then
- fc_eod <= '1';
- elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then
- fc_eod <= '1';
- elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then
- fc_eod <= '1';
- else
- fc_eod <= '0';
- end if;
- end if;
-end process eodProc;
-
-sodProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- fc_sod <= '0';
- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
- fc_sod <= '1';
- elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then
- fc_sod <= '1';
- else
- fc_sod <= '0';
- end if;
- end if;
-end process sodProc;
-
-offsetProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then
- fc_flags_offset(12 downto 0) <= (others => '0');
- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then
- fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);
- end if;
- end if;
-end process offsetProc;
-
-fcIPSizeProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET= '1') then
- fc_ip_size <= (others => '0');
- elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then
- if (size_left >= max_frame_size) then
- fc_ip_size <= max_frame_size;
- else
- fc_ip_size <= size_left(15 downto 0);
- end if;
- end if;
- end if;
-end process fcIPSizeProc;
-
-fcUDPSizeProc : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- fc_udp_size <= (others => '0');
- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then
- fc_udp_size <= queue_size(15 downto 0);
- end if;
- end if;
-end process fcUDPSizeProc;
-
-
---***********************
--- SUBEVENT HEADERS WRITE AND READ
---***********************
-
-SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3 --fifo_16kx8
-port map(
- Data => shf_data,
- WrClock => CLK,
- RdClock => CLK,
- WrEn => shf_wr_en,
- RdEn => shf_rd_en,
- Reset => RESET,
- RPReset => RESET,
- Q => shf_q,
- Empty => shf_empty,
- Full => shf_full
-);
-
--- write enable for SHF
-shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))
- else '0';
-
--- data multiplexing for SHF (convert 32bit LWs to 8bit)
--- CHANGED.
--- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.
-shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN,
- pc_trig_nr, my_int_ctr, fc_data)
-begin
- case saveSubCurrentState is
- when SIDLE => shf_data <= x"ac";
- when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);
- when SAVE_TERM => shf_data <= fc_data;
- when others => shf_data <= x"00";
- end case;
-end process shfDataProc;
-
-saveSubMachineProc : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- saveSubCurrentState <= SIDLE;
- else
- saveSubCurrentState <= saveSubNextState;
- end if;
- end if;
-end process saveSubMachineProc;
-
-saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN)
-begin
- case saveSubCurrentState is
- when SIDLE =>
- save_state <= x"0";
- if (PC_START_OF_SUB_IN = '1') then
- saveSubNextState <= SAVE_SIZE;
- -- this branch is dangerous!
- elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len
- saveSubNextState <= SAVE_TERM;
- else
- saveSubNextState <= SIDLE;
- end if;
- when SAVE_SIZE =>
- save_state <= x"1";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_DECODING;
- else
- saveSubNextState <= SAVE_SIZE;
- end if;
- when SAVE_DECODING =>
- save_state <= x"2";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_ID;
- else
- saveSubNextState <= SAVE_DECODING;
- end if;
- when SAVE_ID =>
- save_state <= x"3";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SAVE_TRIG_NR;
- else
- saveSubNextState <= SAVE_ID;
- end if;
- when SAVE_TRIG_NR =>
- save_state <= x"4";
- if (sub_int_ctr = 3) then
- saveSubNextState <= SIDLE;
- else
- saveSubNextState <= SAVE_TRIG_NR;
- end if;
- when SAVE_TERM =>
- save_state <= x"5";
- if (sub_int_ctr = 31) then
- saveSubNextState <= SIDLE;
- else
- saveSubNextState <= SAVE_TERM;
- end if;
- when others =>
- save_state <= x"f";
- saveSubNextState <= SIDLE;
- end case;
-end process;
-
--- This counter is used for breaking down 32bit information words into 8bit bytes for
--- storing them in the SHF.
--- It is also used for the termination 32byte sequence.
-subIntProc: process( CLK )
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (saveSubCurrentState = SIDLE) then
- sub_int_ctr <= 0;
- elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then
- sub_int_ctr <= 0;
- elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then
- sub_int_ctr <= 0;
- elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then
- sub_int_ctr <= sub_int_ctr + 1;
- end if;
- end if;
-end process subIntProc;
-
---debug(3 downto 0) <= constr_state;
---debug(7 downto 4) <= save_state;
---debug(11 downto 8) <= load_state;
---debug(27 downto 12) <= queue_size(15 downto 0);
---debug(28) <= df_full;
---debug(29) <= df_empty;
---debug(30) <= shf_full;
---debug(31) <= shf_empty;
---
---debug(47 downto 32) <= size_left(15 downto 0);
---debug(52 downto 48) <= all_ctr;
---debug(53) <= pc_ready;
-
--- outputs
-PC_READY_OUT <= pc_ready;
-TC_WR_EN_OUT <= fc_wr_en;
-TC_DATA_OUT <= fc_data;
-TC_IP_SIZE_OUT <= fc_ip_size;
-TC_UDP_SIZE_OUT <= fc_udp_size;
--- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);
--- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);
-TC_FLAGS_OFFSET_OUT <= fc_flags_offset;
-TC_SOD_OUT <= fc_sod;
-TC_EOD_OUT <= fc_eod;
-
-DEBUG_OUT <= debug;
-
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+use IEEE.std_logic_arith.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb_net16_hub_func.all;\r
+\r
+entity trb_net16_gbe_packet_constr is\r
+port(\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10\r
+ -- ports for user logic\r
+ PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic\r
+ PC_DATA_IN : in std_logic_vector(7 downto 0);\r
+ PC_READY_OUT : out std_logic;\r
+ PC_START_OF_SUB_IN : in std_logic;\r
+ PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10\r
+ PC_END_OF_DATA_IN : in std_logic;\r
+ PC_TRANSMIT_ON_OUT : out std_logic;\r
+ -- queue and subevent layer headers\r
+ PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap\r
+ PC_PADDING_IN : in std_logic; -- gk 29.03.10\r
+ PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap\r
+ PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap\r
+ PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!\r
+ PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap\r
+ PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP\r
+ PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10\r
+ -- FrameConstructor ports\r
+ TC_WR_EN_OUT : out std_logic;\r
+ TC_DATA_OUT : out std_logic_vector(7 downto 0);\r
+ TC_H_READY_IN : in std_logic;\r
+ TC_READY_IN : in std_logic;\r
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);\r
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);\r
+ TC_SOD_OUT : out std_logic;\r
+ TC_EOD_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end trb_net16_gbe_packet_constr;\r
+\r
+architecture trb_net16_gbe_packet_constr of trb_net16_gbe_packet_constr is\r
+\r
+--attribute HGROUP : string;\r
+--attribute HGROUP of trb_net16_gbe_packet_constr : architecture is "GBE_GBE_group";\r
+\r
+component fifo_64kx9\r
+port (\r
+ Data : in std_logic_vector(8 downto 0); \r
+ WrClock : in std_logic; \r
+ RdClock : in std_logic; \r
+ WrEn : in std_logic; \r
+ RdEn : in std_logic; \r
+ Reset : in std_logic; \r
+ RPReset : in std_logic; \r
+ Q : out std_logic_vector(8 downto 0); \r
+ Empty : out std_logic; \r
+ Full : out std_logic\r
+);\r
+end component;\r
+\r
+-- FIFO for SubEventHeader information\r
+component fifo_16kx8 is\r
+port (\r
+ Data : in std_logic_vector(7 downto 0); \r
+ WrClock : in std_logic; \r
+ RdClock : in std_logic; \r
+ WrEn : in std_logic; \r
+ RdEn : in std_logic; \r
+ Reset : in std_logic; \r
+ RPReset : in std_logic; \r
+ Q : out std_logic_vector(7 downto 0); \r
+ Empty : out std_logic; \r
+ Full : out std_logic\r
+);\r
+end component;\r
+\r
+signal df_wr_en : std_logic;\r
+signal df_rd_en : std_logic;\r
+signal df_q : std_logic_vector(7 downto 0);\r
+signal df_q_reg : std_logic_vector(7 downto 0);\r
+signal df_empty : std_logic;\r
+signal df_full : std_logic;\r
+\r
+signal fc_data : std_logic_vector(7 downto 0);\r
+signal fc_wr_en : std_logic;\r
+signal fc_sod : std_logic;\r
+signal fc_eod : std_logic;\r
+signal fc_ident : std_logic_vector(15 downto 0); -- change this to own counter!\r
+signal fc_flags_offset : std_logic_vector(15 downto 0);\r
+\r
+signal shf_data : std_logic_vector(7 downto 0);\r
+signal shf_wr_en : std_logic;\r
+signal shf_rd_en : std_logic;\r
+signal shf_q : std_logic_vector(7 downto 0);\r
+signal shf_empty : std_logic;\r
+signal shf_full : std_logic;\r
+\r
+type constructStates is (CIDLE, SAVE_DATA, WAIT_FOR_LOAD);\r
+signal constructCurrentState, constructNextState : constructStates;\r
+signal constr_state : std_logic_vector(3 downto 0);\r
+signal all_int_ctr : integer range 0 to 31;\r
+signal all_ctr : std_logic_vector(4 downto 0);\r
+\r
+type saveSubStates is (SIDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRIG_NR, SAVE_TERM);\r
+signal saveSubCurrentState, saveSubNextState : saveSubStates;\r
+signal save_state : std_logic_vector(3 downto 0);\r
+signal sub_int_ctr : integer range 0 to 31;\r
+signal sub_ctr : std_logic_vector(4 downto 0);\r
+signal my_int_ctr : integer range 0 to 3;\r
+signal my_ctr : std_logic_vector(1 downto 0);\r
+\r
+type loadStates is (LIDLE, WAIT_FOR_FC, PUT_Q_LEN, PUT_Q_DEC, LOAD_SUB, PREP_DATA, LOAD_DATA, DIVIDE, LOAD_TERM, CLEANUP, DELAY);\r
+signal loadCurrentState, loadNextState: loadStates;\r
+signal load_state : std_logic_vector(3 downto 0);\r
+\r
+signal queue_size : std_logic_vector(31 downto 0); -- sum of all subevents sizes plus their headers and queue headers and termination\r
+signal queue_size_temp : std_logic_vector(31 downto 0);\r
+signal actual_queue_size : std_logic_vector(31 downto 0); -- queue size used during loading process when queue_size is no more valid\r
+signal bytes_loaded : std_logic_vector(15 downto 0); -- size of actual constructing frame\r
+signal sub_size_to_save : std_logic_vector(31 downto 0); -- size of subevent to save to shf\r
+signal sub_size_loaded : std_logic_vector(31 downto 0); -- size of subevent actually being transmitted\r
+signal sub_bytes_loaded : std_logic_vector(31 downto 0); -- amount of bytes of actual subevent sent \r
+signal actual_packet_size : std_logic_vector(15 downto 0); -- actual size of whole udp packet\r
+signal size_left : std_logic_vector(31 downto 0);\r
+signal fc_ip_size : std_logic_vector(15 downto 0);\r
+signal fc_udp_size : std_logic_vector(15 downto 0);\r
+signal max_frame_size : std_logic_vector(15 downto 0);\r
+signal divide_position : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term\r
+signal debug : std_logic_vector(63 downto 0);\r
+signal pc_ready : std_logic;\r
+\r
+signal pc_sub_size : std_logic_vector(31 downto 0);\r
+signal pc_trig_nr : std_logic_vector(31 downto 0);\r
+signal rst_after_sub_comb : std_logic; -- gk 08.04.10\r
+signal rst_after_sub : std_logic; -- gk 08.04.10\r
+signal load_int_ctr : integer range 0 to 3; -- gk 08.04.10\r
+signal delay_ctr : std_logic_vector(31 downto 0); -- gk 28.04.10\r
+signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10\r
+\r
+-- gk 26.07.10\r
+signal load_eod : std_logic;\r
+signal load_eod_q : std_logic;\r
+\r
+-- gk 07.10.10\r
+signal df_eod : std_logic;\r
+\r
+-- gk 04.12.10\r
+signal first_sub_in_multi : std_logic;\r
+signal from_divide_state : std_logic;\r
+signal disable_prep : std_logic;\r
+\r
+begin\r
+\r
+\r
+PC_TRANSMIT_ON_OUT <= '1' when constructCurrentState = WAIT_FOR_LOAD else '0';\r
+\r
+my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order\r
+load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2))); -- gk 08.04.10\r
+\r
+all_ctr <= std_logic_vector(to_unsigned(all_int_ctr, all_ctr'length)); -- for debugging\r
+sub_ctr <= std_logic_vector(to_unsigned(sub_int_ctr, sub_ctr'length)); -- for debugging\r
+my_ctr <= std_logic_vector(to_unsigned(my_int_ctr, my_ctr'length)); -- for debugging\r
+\r
+max_frame_size <= PC_MAX_FRAME_SIZE_IN;\r
+\r
+-- Ready signal for PacketConstructor\r
+pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '0';\r
+\r
+-- store event information on Start_of_Subevent\r
+THE_EVT_INFO_STORE_PROC: process( CLK )\r
+begin\r
+ if( rising_edge(CLK) ) then\r
+ if (RESET = '1') then -- gk 31.05.10\r
+ pc_sub_size <= (others => '0');\r
+ pc_trig_nr <= (others => '0');\r
+ elsif( PC_START_OF_SUB_IN = '1' ) then\r
+ pc_sub_size <= PC_SUB_SIZE_IN;\r
+ pc_trig_nr <= PC_TRIG_NR_IN;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+-- gk 07.10.10\r
+df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))\r
+ or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))\r
+ else '0';\r
+\r
+-- Data FIFO for incoming packet data from IPU buffer\r
+-- gk 26.07.10\r
+DATA_FIFO : fifo_64kx9\r
+port map(\r
+ Data(7 downto 0) => PC_DATA_IN,\r
+ Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 07.10.10\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => df_wr_en,\r
+ RdEn => df_rd_en,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(7 downto 0) => df_q,\r
+ Q(8) => load_eod,\r
+ Empty => df_empty,\r
+ Full => df_full\r
+);\r
+\r
+LOAD_EOD_PROC : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ load_eod_q <= '0';\r
+ else\r
+ load_eod_q <= load_eod;\r
+ end if;\r
+ end if;\r
+end process LOAD_EOD_PROC;\r
+\r
+-- Write enable for the data FIFO\r
+-- !!!combinatorial signal!!!\r
+-- could be avoided as IPU2GBE does only send data in case of PC_READY.\r
+df_wr_en <= '1' when ((PC_WR_EN_IN = '1') and (constructCurrentState /= WAIT_FOR_LOAD)) \r
+ else '0';\r
+\r
+-- Output register for data FIFO\r
+dfQProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ df_q_reg <= df_q;\r
+ end if;\r
+end process dfQProc;\r
+\r
+-- Construction state machine\r
+constructMachineProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ constructCurrentState <= CIDLE;\r
+ else\r
+ constructCurrentState <= constructNextState;\r
+ end if;\r
+ end if;\r
+end process constructMachineProc;\r
+\r
+constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)\r
+begin\r
+ case constructCurrentState is\r
+ when CIDLE =>\r
+ constr_state <= x"0";\r
+ --if( PC_WR_EN_IN = '1' ) then\r
+ -- gk 04.12.10\r
+ if (PC_START_OF_SUB_IN = '1') then\r
+\r
+ constructNextState <= SAVE_DATA;\r
+ else\r
+ constructNextState <= CIDLE;\r
+ end if;\r
+ when SAVE_DATA =>\r
+ constr_state <= x"1";\r
+ if( PC_END_OF_DATA_IN = '1') then\r
+ constructNextState <= WAIT_FOR_LOAD;\r
+ else\r
+ constructNextState <= SAVE_DATA;\r
+ end if;\r
+ when WAIT_FOR_LOAD =>\r
+ constr_state <= x"2";\r
+ if( (df_empty = '1') and (loadCurrentState = LIDLE) ) then -- waits until the whole packet is transmitted\r
+ constructNextState <= CIDLE;\r
+ else\r
+ constructNextState <= WAIT_FOR_LOAD;\r
+ end if;\r
+ when others =>\r
+ constr_state <= x"f";\r
+ constructNextState <= CIDLE;\r
+ end case;\r
+end process constructMachine;\r
+\r
+--***********************\r
+-- SIZE COUNTERS FOR SAVING SIDE\r
+--***********************\r
+\r
+-- gk 29.03.10 the subevent size saved to its headers cannot contain padding bytes but they are included in pc_sub_size\r
+-- that's why they are removed if pc_padding flag is asserted\r
+sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')\r
+ else (x"c" + pc_sub_size); -- subevent headers + data\r
+\r
+-- BUG HERE BUG HERE BUG HERE BUG HERE\r
+-- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents\r
+queueSizeProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ --if (RESET = '1') or (loadCurrentState = PUT_Q_DEC) then -- gk 07.10.10 -- (loadCurrentState = CLEANUP) then\r
+ if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
+ queue_size <= x"00000028"; -- + 8B for queue headers and 32B for termination\r
+ elsif (saveSubCurrentState = SAVE_SIZE) and (sub_int_ctr = 3) then\r
+ queue_size <= queue_size + pc_sub_size + x"10"; -- + 16B for each subevent headers\r
+ end if;\r
+ end if;\r
+end process queueSizeProc;\r
+\r
+\r
+--***********************\r
+-- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION\r
+--***********************\r
+\r
+loadMachineProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ loadCurrentState <= LIDLE;\r
+ else\r
+ loadCurrentState <= loadNextState;\r
+ end if;\r
+ end if;\r
+end process loadMachineProc;\r
+\r
+loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,\r
+ sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN,\r
+ max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,\r
+ delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)\r
+begin\r
+ case loadCurrentState is\r
+ when LIDLE =>\r
+ load_state <= x"0";\r
+ if ((constructCurrentState = WAIT_FOR_LOAD) and (df_empty = '0')) then\r
+ loadNextState <= WAIT_FOR_FC;\r
+ else\r
+ loadNextState <= LIDLE;\r
+ end if;\r
+ when WAIT_FOR_FC =>\r
+ load_state <= x"1";\r
+ if (TC_H_READY_IN = '1') then\r
+ loadNextState <= PUT_Q_LEN;\r
+ else\r
+ loadNextState <= WAIT_FOR_FC;\r
+ end if;\r
+ when PUT_Q_LEN =>\r
+ load_state <= x"2";\r
+ if (all_int_ctr = 3) then\r
+ loadNextState <= PUT_Q_DEC;\r
+ else\r
+ loadNextState <= PUT_Q_LEN;\r
+ end if;\r
+ when PUT_Q_DEC =>\r
+ load_state <= x"3";\r
+ if (all_int_ctr = 3) then\r
+ loadNextState <= LOAD_SUB;\r
+ else\r
+ loadNextState <= PUT_Q_DEC;\r
+ end if;\r
+ when LOAD_SUB =>\r
+ load_state <= x"4";\r
+ if (bytes_loaded = max_frame_size - 1) then\r
+ loadNextState <= DIVIDE;\r
+ elsif (all_int_ctr = 15) then\r
+ loadNextState <= PREP_DATA;\r
+ else\r
+ loadNextState <= LOAD_SUB;\r
+ end if;\r
+ when PREP_DATA =>\r
+ load_state <= x"5";\r
+ loadNextState <= LOAD_DATA;\r
+ when LOAD_DATA =>\r
+ load_state <= x"6";\r
+-- if (bytes_loaded = max_frame_size - 1) then\r
+-- loadNextState <= DIVIDE;\r
+-- -- gk 07.10.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '1') then\r
+-- if (size_left = x"0000_0023") then\r
+-- loadNextState <= LOAD_TERM;\r
+-- elsif (load_eod_q = '1') then\r
+-- loadNextState <= LOAD_SUB;\r
+-- else\r
+-- loadNextState <= LOAD_DATA;\r
+-- end if;\r
+-- else\r
+-- if (load_eod_q = '1') then\r
+-- loadNextState <= LOAD_TERM;\r
+-- else\r
+-- loadNextState <= LOAD_DATA;\r
+-- end if;\r
+-- end if;\r
+ if (bytes_loaded = max_frame_size - 1) then\r
+ loadNextState <= DIVIDE;\r
+ -- gk 07.10.10\r
+ elsif (load_eod_q = '1') then\r
+ if (MULT_EVT_ENABLE_IN = '1') then\r
+ if (size_left < x"0000_0030") then\r
+ loadNextState <= LOAD_TERM;\r
+ else\r
+ loadNextState <= LOAD_SUB;\r
+ end if;\r
+ else\r
+ loadNextState <= LOAD_TERM;\r
+ end if;\r
+ else\r
+ loadNextState <= LOAD_DATA;\r
+ end if;\r
+ when DIVIDE =>\r
+ load_state <= x"7";\r
+ if (TC_H_READY_IN = '1') then\r
+ if (divide_position = "00") then\r
+ loadNextState <= PREP_DATA;\r
+ elsif (divide_position = "01") then\r
+ loadNextState <= LOAD_SUB;\r
+ else\r
+ loadNextState <= LOAD_TERM;\r
+ end if;\r
+ else\r
+ loadNextState <= DIVIDE;\r
+ end if;\r
+ when LOAD_TERM =>\r
+ load_state <= x"8";\r
+ if (bytes_loaded = max_frame_size - 1) and (all_int_ctr /= 31) then\r
+ loadNextState <= DIVIDE;\r
+ elsif (all_int_ctr = 31) then\r
+ loadNextState <= CLEANUP;\r
+ else\r
+ loadNextState <= LOAD_TERM;\r
+ end if;\r
+ -- gk 28.04.10\r
+ when CLEANUP =>\r
+ load_state <= x"9";\r
+ if (PC_DELAY_IN = x"0000_0000") then\r
+ loadNextState <= LIDLE;\r
+ else\r
+ loadNextState <= DELAY;\r
+ end if;\r
+ -- gk 28.04.10\r
+ when DELAY =>\r
+ load_state <= x"a";\r
+ if (delay_ctr = x"0000_0000") then\r
+ loadNextState <= LIDLE;\r
+ else\r
+ loadNextState <= DELAY;\r
+ end if;\r
+ when others =>\r
+ load_state <= x"f";\r
+ loadNextState <= LIDLE;\r
+ end case;\r
+end process loadMachine;\r
+\r
+-- gk 04.12.10\r
+firstSubInMultiProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LOAD_TERM) then\r
+ first_sub_in_multi <= '1';\r
+ elsif (loadCurrentState = LOAD_DATA) then\r
+ first_sub_in_multi <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+-- gk 04.12.10\r
+fromDivideStateProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ from_divide_state <= '0';\r
+ elsif (loadCurrentState = DIVIDE) then\r
+ from_divide_state <= '1';\r
+ elsif (loadCurrentState = PREP_DATA) then\r
+ from_divide_state <= '0';\r
+ end if;\r
+ end if;\r
+end process fromDivideStateProc;\r
+\r
+\r
+dividePositionProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ divide_position <= "00";\r
+-- elsif (bytes_loaded = max_frame_size - 1) then\r
+-- if (loadCurrentState = LIDLE) then\r
+-- divide_position <= "00";\r
+-- elsif (loadCurrentState = LOAD_DATA) then\r
+-- -- gk 07.10.10\r
+-- if (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then\r
+-- divide_position <= "11";\r
+-- -- gk 07.10.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
+-- divide_position <= "01";\r
+-- -- gk 26.07.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
+-- divide_position <= "11";\r
+-- else\r
+-- divide_position <= "00"; -- still data loaded divide on data\r
+-- end if;\r
+-- elsif (loadCurrentState = LOAD_SUB) then\r
+-- if (all_int_ctr = 15) then\r
+-- divide_position <= "00";\r
+-- else\r
+-- divide_position <= "01";\r
+-- end if;\r
+-- elsif (loadCurrentState = LOAD_TERM) then\r
+-- divide_position <= "11";\r
+-- end if;\r
+-- end if;\r
+ elsif (bytes_loaded = max_frame_size - 1) then\r
+ if (loadCurrentState = LIDLE) then\r
+ divide_position <= "00";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ elsif (loadCurrentState = LOAD_DATA) then\r
+ -- gk 05.12.10\r
+ -- gk 26.07.10\r
+ if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
+ divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
+ if (size_left > x"0000_0028") then\r
+ divide_position <= "01";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ else\r
+ divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ end if;\r
+ else\r
+ divide_position <= "00"; -- still data loaded divide on data\r
+ disable_prep <= '1'; -- gk 05.12.10\r
+ end if;\r
+ elsif (loadCurrentState = LOAD_SUB) then\r
+ if (all_int_ctr = 15) then\r
+ divide_position <= "00";\r
+ disable_prep <= '1'; -- gk 05.12.10\r
+ else\r
+ divide_position <= "01";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ end if;\r
+ elsif (loadCurrentState = LOAD_TERM) then\r
+ divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ end if;\r
+ elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep\r
+ disable_prep <= '0';\r
+ end if;\r
+\r
+ end if;\r
+end process dividePositionProc;\r
+\r
+allIntCtrProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then -- gk 31.05.10\r
+ all_int_ctr <= 0;\r
+ else\r
+ case loadCurrentState is\r
+ \r
+ when LIDLE => all_int_ctr <= 0;\r
+ \r
+ when WAIT_FOR_FC => all_int_ctr <= 0;\r
+ \r
+ when PUT_Q_LEN =>\r
+ if (all_int_ctr = 3) then\r
+ all_int_ctr <= 0;\r
+ else\r
+ all_int_ctr <= all_int_ctr + 1;\r
+ end if;\r
+ \r
+ when PUT_Q_DEC =>\r
+ if (all_int_ctr = 3) then\r
+ all_int_ctr <= 0;\r
+ else\r
+ all_int_ctr <= all_int_ctr + 1;\r
+ end if;\r
+ \r
+ when LOAD_SUB =>\r
+ if (all_int_ctr = 15) then\r
+ all_int_ctr <= 0;\r
+ else\r
+ all_int_ctr <= all_int_ctr + 1;\r
+ end if;\r
+ \r
+ when LOAD_DATA => all_int_ctr <= 0;\r
+ \r
+ when LOAD_TERM =>\r
+ if (all_int_ctr = 31) then\r
+ all_int_ctr <= 0;\r
+ else\r
+ all_int_ctr <= all_int_ctr + 1;\r
+ end if;\r
+ \r
+ when DIVIDE => null;\r
+ \r
+ when CLEANUP => all_int_ctr <= 0;\r
+ \r
+ when PREP_DATA => all_int_ctr <= 0;\r
+ \r
+ when DELAY => all_int_ctr <= 0;\r
+ end case;\r
+ end if;\r
+ end if;\r
+end process allIntCtrProc;\r
+\r
+dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, \r
+ sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q)\r
+begin\r
+ if (RESET = '1') then\r
+ df_rd_en <= '0';\r
+ elsif (loadCurrentState = LOAD_DATA) then\r
+-- if (bytes_loaded = max_frame_size - x"1") then\r
+-- df_rd_en <= '0';\r
+-- -- gk 07.10.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then\r
+-- df_rd_en <= '0';\r
+-- -- gk 07.10.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '1') and (size_left = x"0000_003a") then\r
+-- df_rd_en <= '0';\r
+-- else\r
+-- df_rd_en <= '1';\r
+-- end if;\r
+ if (bytes_loaded = max_frame_size - x"1") then\r
+ df_rd_en <= '0';\r
+ -- gk 26.07.10\r
+ --elsif (load_eod = '1') or (load_eod_q = '1') then\r
+ elsif (load_eod_q = '1') then\r
+ df_rd_en <= '0';\r
+-- elsif (sub_bytes_loaded = sub_size_loaded) then\r
+-- df_rd_en <= '0';\r
+ else\r
+ df_rd_en <= '1';\r
+ end if;\r
+\r
+ elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 15) and (bytes_loaded /= max_frame_size - x"1") then\r
+ df_rd_en <= '1';\r
+ elsif (loadCurrentState = PREP_DATA) then\r
+ df_rd_en <= '1';\r
+ else\r
+ df_rd_en <= '0';\r
+ end if;\r
+end process dfRdEnProc;\r
+\r
+shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)\r
+begin\r
+ if (RESET = '1') then -- gk 31.05.10\r
+ shf_rd_en <= '0';\r
+ elsif (loadCurrentState = LOAD_SUB) then\r
+ shf_rd_en <= '1';\r
+ elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then\r
+ shf_rd_en <= '1';\r
+ elsif (loadCurrentState = PUT_Q_DEC) and (all_int_ctr = 3) then\r
+ shf_rd_en <= '1';\r
+ else\r
+ shf_rd_en <= '0';\r
+ end if;\r
+end process shfRdEnProc;\r
+\r
+\r
+-- fcWrEnProc : process(loadCurrentState, RESET)\r
+-- begin\r
+-- if (RESET = '1') then -- gk 31.05.10\r
+-- fc_wr_en <= '0';\r
+-- elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
+-- fc_wr_en <= '1';\r
+-- elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
+-- fc_wr_en <= '1';\r
+-- else\r
+-- fc_wr_en <= '0';\r
+-- end if;\r
+-- end process fcWrEnProc;\r
+fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)\r
+begin\r
+ if (RESET = '1') then -- gk 31.05.10\r
+ fc_wr_en <= '0';\r
+ elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then\r
+ fc_wr_en <= '1';\r
+ elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
+ fc_wr_en <= '1';\r
+ -- gk 04.12.10\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
+ fc_wr_en <= '1';\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
+ fc_wr_en <= '1';\r
+ else\r
+ fc_wr_en <= '0';\r
+ end if;\r
+end process fcWrEnProc;\r
+\r
+\r
+-- was all_int_ctr\r
+fcDataProc : process(loadCurrentState, queue_size_temp, PC_QUEUE_DEC_IN, shf_q, df_q_reg, load_int_ctr)\r
+begin\r
+ case loadCurrentState is\r
+ when LIDLE => fc_data <= x"af";\r
+ when WAIT_FOR_FC => fc_data <= x"bf";\r
+ -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
+ when PUT_Q_LEN => fc_data <= queue_size_temp(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
+ when PUT_Q_DEC => fc_data <= PC_QUEUE_DEC_IN(load_int_ctr * 8 + 7 downto load_int_ctr * 8);\r
+ when LOAD_SUB => fc_data <= shf_q;\r
+ when PREP_DATA => fc_data <= df_q_reg;\r
+ when LOAD_DATA => fc_data <= df_q_reg;\r
+ when LOAD_TERM => fc_data <= shf_q;\r
+ when DIVIDE => fc_data <= x"cf";\r
+ when CLEANUP => fc_data <= x"df";\r
+ when others => fc_data <= x"00";\r
+ end case;\r
+end process fcDataProc;\r
+\r
+-- delay counters\r
+-- gk 28.04.10\r
+DELAY_CTR_PROC : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if ((RESET = '1') or (loadCurrentState = LIDLE)) then\r
+ delay_ctr <= PC_DELAY_IN;\r
+ elsif ((loadCurrentState = DELAY) and (ticks_ctr(7) = '1')) then\r
+ delay_ctr <= delay_ctr - x"1";\r
+ end if;\r
+ end if;\r
+end process DELAY_CTR_PROC;\r
+\r
+-- gk 28.04.10\r
+TICKS_CTR_PROC : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if ((RESET = '1') or (loadCurrentState = LIDLE) or (ticks_ctr(7) = '1')) then\r
+ ticks_ctr <= x"00";\r
+ elsif (loadCurrentState = DELAY) then\r
+ ticks_ctr <= ticks_ctr + x"1";\r
+ end if;\r
+ end if;\r
+end process TICKS_CTR_PROC;\r
+\r
+\r
+--***********************\r
+-- SIZE COUNTERS FOR LOADING SIDE\r
+--***********************\r
+\r
+queue_size_temp <= queue_size - x"20"; -- size of data without termination\r
+\r
+-- gk 08.04.10\r
+rst_after_sub_comb <= '1' when (loadCurrentState = LIDLE) or\r
+ ((loadCurrentState = LOAD_DATA) and (size_left /= x"00000021")) -- gk 26.07.10 -- and (sub_bytes_loaded = sub_size_loaded) \r
+ else '0';\r
+\r
+-- gk 08.04.10\r
+RST_AFTER_SUB_PROC : process(CLK)\r
+begin\r
+ if(rising_edge(CLK)) then\r
+ if(RESET = '1') then\r
+ rst_after_sub <= '0';\r
+ else\r
+ rst_after_sub <= rst_after_sub_comb;\r
+ end if;\r
+ end if;\r
+end process RST_AFTER_SUB_PROC;\r
+\r
+-- counts all bytes loaded to divide data into frames\r
+bytesLoadedProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = DIVIDE) or (loadCurrentState = CLEANUP) then\r
+ bytes_loaded <= x"0000";\r
+ elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then\r
+ bytes_loaded <= bytes_loaded + x"1";\r
+ -- gk 05.12.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then\r
+-- bytes_loaded <= bytes_loaded + x"1";\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
+ bytes_loaded <= bytes_loaded + x"1";\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
+ bytes_loaded <= bytes_loaded + x"1";\r
+ end if;\r
+ end if;\r
+end process bytesLoadedProc;\r
+\r
+-- size of subevent loaded from memory\r
+subSizeLoadedProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 08.04.10\r
+ sub_size_loaded <= x"00000000";\r
+ elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr < 4) then\r
+ -- was all_int_ctr\r
+ -- gk 08.04.10 my_int_ctr changed to load_int_ctr\r
+ sub_size_loaded(7 + load_int_ctr * 8 downto load_int_ctr * 8) <= shf_q;\r
+ -- gk 29.03.10 here the padding bytes have to be added to the loadedSize in order to load the correct amount of bytes from fifo\r
+ elsif (loadCurrentState = LOAD_SUB) and (all_int_ctr = 5) and (sub_size_loaded(2) = '1') then\r
+ sub_size_loaded <= sub_size_loaded + x"4";\r
+ end if;\r
+ end if;\r
+end process subSizeLoadedProc;\r
+\r
+-- counts only raw data bytes being loaded\r
+subBytesLoadedProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) or (rst_after_sub = '1') then -- gk 26.07.10 --or (sub_bytes_loaded = sub_size_loaded) -- gk 08.04.10\r
+ sub_bytes_loaded <= x"00000011"; -- subevent headers doesnt count\r
+ elsif (loadCurrentState = LOAD_DATA) then\r
+ sub_bytes_loaded <= sub_bytes_loaded + x"1";\r
+ end if;\r
+ end if;\r
+end process subBytesLoadedProc;\r
+\r
+-- counts the size of the large udp packet\r
+actualPacketProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
+ actual_packet_size <= x"0008";\r
+ elsif (fc_wr_en = '1') then\r
+ actual_packet_size <= actual_packet_size + x"1";\r
+ end if;\r
+ end if;\r
+end process actualPacketProc;\r
+\r
+actualQueueSizeProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
+ actual_queue_size <= (others => '0');\r
+ elsif (loadCurrentState = LIDLE) then\r
+ actual_queue_size <= queue_size;\r
+ end if;\r
+ end if;\r
+end process actualQueueSizeProc;\r
+\r
+-- amount of bytes left to send in current packet\r
+sizeLeftProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = CLEANUP) then\r
+ size_left <= (others => '0');\r
+ elsif (loadCurrentState = LIDLE) then\r
+ size_left <= queue_size;\r
+ elsif (fc_wr_en = '1') then\r
+ size_left <= size_left - 1;\r
+ end if;\r
+ end if;\r
+end process sizeLeftProc;\r
+\r
+-- HOT FIX: don't rely on CTS information, count the packets on your own.\r
+-- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.\r
+THE_FC_IDENT_COUNTER_PROC: process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ fc_ident <= (others => '0');\r
+ elsif (PC_END_OF_DATA_IN = '1') then\r
+ fc_ident <= fc_ident + 1;\r
+ end if;\r
+ end if;\r
+end process THE_FC_IDENT_COUNTER_PROC;\r
+\r
+fc_flags_offset(15 downto 14) <= "00";\r
+\r
+moreFragmentsProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
+ fc_flags_offset(13) <= '0';\r
+ elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then\r
+ if ((actual_queue_size - actual_packet_size) < max_frame_size) then\r
+ fc_flags_offset(13) <= '0'; -- no more fragments\r
+ else\r
+ fc_flags_offset(13) <= '1'; -- more fragments\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process moreFragmentsProc;\r
+\r
+eodProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ fc_eod <= '0';\r
+ elsif (loadCurrentState = LOAD_DATA) and (bytes_loaded = max_frame_size - 2) then\r
+ fc_eod <= '1';\r
+ elsif (loadCurrentState = LOAD_SUB) and (bytes_loaded = max_frame_size - 2) then\r
+ fc_eod <= '1';\r
+ elsif (loadCurrentState = LOAD_TERM) and ((bytes_loaded = max_frame_size - 2) or (all_int_ctr = 30)) then\r
+ fc_eod <= '1';\r
+ else\r
+ fc_eod <= '0';\r
+ end if;\r
+ end if;\r
+end process eodProc;\r
+\r
+sodProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ fc_sod <= '0';\r
+ elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then\r
+ fc_sod <= '1';\r
+ elsif (loadCurrentState = DIVIDE) and (TC_READY_IN = '1') then\r
+ fc_sod <= '1';\r
+ else\r
+ fc_sod <= '0';\r
+ end if;\r
+ end if;\r
+end process sodProc;\r
+\r
+offsetProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LIDLE) or (loadCurrentState = CLEANUP) then\r
+ fc_flags_offset(12 downto 0) <= (others => '0');\r
+ elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) then\r
+ fc_flags_offset(12 downto 0) <= actual_packet_size(15 downto 3);\r
+ end if;\r
+ end if;\r
+end process offsetProc;\r
+\r
+fcIPSizeProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET= '1') then\r
+ fc_ip_size <= (others => '0');\r
+ elsif ((loadCurrentState = DIVIDE) and (TC_READY_IN = '1')) or ((loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1')) then\r
+ if (size_left >= max_frame_size) then\r
+ fc_ip_size <= max_frame_size;\r
+ else\r
+ fc_ip_size <= size_left(15 downto 0);\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process fcIPSizeProc;\r
+\r
+fcUDPSizeProc : process(CLK)\r
+ begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ fc_udp_size <= (others => '0');\r
+ elsif (loadCurrentState = WAIT_FOR_FC) and (TC_READY_IN = '1') then\r
+ fc_udp_size <= queue_size(15 downto 0);\r
+ end if;\r
+ end if;\r
+end process fcUDPSizeProc;\r
+\r
+\r
+--***********************\r
+-- SUBEVENT HEADERS WRITE AND READ\r
+--***********************\r
+\r
+SUBEVENT_HEADERS_FIFO : fifo_16kx8\r
+port map(\r
+ Data => shf_data,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => shf_wr_en,\r
+ RdEn => shf_rd_en,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q => shf_q,\r
+ Empty => shf_empty,\r
+ Full => shf_full\r
+);\r
+\r
+-- write enable for SHF \r
+shf_wr_en <= '1' when ((saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA))\r
+ else '0';\r
+\r
+-- data multiplexing for SHF (convert 32bit LWs to 8bit)\r
+-- CHANGED. \r
+-- The SubEventHeader (4x 32bit is stored in [MSB:LSB] now, same byte order as data from PC.\r
+shfDataProc : process(saveSubCurrentState, sub_size_to_save, PC_DECODING_IN, PC_EVENT_ID_IN, \r
+ pc_trig_nr, my_int_ctr, fc_data)\r
+begin\r
+ case saveSubCurrentState is\r
+ when SIDLE => shf_data <= x"ac";\r
+ when SAVE_SIZE => shf_data <= sub_size_to_save(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
+ when SAVE_DECODING => shf_data <= PC_DECODING_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
+ when SAVE_ID => shf_data <= PC_EVENT_ID_IN(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
+ when SAVE_TRIG_NR => shf_data <= pc_trig_nr(my_int_ctr * 8 + 7 downto my_int_ctr * 8);\r
+ when SAVE_TERM => shf_data <= fc_data;\r
+ when others => shf_data <= x"00";\r
+ end case;\r
+end process shfDataProc;\r
+\r
+saveSubMachineProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ saveSubCurrentState <= SIDLE;\r
+ else\r
+ saveSubCurrentState <= saveSubNextState;\r
+ end if;\r
+ end if;\r
+end process saveSubMachineProc;\r
+\r
+saveSubMachine : process(saveSubCurrentState, PC_START_OF_SUB_IN, sub_int_ctr, loadCurrentState, TC_H_READY_IN)\r
+begin\r
+ case saveSubCurrentState is\r
+ when SIDLE =>\r
+ save_state <= x"0";\r
+ if (PC_START_OF_SUB_IN = '1') then\r
+ saveSubNextState <= SAVE_SIZE;\r
+ -- this branch is dangerous!\r
+ elsif (loadCurrentState = WAIT_FOR_FC) and (TC_H_READY_IN = '1') then -- means that loadCurrentState is put_q_len\r
+ saveSubNextState <= SAVE_TERM;\r
+ else\r
+ saveSubNextState <= SIDLE;\r
+ end if;\r
+ when SAVE_SIZE =>\r
+ save_state <= x"1";\r
+ if (sub_int_ctr = 3) then\r
+ saveSubNextState <= SAVE_DECODING;\r
+ else\r
+ saveSubNextState <= SAVE_SIZE;\r
+ end if;\r
+ when SAVE_DECODING =>\r
+ save_state <= x"2";\r
+ if (sub_int_ctr = 3) then\r
+ saveSubNextState <= SAVE_ID;\r
+ else\r
+ saveSubNextState <= SAVE_DECODING;\r
+ end if;\r
+ when SAVE_ID =>\r
+ save_state <= x"3";\r
+ if (sub_int_ctr = 3) then\r
+ saveSubNextState <= SAVE_TRIG_NR;\r
+ else\r
+ saveSubNextState <= SAVE_ID;\r
+ end if;\r
+ when SAVE_TRIG_NR =>\r
+ save_state <= x"4";\r
+ if (sub_int_ctr = 3) then\r
+ saveSubNextState <= SIDLE;\r
+ else\r
+ saveSubNextState <= SAVE_TRIG_NR;\r
+ end if;\r
+ when SAVE_TERM =>\r
+ save_state <= x"5";\r
+ if (sub_int_ctr = 31) then\r
+ saveSubNextState <= SIDLE;\r
+ else\r
+ saveSubNextState <= SAVE_TERM;\r
+ end if;\r
+ when others =>\r
+ save_state <= x"f";\r
+ saveSubNextState <= SIDLE;\r
+ end case;\r
+end process;\r
+\r
+-- This counter is used for breaking down 32bit information words into 8bit bytes for \r
+-- storing them in the SHF.\r
+-- It is also used for the termination 32byte sequence.\r
+subIntProc: process( CLK )\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (saveSubCurrentState = SIDLE) then\r
+ sub_int_ctr <= 0;\r
+ elsif (sub_int_ctr = 3) and (saveSubCurrentState /= SAVE_TERM) then\r
+ sub_int_ctr <= 0;\r
+ elsif (sub_int_ctr = 31) and (saveSubCurrentState = SAVE_TERM) then\r
+ sub_int_ctr <= 0;\r
+ elsif (saveSubCurrentState /= SIDLE) and (loadCurrentState /= PREP_DATA) then\r
+ sub_int_ctr <= sub_int_ctr + 1;\r
+ end if;\r
+ end if;\r
+end process subIntProc;\r
+\r
+debug(3 downto 0) <= constr_state;\r
+debug(7 downto 4) <= save_state;\r
+debug(11 downto 8) <= load_state;\r
+debug(27 downto 12) <= queue_size(15 downto 0);\r
+debug(28) <= df_full;\r
+debug(29) <= df_empty;\r
+debug(30) <= shf_full;\r
+debug(31) <= shf_empty;\r
+\r
+debug(47 downto 32) <= size_left(15 downto 0);\r
+debug(52 downto 48) <= all_ctr;\r
+debug(53) <= pc_ready;\r
+\r
+-- outputs\r
+PC_READY_OUT <= pc_ready;\r
+TC_WR_EN_OUT <= fc_wr_en;\r
+TC_DATA_OUT <= fc_data;\r
+TC_IP_SIZE_OUT <= fc_ip_size;\r
+TC_UDP_SIZE_OUT <= fc_udp_size;\r
+-- FC_IDENT_OUT(15 downto 8) <= fc_ident(7 downto 0);\r
+-- FC_IDENT_OUT(7 downto 0) <= fc_ident(15 downto 8);\r
+TC_FLAGS_OFFSET_OUT <= fc_flags_offset;\r
+TC_SOD_OUT <= fc_sod;\r
+TC_EOD_OUT <= fc_eod;\r
+\r
+DEBUG_OUT <= debug;\r
+\r
end trb_net16_gbe_packet_constr;
\ No newline at end of file
if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client
CODE_OUT(1) <= '1';
-- No. 4 = SCTRL
- elsif (UDP_PROTOCOL_IN = x"6590") then -- SCTRL module
- CODE_OUT(2) <= '1';
+ elsif (UDP_PROTOCOL_IN = x"61a8") then -- SCTRL module
+ CODE_OUT(3) <= '1';
else
-- branch for pure IPv4
CODE_OUT <= (others => '0');
end if;
-- No. 3 = ICMP
--- elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
--- CODE_OUT(2) <= '1';
+ elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
+ CODE_OUT(2) <= '1';
else
CODE_OUT <= (others => '0');
end if;
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
MC_BUSY_IN : in std_logic;
-- counters from response constructors
GSC_BUSY_IN : in std_logic;
MAKE_RESET_OUT : out std_logic;
-
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-- input for statistics from outside
STAT_DATA_IN : in std_logic_vector(31 downto 0);
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_protocol_selector : architecture is "GBE_MAIN_group";
-attribute syn_encoding : string;
-
signal rd_en : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal resp_ready : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_wr : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal tc_data : std_logic_vector(c_MAX_PROTOCOLS * 9 - 1 downto 0);
signal tc_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
signal tc_type : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
-- plus 1 is for the outside
-signal stat_data : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
-signal stat_addr : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
-signal stat_rdy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal stat_ack : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal tc_ip_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_udp_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_size_left : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal tc_flags_size : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
+signal stat_data : std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
+signal stat_addr : std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
+signal stat_rdy : std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+signal stat_ack : std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+signal tc_ip_size : std_logic_vector((c_MAX_PROTOCOLS + 1) * 16 - 1 downto 0);
+signal tc_udp_size : std_logic_vector((c_MAX_PROTOCOLS + 1) * 16 - 1 downto 0);
+signal tc_flags_size : std_logic_vector((c_MAX_PROTOCOLS + 1) * 16 - 1 downto 0);
-signal tc_data_not_valid : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
type select_states is (IDLE, LOOP_OVER, SELECT_ONE, PROCESS_REQUEST, CLEANUP);
signal select_current_state, select_next_state : select_states;
-attribute syn_encoding of select_current_state : signal is "onehot";
signal state : std_logic_vector(3 downto 0);
signal index : integer range 0 to c_MAX_PROTOCOLS - 1;
signal mult : std_logic;
-signal tc_ident : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
-signal zeros : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_keep of state, mult : signal is true;
begin
-zeros <= (others => '0');
-
-- protocol Nr. 1 ARP
ARP : trb_net16_gbe_response_constructor_ARP
generic map( STAT_ADDRESS_BASE => 6
)
port map (
- CLK => CLK,
- RESET => RESET,
+ CLK => CLK,
+ RESET => RESET,
-- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0),
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(0),
PS_RESPONSE_READY_OUT => resp_ready(0),
- PS_BUSY_OUT => busy(0),
- PS_SELECTED_IN => selected(0),
+ PS_BUSY_OUT => busy(0),
+ PS_SELECTED_IN => selected(0),
PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9),
- TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16),
- TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8),
- TC_IDENT_OUT => tc_ident(1 * 16 - 1 downto 0 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48),
- TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32),
- TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48),
- TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16),
-
- STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
- STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(0),
- STAT_DATA_ACK_IN => stat_ack(0),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
- DEBUG_OUT => PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
--- END OF INTERFACE
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(1 * 9 - 1 downto 0 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(1 * 16 - 1 downto 0 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(1 * 16 - 1 downto 0 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(1 * 8 - 1 downto 0 * 8),
+
+ TC_DEST_MAC_OUT => tc_mac(1 * 48 - 1 downto 0 * 48),
+ TC_DEST_IP_OUT => tc_ip(1 * 32 - 1 downto 0 * 32),
+ TC_DEST_UDP_OUT => tc_udp(1 * 16 - 1 downto 0 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(1 * 48 - 1 downto 0 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(1 * 32 - 1 downto 0 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(1 * 16 - 1 downto 0 * 16),
+
+ TC_IP_SIZE_OUT => tc_ip_size(1 * 16 - 1 downto 0 * 16),
+ TC_UDP_SIZE_OUT => tc_udp_size(1 * 16 - 1 downto 0 * 16),
+ TC_FLAGS_OFFSET_OUT => tc_flags_size(1 * 16 - 1 downto 0 * 16),
+
+ TC_BUSY_IN => TC_BUSY_IN,
+
+ STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
+ STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(0),
+ STAT_DATA_ACK_IN => stat_ack(0),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
+ DEBUG_OUT => PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+-- END OF INTERFACE
);
-- protocol No. 2 DHCP
generic map( STAT_ADDRESS_BASE => 0
)
port map (
- CLK => CLK,
- RESET => RESET,
+ CLK => CLK,
+ RESET => RESET,
-- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1),
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(1),
PS_RESPONSE_READY_OUT => resp_ready(1),
- PS_BUSY_OUT => busy(1),
- PS_SELECTED_IN => selected(1),
+ PS_BUSY_OUT => busy(1),
+ PS_SELECTED_IN => selected(1),
PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9),
- TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16),
- TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8),
- TC_IDENT_OUT => tc_ident(2 * 16 - 1 downto 1 * 16),
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(2 * 9 - 1 downto 1 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(2 * 16 - 1 downto 1 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(2 * 16 - 1 downto 1 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(2 * 8 - 1 downto 1 * 8),
- TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48),
- TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32),
- TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48),
- TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16),
-
- STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
- STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(1),
- STAT_DATA_ACK_IN => stat_ack(1),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
+ TC_DEST_MAC_OUT => tc_mac(2 * 48 - 1 downto 1 * 48),
+ TC_DEST_IP_OUT => tc_ip(2 * 32 - 1 downto 1 * 32),
+ TC_DEST_UDP_OUT => tc_udp(2 * 16 - 1 downto 1 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(2 * 48 - 1 downto 1 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(2 * 32 - 1 downto 1 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(2 * 16 - 1 downto 1 * 16),
+
+ TC_IP_SIZE_OUT => tc_ip_size(2 * 16 - 1 downto 1 * 16),
+ TC_UDP_SIZE_OUT => tc_udp_size(2 * 16 - 1 downto 1 * 16),
+ TC_FLAGS_OFFSET_OUT => tc_flags_size(2 * 16 - 1 downto 1 * 16),
+
+ TC_BUSY_IN => TC_BUSY_IN,
+
+ STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
+ STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(1),
+ STAT_DATA_ACK_IN => stat_ack(1),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
-- END OF INTERFACE
- DHCP_START_IN => DHCP_START_IN,
- DHCP_DONE_OUT => DHCP_DONE_OUT,
+ DHCP_START_IN => DHCP_START_IN,
+ DHCP_DONE_OUT => DHCP_DONE_OUT,
- DEBUG_OUT => PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
+ DEBUG_OUT => PROTOS_DEBUG_OUT(2 * 32 - 1 downto 1 * 32)
);
-- protocol No. 3 Ping
---Ping : trb_net16_gbe_response_constructor_Ping
---generic map( STAT_ADDRESS_BASE => 3
---)
---port map (
--- CLK => CLK,
--- RESET => RESET,
---
------- INTERFACE
--- PS_DATA_IN => PS_DATA_IN,
--- PS_WR_EN_IN => PS_WR_EN_IN,
--- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
--- PS_RESPONSE_READY_OUT => resp_ready(2),
--- PS_BUSY_OUT => busy(2),
--- PS_SELECTED_IN => selected(2),
---
--- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
--- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
--- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
--- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
--- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
--- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
---
--- TC_RD_EN_IN => TC_RD_EN_IN,
--- TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
--- TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
--- TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
--- TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
--- TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
---
--- TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
--- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
--- TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
--- TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
--- TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
--- TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
---
--- STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
--- STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
--- STAT_DATA_RDY_OUT => stat_rdy(2),
--- STAT_DATA_ACK_IN => stat_ack(2),
--- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
--- SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
--- DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
----- END OF INTERFACE
---);
+Ping : trb_net16_gbe_response_constructor_Ping
+generic map( STAT_ADDRESS_BASE => 3
+)
+port map (
+ CLK => CLK,
+ RESET => RESET,
+
+-- INTERFACE
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
+ PS_RESPONSE_READY_OUT => resp_ready(2),
+ PS_BUSY_OUT => busy(2),
+ PS_SELECTED_IN => selected(2),
+
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
+
+ TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
+ TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
+ TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
+
+ TC_IP_SIZE_OUT => tc_ip_size(3 * 16 - 1 downto 2 * 16),
+ TC_UDP_SIZE_OUT => tc_udp_size(3 * 16 - 1 downto 2 * 16),
+ TC_FLAGS_OFFSET_OUT => tc_flags_size(3 * 16 - 1 downto 2 * 16),
+
+ TC_BUSY_IN => TC_BUSY_IN,
+
+ STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
+ STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(2),
+ STAT_DATA_ACK_IN => stat_ack(2),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+ DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
+-- END OF INTERFACE
+);
SCTRL : trb_net16_gbe_response_constructor_SCTRL
generic map( STAT_ADDRESS_BASE => 8
)
port map (
- CLK => CLK,
- RESET => RESET,
+ CLK => CLK,
+ RESET => RESET,
-- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(2),
- PS_RESPONSE_READY_OUT => resp_ready(2),
- PS_BUSY_OUT => busy(2),
- PS_SELECTED_IN => selected(2),
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
+ PS_RESPONSE_READY_OUT => resp_ready(3),
+ PS_BUSY_OUT => busy(3),
+ PS_SELECTED_IN => selected(3),
PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(3 * 9 - 1 downto 2 * 9),
- TC_FRAME_SIZE_OUT => tc_size(3 * 16 - 1 downto 2 * 16),
- TC_FRAME_TYPE_OUT => tc_type(3 * 16 - 1 downto 2 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(3 * 8 - 1 downto 2 * 8),
- TC_IDENT_OUT => tc_ident(3 * 16 - 1 downto 2 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(3 * 48 - 1 downto 2 * 48),
- TC_DEST_IP_OUT => tc_ip(3 * 32 - 1 downto 2 * 32),
- TC_DEST_UDP_OUT => tc_udp(3 * 16 - 1 downto 2 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(3 * 48 - 1 downto 2 * 48),
- TC_SRC_IP_OUT => tc_src_ip(3 * 32 - 1 downto 2 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(3 * 16 - 1 downto 2 * 16),
-
- STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
- STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(2),
- STAT_DATA_ACK_IN => stat_ack(2),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
+
+ TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
+ TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
+ TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
+
+ TC_IP_SIZE_OUT => tc_ip_size(4 * 16 - 1 downto 3 * 16),
+ TC_UDP_SIZE_OUT => tc_udp_size(4 * 16 - 1 downto 3 * 16),
+ TC_FLAGS_OFFSET_OUT => tc_flags_size(4 * 16 - 1 downto 3 * 16),
+
+ TC_BUSY_IN => TC_BUSY_IN,
+
+ STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
+ STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(3),
+ STAT_DATA_ACK_IN => stat_ack(3),
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
-- END OF INTERFACE
- GSC_CLK_IN => GSC_CLK_IN,
- GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- GSC_INIT_READ_IN => GSC_INIT_READ_IN,
- GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
- GSC_BUSY_IN => GSC_BUSY_IN,
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
- MAKE_RESET_OUT => MAKE_RESET_OUT,
+ MAKE_RESET_OUT => MAKE_RESET_OUT,
- DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
+ DEBUG_OUT => PROTOS_DEBUG_OUT(4 * 32 - 1 downto 3 * 32)
);
-TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
+--stat_gen : if g_SIMULATE = 0 generate
+Stat : trb_net16_gbe_response_constructor_Stat
+generic map( STAT_ADDRESS_BASE => 10
+)
port map (
- CLK => CLK,
- RESET => RESET,
+ CLK => CLK,
+ RESET => RESET,
-- INTERFACE
- PS_DATA_IN => PS_DATA_IN,
- PS_WR_EN_IN => PS_WR_EN_IN,
- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(3),
- PS_RESPONSE_READY_OUT => resp_ready(3),
- PS_BUSY_OUT => busy(3),
- PS_SELECTED_IN => selected(3),
-
- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
-
- TC_RD_EN_IN => TC_RD_EN_IN,
- TC_DATA_OUT => tc_data(4 * 9 - 1 downto 3 * 9),
- TC_FRAME_SIZE_OUT => tc_size(4 * 16 - 1 downto 3 * 16),
- TC_FRAME_TYPE_OUT => tc_type(4 * 16 - 1 downto 3 * 16),
- TC_IP_PROTOCOL_OUT => tc_ip_proto(4 * 8 - 1 downto 3 * 8),
- TC_IDENT_OUT => tc_ident(4 * 16 - 1 downto 3 * 16),
-
- TC_DEST_MAC_OUT => tc_mac(4 * 48 - 1 downto 3 * 48),
- TC_DEST_IP_OUT => tc_ip(4 * 32 - 1 downto 3 * 32),
- TC_DEST_UDP_OUT => tc_udp(4 * 16 - 1 downto 3 * 16),
- TC_SRC_MAC_OUT => tc_src_mac(4 * 48 - 1 downto 3 * 48),
- TC_SRC_IP_OUT => tc_src_ip(4 * 32 - 1 downto 3 * 32),
- TC_SRC_UDP_OUT => tc_src_udp(4 * 16 - 1 downto 3 * 16),
-
- STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
- STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
- STAT_DATA_RDY_OUT => stat_rdy(3),
- STAT_DATA_ACK_IN => stat_ack(3),
- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
- SENT_FRAMES_OUT => SENT_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data payload interface
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- ip configurator
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
-
- CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN,
-
--- debug
- DEBUG_OUT => open
+ PS_DATA_IN => PS_DATA_IN,
+ PS_WR_EN_IN => PS_WR_EN_IN,
+ PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
+ PS_RESPONSE_READY_OUT => resp_ready(4),
+ PS_BUSY_OUT => busy(4),
+ PS_SELECTED_IN => selected(4),
+
+ PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
+ PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
+ PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
+ PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
+ PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
+ PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
+
+ TC_RD_EN_IN => TC_RD_EN_IN,
+ TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
+ TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
+ TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
+ TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
+
+ TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
+ TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
+ TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
+ TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
+ TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
+ TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
+
+ TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16),
+ TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16),
+ TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16),
+
+ TC_BUSY_IN => TC_BUSY_IN,
+
+ STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
+ STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(4),
+ STAT_DATA_ACK_IN => stat_ack(4),
+
+ RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
+ SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
+ DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32),
+
+ STAT_DATA_IN => stat_data,
+ STAT_ADDR_IN => stat_addr,
+ STAT_DATA_RDY_IN => stat_rdy,
+ STAT_DATA_ACK_OUT => stat_ack
);
-
---stat_gen : if g_SIMULATE = 0 generate
---Stat : trb_net16_gbe_response_constructor_Stat
---generic map( STAT_ADDRESS_BASE => 10
---)
---port map (
--- CLK => CLK,
--- RESET => RESET,
---
----- INTERFACE
--- PS_DATA_IN => PS_DATA_IN,
--- PS_WR_EN_IN => PS_WR_EN_IN,
--- PS_ACTIVATE_IN => PS_PROTO_SELECT_IN(4),
--- PS_RESPONSE_READY_OUT => resp_ready(4),
--- PS_BUSY_OUT => busy(4),
--- PS_SELECTED_IN => selected(4),
---
--- PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN,
--- PS_DEST_MAC_ADDRESS_IN => PS_DEST_MAC_ADDRESS_IN,
--- PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN,
--- PS_DEST_IP_ADDRESS_IN => PS_DEST_IP_ADDRESS_IN,
--- PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN,
--- PS_DEST_UDP_PORT_IN => PS_DEST_UDP_PORT_IN,
---
--- TC_WR_EN_OUT => TC_WR_EN_OUT,
--- TC_DATA_OUT => tc_data(5 * 9 - 1 downto 4 * 9),
--- TC_FRAME_SIZE_OUT => tc_size(5 * 16 - 1 downto 4 * 16),
--- TC_FRAME_TYPE_OUT => tc_type(5 * 16 - 1 downto 4 * 16),
--- TC_IP_PROTOCOL_OUT => tc_ip_proto(5 * 8 - 1 downto 4 * 8),
---
--- TC_DEST_MAC_OUT => tc_mac(5 * 48 - 1 downto 4 * 48),
--- TC_DEST_IP_OUT => tc_ip(5 * 32 - 1 downto 4 * 32),
--- TC_DEST_UDP_OUT => tc_udp(5 * 16 - 1 downto 4 * 16),
--- TC_SRC_MAC_OUT => tc_src_mac(5 * 48 - 1 downto 4 * 48),
--- TC_SRC_IP_OUT => tc_src_ip(5 * 32 - 1 downto 4 * 32),
--- TC_SRC_UDP_OUT => tc_src_udp(5 * 16 - 1 downto 4 * 16),
---
--- TC_IP_SIZE_OUT => tc_ip_size(5 * 16 - 1 downto 4 * 16),
--- TC_UDP_SIZE_OUT => tc_udp_size(5 * 16 - 1 downto 4 * 16),
--- TC_FLAGS_OFFSET_OUT => tc_flags_size(5 * 16 - 1 downto 4 * 16),
---
--- TC_BUSY_IN => TC_BUSY_IN,
---
--- STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
--- STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
--- STAT_DATA_RDY_OUT => stat_rdy(4),
--- STAT_DATA_ACK_IN => stat_ack(4),
---
--- RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
--- SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
--- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32),
---
--- STAT_DATA_IN => stat_data,
--- STAT_ADDR_IN => stat_addr,
--- STAT_DATA_RDY_IN => stat_rdy,
--- STAT_DATA_ACK_OUT => stat_ack
---);
--end generate;
--***************
-- DO NOT TOUCH, response selection logic
---stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN;
---stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN;
---stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN;
---STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS);
+stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN;
+stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN;
+stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN;
+STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS);
+
+mult <= or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3));
---mult <= or_all(resp_ready(2 downto 0)); --or_all(resp_ready(2 downto 0)) and or_all(resp_ready(4 downto 3));
PS_BUSY_OUT <= busy;
end if;
end process SELECT_MACHINE_PROC;
-SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros)
+SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index)
begin
case (select_current_state) is
when IDLE =>
+ state <= x"1";
if (MC_BUSY_IN = '0') then
select_next_state <= LOOP_OVER;
else
end if;
when LOOP_OVER =>
- if (resp_ready /= zeros) then
+ state <= x"2";
+ if (or_all(resp_ready) = '1') then
if (resp_ready(index) = '1') then
select_next_state <= SELECT_ONE;
elsif (index = c_MAX_PROTOCOLS) then
select_next_state <= CLEANUP;
- else
- select_next_state <= LOOP_OVER;
end if;
else
select_next_state <= CLEANUP;
- end if;
-
+ end if;
+
when SELECT_ONE =>
+ state <= x"3";
if (MC_BUSY_IN = '1') then
select_next_state <= PROCESS_REQUEST;
else
end if;
when PROCESS_REQUEST =>
+ state <= x"4";
if (MC_BUSY_IN = '0') then
select_next_state <= CLEANUP;
else
end if;
when CLEANUP =>
+ state <= x"5";
select_next_state <= IDLE;
end case;
if rising_edge(CLK) then
if (RESET = '1') or (select_current_state = IDLE) then
index <= 0;
- elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0') then -- and (or_all(resp_ready) = '1' or mult = '1')) then
+ elsif (select_current_state = LOOP_OVER and resp_ready(index) = '0' and (or_all(resp_ready) = '1' or mult = '1')) then
index <= index + 1;
end if;
end if;
TC_SRC_IP_OUT <= (others => '0');
TC_SRC_UDP_OUT <= (others => '0');
TC_IP_PROTOCOL_OUT <= (others => '0');
- TC_IDENT_OUT <= (others => '0');
+ TC_IP_SIZE_OUT <= (others => '0');
+ TC_UDP_SIZE_OUT <= (others => '0');
+ TC_FLAGS_OFFSET_OUT <= (others => '0');
PS_RESPONSE_READY_OUT <= '0';
selected <= (others => '0');
elsif (select_current_state = SELECT_ONE or select_current_state = PROCESS_REQUEST) then
TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32);
TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16);
TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8);
- TC_IDENT_OUT <= tc_ident((index + 1) * 16 - 1 downto index * 16);
+ TC_IP_SIZE_OUT <= tc_ip_size((index + 1) * 16 - 1 downto index * 16);
+ TC_UDP_SIZE_OUT <= tc_udp_size((index + 1) * 16 - 1 downto index * 16);
+ TC_FLAGS_OFFSET_OUT <= tc_flags_size((index + 1) * 16 - 1 downto index * 16);
if (select_current_state = SELECT_ONE) then
PS_RESPONSE_READY_OUT <= '1';
- selected(index) <= '0';
else
PS_RESPONSE_READY_OUT <= '0';
- selected(index) <= '1';
end if;
+ selected(index) <= '1';
else
TC_DATA_OUT <= (others => '0');
TC_FRAME_SIZE_OUT <= (others => '0');
TC_SRC_IP_OUT <= (others => '0');
TC_SRC_UDP_OUT <= (others => '0');
TC_IP_PROTOCOL_OUT <= (others => '0');
- TC_IDENT_OUT <= (others => '0');
+ TC_IP_SIZE_OUT <= (others => '0');
+ TC_UDP_SIZE_OUT <= (others => '0');
+ TC_FLAGS_OFFSET_OUT <= (others => '0');
PS_RESPONSE_READY_OUT <= '0';
selected <= (others => '0');
end if;
end if;
end process SELECTOR_PROC;
+--SELECTOR_PROC : process(CLK)
+-- variable found : boolean := false;
+-- variable index : integer range 0 to c_MAX_PROTOCOLS - 1 := 0;
+--begin
+-- if rising_edge(CLK) then
+--
+-- selected <= (others => '0');
+--
+-- if (RESET = '1') then
+-- TC_DATA_OUT <= (others => '0');
+-- TC_FRAME_SIZE_OUT <= (others => '0');
+-- TC_FRAME_TYPE_OUT <= (others => '0');
+-- TC_DEST_MAC_OUT <= (others => '0');
+-- TC_DEST_IP_OUT <= (others => '0');
+-- TC_DEST_UDP_OUT <= (others => '0');
+-- TC_SRC_MAC_OUT <= (others => '0');
+-- TC_SRC_IP_OUT <= (others => '0');
+-- TC_SRC_UDP_OUT <= (others => '0');
+-- TC_IP_PROTOCOL_OUT <= (others => '0');
+-- TC_IP_SIZE_OUT <= (others => '0');
+-- TC_UDP_SIZE_OUT <= (others => '0');
+-- TC_FLAGS_OFFSET_OUT <= (others => '0');
+-- PS_RESPONSE_READY_OUT <= '0';
+-- selected <= (others => '0');
+-- found := false;
+-- index := 0;
+-- else
+-- if (or_all(resp_ready) = '1' and MC_BUSY_IN = '0') then
+-- for i in 0 to c_MAX_PROTOCOLS - 1 loop
+-- if (resp_ready(i) = '1' and found = false) then
+-- TC_DATA_OUT <= tc_data((i + 1) * 9 - 1 downto i * 9);
+-- TC_FRAME_SIZE_OUT <= tc_size((i + 1) * 16 - 1 downto i * 16);
+-- TC_FRAME_TYPE_OUT <= tc_type((i + 1) * 16 - 1 downto i * 16);
+-- TC_DEST_MAC_OUT <= tc_mac((i + 1) * 48 - 1 downto i * 48);
+-- TC_DEST_IP_OUT <= tc_ip((i + 1) * 32 - 1 downto i * 32);
+-- TC_DEST_UDP_OUT <= tc_udp((i + 1) * 16 - 1 downto i * 16);
+-- TC_SRC_MAC_OUT <= tc_src_mac((i + 1) * 48 - 1 downto i * 48);
+-- TC_SRC_IP_OUT <= tc_src_ip((i + 1) * 32 - 1 downto i * 32);
+-- TC_SRC_UDP_OUT <= tc_src_udp((i + 1) * 16 - 1 downto i * 16);
+-- TC_IP_PROTOCOL_OUT <= tc_ip_proto((i + 1) * 8 - 1 downto i * 8);
+-- TC_IP_SIZE_OUT <= tc_ip_size((i + 1) * 16 - 1 downto i * 16);
+-- TC_UDP_SIZE_OUT <= tc_udp_size((i + 1) * 16 - 1 downto i * 16);
+-- TC_FLAGS_OFFSET_OUT <= tc_flags_size((i + 1) * 16 - 1 downto i * 16);
+-- PS_RESPONSE_READY_OUT <= '1';
+-- selected(i) <= '1';
+-- index := i;
+-- found := true;
+---- elsif (i = c_MAX_PROTOCOLS - 1) and (resp_ready(i) = '0') and (found = false) then
+---- found := false;
+---- PS_RESPONSE_READY_OUT <= '0';
+-- end if;
+-- end loop;
+-- elsif (or_all(resp_ready) = '1' and MC_BUSY_IN = '1') then
+-- TC_DATA_OUT <= tc_data((index + 1) * 9 - 1 downto index * 9);
+-- TC_FRAME_SIZE_OUT <= tc_size((index + 1) * 16 - 1 downto index * 16);
+-- TC_FRAME_TYPE_OUT <= tc_type((index + 1) * 16 - 1 downto index * 16);
+-- TC_DEST_MAC_OUT <= tc_mac((index + 1) * 48 - 1 downto index * 48);
+-- TC_DEST_IP_OUT <= tc_ip((index + 1) * 32 - 1 downto index * 32);
+-- TC_DEST_UDP_OUT <= tc_udp((index + 1) * 16 - 1 downto index * 16);
+-- TC_SRC_MAC_OUT <= tc_src_mac((index + 1) * 48 - 1 downto index * 48);
+-- TC_SRC_IP_OUT <= tc_src_ip((index + 1) * 32 - 1 downto index * 32);
+-- TC_SRC_UDP_OUT <= tc_src_udp((index + 1) * 16 - 1 downto index * 16);
+-- TC_IP_PROTOCOL_OUT <= tc_ip_proto((index + 1) * 8 - 1 downto index * 8);
+-- TC_IP_SIZE_OUT <= tc_ip_size((index + 1) * 16 - 1 downto index * 16);
+-- TC_UDP_SIZE_OUT <= tc_udp_size((index + 1) * 16 - 1 downto index * 16);
+-- TC_FLAGS_OFFSET_OUT <= tc_flags_size((index + 1) * 16 - 1 downto index * 16);
+-- PS_RESPONSE_READY_OUT <= '1';
+-- selected(index) <= '1';
+-- index := index;
+-- found := true;
+-- elsif (MC_BUSY_IN = '0') then
+-- TC_DATA_OUT <= (others => '0');
+-- TC_FRAME_SIZE_OUT <= (others => '0');
+-- TC_FRAME_TYPE_OUT <= (others => '0');
+-- TC_DEST_MAC_OUT <= (others => '0');
+-- TC_DEST_IP_OUT <= (others => '0');
+-- TC_DEST_UDP_OUT <= (others => '0');
+-- TC_SRC_MAC_OUT <= (others => '0');
+-- TC_SRC_IP_OUT <= (others => '0');
+-- TC_SRC_UDP_OUT <= (others => '0');
+-- TC_IP_PROTOCOL_OUT <= (others => '0');
+-- TC_IP_SIZE_OUT <= (others => '0');
+-- TC_UDP_SIZE_OUT <= (others => '0');
+-- TC_FLAGS_OFFSET_OUT <= (others => '0');
+-- PS_RESPONSE_READY_OUT <= '0';
+-- found := false;
+-- index := 0;
+-- else
+-- TC_DATA_OUT <= (others => '0');
+-- TC_FRAME_SIZE_OUT <= (others => '0');
+-- TC_FRAME_TYPE_OUT <= (others => '0');
+-- TC_DEST_MAC_OUT <= (others => '0');
+-- TC_DEST_IP_OUT <= (others => '0');
+-- TC_DEST_UDP_OUT <= (others => '0');
+-- TC_SRC_MAC_OUT <= (others => '0');
+-- TC_SRC_IP_OUT <= (others => '0');
+-- TC_SRC_UDP_OUT <= (others => '0');
+-- TC_IP_PROTOCOL_OUT <= (others => '0');
+-- TC_IP_SIZE_OUT <= (others => '0');
+-- TC_UDP_SIZE_OUT <= (others => '0');
+-- TC_FLAGS_OFFSET_OUT <= (others => '0');
+-- PS_RESPONSE_READY_OUT <= '0';
+-- found := false;
+-- index := 0;
+-- end if;
+-- end if;
+--
+-- end if;
+--end process SELECTOR_PROC;
+-- ***********
+
end trb_net16_gbe_protocol_selector;
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_receive_control : architecture is "GBE_MAIN_group";
-attribute syn_encoding : string;
-type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
+type load_states is (IDLE, PREPARE, READY);
signal load_current_state, load_next_state : load_states;
-attribute syn_encoding of load_current_state : signal is "onehot";
signal frames_received_ctr : std_logic_vector(31 downto 0);
signal frames_readout_ctr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(3 downto 0);
signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal reset_prioritizer : std_logic;
-signal frame_waiting : std_logic;
-- debug only
signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
protocol_prioritizer : trb_net16_gbe_protocol_prioritizer
port map(
- CLK => CLK,
- RESET => reset_prioritizer,
+ CLK => CLK,
+ RESET => reset_prioritizer,
FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
- CODE_OUT => proto_code
+ CODE_OUT => proto_code
);
reset_prioritizer <= '1' when load_current_state = IDLE else '0';
--RC_FRAME_PROTO_OUT <= proto_code when (and_all(proto_code) = '0') else (others => '0');
RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0);
---DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
---DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(11 downto 4) <= frames_received_ctr(7 downto 0);
+DEBUG_OUT(19 downto 12) <= frames_readout_ctr(7 downto 0);
+DEBUG_OUT(31 downto 20) <= bytes_rec_ctr(11 downto 0);
LOAD_MACHINE_PROC : process(CLK)
begin
when PREPARE => -- prepare frame size
state <= x"2";
- load_next_state <= WAIT_ONE; --READY;
-
- when WAIT_ONE =>
- load_next_state <= READY;
+ load_next_state <= READY;
when READY => -- wait for reading out the whole frame
state <= x"3";
end case;
end process LOAD_MACHINE;
-process(CLK)
+FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
+ else '0';
+
+RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
+ else '0';
+
+SYNC_PROC : process(CLK)
begin
- if rising_edge(CLK) then
- if (load_current_state = PREPARE) then
- FR_GET_FRAME_OUT <= '1';
- else
- FR_GET_FRAME_OUT <= '0';
- end if;
-
- if (load_current_state = READY and RC_LOADING_DONE_IN = '0') then
- RC_FRAME_WAITING_OUT <= '1';
- else
- RC_FRAME_WAITING_OUT <= '0';
- end if;
-
- --RC_FRAME_WAITING_OUT <= frame_waiting;
- end if;
-end process;
-
---FR_GET_FRAME_OUT <= '1' when (load_current_state = PREPARE)
--- else '0';
---
---RC_FRAME_WAITING_OUT <= '1' when (load_current_state = READY)
--- else '0';
-
---SYNC_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- FRAMES_RECEIVED_OUT <= frames_received_ctr;
--- --BYTES_RECEIVED_OUT <= bytes_rec_ctr;
--- BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0);
--- BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
--- BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
--- end if;
---end process SYNC_PROC;
+ if rising_edge(CLK) then
+ FRAMES_RECEIVED_OUT <= frames_received_ctr;
+ --BYTES_RECEIVED_OUT <= bytes_rec_ctr;
+ BYTES_RECEIVED_OUT(15 downto 0) <= bytes_rec_ctr(15 downto 0);
+ BYTES_RECEIVED_OUT(16 + c_MAX_PROTOCOLS - 1 downto 16) <= saved_proto;
+ BYTES_RECEIVED_OUT(31 downto 16 + c_MAX_PROTOCOLS) <= (others => '0');
+ end if;
+end process SYNC_PROC;
FRAMES_REC_CTR_PROC : process(CLK)
begin
end if;
end process FRAMES_READOUT_CTR_PROC;
--- debug only
BYTES_REC_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process BYTES_REC_CTR_PROC;
+-- debug only
SAVED_PROTO_PROC : process(CLK)
begin
if rising_edge(CLK) then
RESET : in std_logic;
-- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
type dissect_states is (IDLE, READ_FRAME, DECIDE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
+attribute syn_encoding of dissect_current_state: signal is "safe,gray";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
-
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
signal saved_opcode : std_logic_vector(15 downto 0);
signal saved_sender_ip : std_logic_vector(31 downto 0);
signal saved_target_ip : std_logic_vector(31 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
signal stat_data_temp : std_logic_vector(31 downto 0);
-signal tc_wr : std_logic;
-
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_keep of state : signal is true;
end if;
end process DISSECT_MACHINE_PROC;
-DISSECT_MACHINE : process(dissect_current_state, g_MY_IP, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, PS_SELECTED_IN, saved_target_ip)
+DISSECT_MACHINE : process(dissect_current_state, g_MY_IP, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, TC_BUSY_IN, data_ctr, PS_SELECTED_IN, saved_target_ip)
begin
case dissect_current_state is
when WAIT_FOR_LOAD =>
state <= x"4";
- if (PS_SELECTED_IN = '1') then
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
dissect_next_state <= LOAD_FRAME;
else
dissect_next_state <= WAIT_FOR_LOAD;
DATA_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') then
- data_ctr <= 1;
- elsif (dissect_current_state = WAIT_FOR_LOAD) then
+ if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') or (dissect_current_state = WAIT_FOR_LOAD) then
data_ctr <= 1;
elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
data_ctr <= data_ctr + 1;
elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame
data_ctr <= data_ctr + 1;
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then -- in case of constructing response
data_ctr <= data_ctr + 1;
end if;
end if;
end process DATA_CTR_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then
--- tc_wr <= '1';
--- else
--- tc_wr <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
SAVE_VALUES_PROC : process(CLK)
begin
if rising_edge(CLK) then
elsif (dissect_current_state = READ_FRAME) then
case (data_ctr) is
- when 6 =>
- saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0);
when 7 =>
+ saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0);
+ when 8 =>
saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0);
- when 13 =>
- saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
when 14 =>
- saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
+ saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
when 15 =>
- saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
+ saved_sender_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
when 16 =>
+ saved_sender_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
+ when 17 =>
saved_sender_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
- when 23 =>
- saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
when 24 =>
- saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
+ saved_target_ip(7 downto 0) <= PS_DATA_IN(7 downto 0);
when 25 =>
- saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
+ saved_target_ip(15 downto 8) <= PS_DATA_IN(7 downto 0);
when 26 =>
+ saved_target_ip(23 downto 16) <= PS_DATA_IN(7 downto 0);
+ when 27 =>
saved_target_ip(31 downto 24) <= PS_DATA_IN(7 downto 0);
when others => null;
TC_DATA_PROC : process(dissect_current_state, data_ctr, values)
begin
- if rising_edge(CLK) then
- tc_data(8) <= '0';
-
- if (dissect_current_state = LOAD_FRAME) then
- for i in 0 to 7 loop
- tc_data(i) <= values((data_ctr - 1) * 8 + i);
- end loop;
- -- mark the last byte
- if (data_ctr = 28) then
- tc_data(8) <= '1';
- end if;
- else
- tc_data(7 downto 0) <= (others => '0');
+ tc_data(8) <= '0';
+
+ if (dissect_current_state = LOAD_FRAME) then
+ for i in 0 to 7 loop
+ tc_data(i) <= values((data_ctr - 1) * 8 + i);
+ end loop;
+ -- mark the last byte
+ if (data_ctr = 28) then
+ tc_data(8) <= '1';
end if;
-
- TC_DATA_OUT <= tc_data;
-
- end if;
+ else
+ tc_data(7 downto 0) <= (others => '0');
+ end if;
+
end process TC_DATA_PROC;
---TC_WR_EN_OUT <= tc_wr;
+TC_DATA_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ TC_DATA_OUT <= tc_data;
+ end if;
+end process TC_DATA_SYNC;
+
+--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1';
+--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0';
PS_RESPONSE_SYNC : process(CLK)
begin
-TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size
+TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size
-TC_FRAME_TYPE_OUT <= x"0608";
-TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
-TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter
-TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter
-TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter
-TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter
-TC_IDENT_OUT <= (others => '0'); -- doesn't matter
+TC_FRAME_TYPE_OUT <= x"0608";
+TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
+TC_DEST_IP_OUT <= x"00000000"; -- doesnt matter
+TC_DEST_UDP_OUT <= x"0000"; -- doesnt matter
+TC_SRC_MAC_OUT <= g_MY_MAC;
+TC_SRC_IP_OUT <= x"00000000"; -- doesnt matter
+TC_SRC_UDP_OUT <= x"0000"; -- doesnt matter
+TC_IP_PROTOCOL_OUT <= x"00"; -- doesnt matter
+TC_IP_SIZE_OUT <= (others => '0'); -- doesn't matter
+TC_UDP_SIZE_OUT <= (others => '0'); -- doesn't matter
+TC_FLAGS_OFFSET_OUT <= (others => '0'); -- doesn't matter
-- **** statistice
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
---SENT_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- sent_frames <= (others => '0');
--- elsif (dissect_current_state = CLEANUP) then
--- sent_frames <= sent_frames + x"1";
--- end if;
--- end if;
---end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0601" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0602" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
-----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
----- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
----- ****
+REC_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
+end process REC_FRAMES_PROC;
+
+SENT_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ sent_frames <= (others => '0');
+ elsif (dissect_current_state = CLEANUP) then
+ sent_frames <= sent_frames + x"1";
+ end if;
+ end if;
+end process SENT_FRAMES_PROC;
+
+RECEIVED_FRAMES_OUT <= rec_frames;
+SENT_FRAMES_OUT <= sent_frames;
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(CLK)
+begin
+ if rising_edge(CLK) then
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0601" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0602" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+ end if;
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
+ STAT_DATA_RDY_OUT <= '1';
+ else
+ STAT_DATA_RDY_OUT <= '0';
+ end if;
+ end if;
+end process STAT_SYNC;
+--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
+
+-- **** debug
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(4) <= '0';
+DEBUG_OUT(7 downto 5) <= "000";
+DEBUG_OUT(8) <= '0';
+DEBUG_OUT(11 downto 9) <= "000";
+DEBUG_OUT(31 downto 12) <= (others => '0');
+-- ****
end trb_net16_gbe_response_constructor_ARP;
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
type main_states is (BOOTING, SENDING_DISCOVER, WAITING_FOR_OFFER, SENDING_REQUEST, WAITING_FOR_ACK, ESTABLISHED);
signal main_current_state, main_next_state : main_states;
-attribute syn_encoding of main_current_state: signal is "onehot";
+attribute syn_encoding of main_current_state: signal is "safe,gray";
type receive_states is (IDLE, DISCARD, CLEANUP, SAVE_VALUES);
signal receive_current_state, receive_next_state : receive_states;
-attribute syn_encoding of receive_current_state: signal is "onehot";
+attribute syn_encoding of receive_current_state: signal is "safe,gray";
-type discover_states is (IDLE, WAIT_FOR_LOAD, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP);
+type discover_states is (IDLE, BOOTP_HEADERS, CLIENT_IP, YOUR_IP, ZEROS1, MY_MAC, ZEROS2, VENDOR_VALS, VENDOR_VALS2, TERMINATION, CLEANUP);
signal construct_current_state, construct_next_state : discover_states;
-attribute syn_encoding of construct_current_state: signal is "onehot";
+attribute syn_encoding of construct_current_state: signal is "safe,gray";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal discarded_ctr : std_logic_vector(15 downto 0);
+
signal stat_data_temp : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
-attribute syn_keep of state, state2 : signal is true;
-attribute syn_preserve of state, state2 : signal is true;
+attribute syn_keep of state : signal is true;
+attribute syn_preserve of state : signal is true;
begin
end if;
end process CONSTRUCT_MACHINE_PROC;
-CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, PS_SELECTED_IN)
+CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, TC_BUSY_IN, PS_SELECTED_IN)
begin
case construct_current_state is
when IDLE =>
state <= x"1";
if (main_current_state = SENDING_DISCOVER) or (main_current_state = SENDING_REQUEST) then
- construct_next_state <= WAIT_FOR_LOAD;
+ construct_next_state <= BOOTP_HEADERS;
else
construct_next_state <= IDLE;
end if;
- when WAIT_FOR_LOAD =>
- state <= x"2";
- if (PS_SELECTED_IN = '1') then
- construct_next_state <= BOOTP_HEADERS;
- else
- construct_next_state <= WAIT_FOR_LOAD;
- end if;
+-- when WAIT_FOR_LOAD =>
+-- state <= x"2";
+-- if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+-- construct_next_state <= BOOTP_HEADERS;
+-- else
+-- construct_next_state <= WAIT_FOR_LOAD;
+-- end if;
when BOOTP_HEADERS =>
if (RESET = '1') or (construct_current_state = IDLE) then
load_ctr <= 0;
elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then
--- elsif (construct_current_state /= IDLE and construct_current_state /= CLEANUP and PS_SELECTED_IN = '1') then
load_ctr <= load_ctr + 1;
- else
- load_ctr <= load_ctr;
end if;
end if;
end process LOAD_CTR_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (construct_current_state /= IDLE and construct_current_state /= CLEANUP and PS_SELECTED_IN = '1') then
--- TC_WR_EN_OUT <= '1';
--- else
--- TC_WR_EN_OUT <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
TC_DATA_PROC : process(CLK, construct_current_state, load_ctr, bootp_hdr, g_MY_MAC, main_current_state)
begin
+
if rising_edge(CLK) then
- case (construct_current_state) is
-
- when BOOTP_HEADERS =>
- for i in 0 to 7 loop
- tc_data(i) <= bootp_hdr(load_ctr * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- when CLIENT_IP =>
- if (main_current_state = SENDING_DISCOVER) then
- tc_data(7 downto 0) <= x"00";
- elsif (main_current_state = SENDING_REQUEST) then
- for i in 0 to 7 loop
- tc_data(i) <= saved_proposed_ip((load_ctr - 12) * 8 + i);
- end loop;
- end if;
- tc_data(8) <= '0';
-
- when YOUR_IP =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
+
+ case (construct_current_state) is
+
+ when BOOTP_HEADERS =>
+ for i in 0 to 7 loop
+ tc_data(i) <= bootp_hdr(load_ctr * 8 + i);
+ end loop;
+ tc_data(8) <= '0';
- when ZEROS1 =>
+ when CLIENT_IP =>
+ if (main_current_state = SENDING_DISCOVER) then
tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- when MY_MAC =>
+ elsif (main_current_state = SENDING_REQUEST) then
for i in 0 to 7 loop
- tc_data(i) <= g_MY_MAC((load_ctr - 28) * 8 + i);
+ tc_data(i) <= saved_proposed_ip((load_ctr - 12) * 8 + i);
end loop;
- tc_data(8) <= '0';
+ end if;
+ tc_data(8) <= '0';
+
+ when YOUR_IP =>
+ tc_data(7 downto 0) <= x"00";
+ tc_data(8) <= '0';
+
+ when ZEROS1 =>
+ tc_data(7 downto 0) <= x"00";
+ tc_data(8) <= '0';
+
+ when MY_MAC =>
+ for i in 0 to 7 loop
+ tc_data(i) <= g_MY_MAC((load_ctr - 28) * 8 + i);
+ end loop;
+ tc_data(8) <= '0';
+
+ when ZEROS2 =>
+ tc_data(7 downto 0) <= x"00";
+ tc_data(8) <= '0';
- when ZEROS2 =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
-
- when VENDOR_VALS =>
- for i in 0 to 7 loop
- tc_data(i) <= vendor_values((load_ctr - 236) * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- -- needed only for DHCP Request message
- when VENDOR_VALS2 =>
- for i in 0 to 7 loop
- tc_data(i) <= vendor_values2((load_ctr - 258) * 8 + i);
- end loop;
- tc_data(8) <= '0';
-
- when TERMINATION =>
- tc_data(7 downto 0) <= x"ff";
- tc_data(8) <= '1';
+ when VENDOR_VALS =>
+ for i in 0 to 7 loop
+ tc_data(i) <= vendor_values((load_ctr - 236) * 8 + i);
+ end loop;
+ tc_data(8) <= '0';
- when others =>
- tc_data(7 downto 0) <= x"00";
- tc_data(8) <= '0';
+ -- needed only for DHCP Request message
+ when VENDOR_VALS2 =>
+ for i in 0 to 7 loop
+ tc_data(i) <= vendor_values2((load_ctr - 258) * 8 + i);
+ end loop;
+ tc_data(8) <= '0';
+
+ when TERMINATION =>
+ tc_data(7 downto 0) <= x"ff";
+ tc_data(8) <= '1';
- end case;
-
- TC_DATA_OUT <= tc_data;
-
+ when others =>
+ tc_data(7 downto 0) <= x"00";
+ tc_data(8) <= '0';
+
+ end case;
+
end if;
+
end process;
+--TC_DATA_SYNC : process(CLK)
+--begin
+ --if rising_edge(CLK) then
+ TC_DATA_OUT <= tc_data;
+ --end if;
+--end process TC_DATA_SYNC;
+
+
+--PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1';
+--PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1';
+
PS_RESPONSE_SYNC : process(CLK)
begin
if rising_edge(CLK) then
end process PS_RESPONSE_SYNC;
-- fixed sizes for discover and request messages
-TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109";
+TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109";
+TC_IP_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109";
+TC_UDP_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109";
-TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip
-
-TC_IDENT_OUT <= x"1" & sent_frames(11 downto 0);
+TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip
+TC_FLAGS_OFFSET_OUT <= (others => '0'); -- doesn't matter
-- **** statistics
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
+REC_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ --elsif (receive_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ elsif (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
+end process REC_FRAMES_PROC;
+
SENT_FRAMES_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end if;
end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_DISCARDED;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when LOAD_DISCARDED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_DISCARDED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0101" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0102" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when LOAD_DISCARDED =>
--- stat_data_temp <= x"0103" & discarded_ctr;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
+
+RECEIVED_FRAMES_OUT <= rec_frames;
+SENT_FRAMES_OUT <= sent_frames;
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_DISCARDED;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when LOAD_DISCARDED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_DISCARDED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(CLK)
+begin
+ if rising_edge(CLK) then
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0101" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0102" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when LOAD_DISCARDED =>
+ stat_data_temp <= x"0103" & discarded_ctr;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+ end if;
+
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
+ STAT_DATA_RDY_OUT <= '1';
+ else
+ STAT_DATA_RDY_OUT <= '0';
+ end if;
+ end if;
+end process STAT_SYNC;
+--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-- ****
-- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(7 downto 4) <= state2;
---DEBUG_OUT(11 downto 8) <= state3;
---DEBUG_OUT(15 downto 12) <= (others => '0');
---DEBUG_OUT(31 downto 16) <= discarded_ctr;
---
---DISCARDED_CTR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- discarded_ctr <= (others => '0');
--- elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
--- discarded_ctr <= discarded_ctr + x"1";
--- end if;
--- end if;
---end process DISCARDED_CTR_PROC;
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(7 downto 4) <= state2;
+DEBUG_OUT(11 downto 8) <= state3;
+DEBUG_OUT(15 downto 12) <= (others => '0');
+DEBUG_OUT(31 downto 16) <= discarded_ctr;
+
+DISCARDED_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ discarded_ctr <= (others => '0');
+ elsif (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
+ discarded_ctr <= discarded_ctr + x"1";
+ end if;
+ end if;
+end process DISCARDED_CTR_PROC;
-- ****
end trb_net16_gbe_response_constructor_DHCP;
end if;
end process FF_RD_LOCK_PROC;
+-- TODO: put a smaller fifo here
FRAME_FIFO: fifo_4096x9
port map(
Data => PS_DATA_IN,
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
+attribute syn_encoding of dissect_current_state: signal is "safe,gray";
type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
+signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
signal stat_data_temp : std_logic_vector(31 downto 0);
-signal tc_wr : std_logic;
-
-signal data_reg : std_logic_vector(511 downto 0);
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_keep of state : signal is true;
+attribute syn_preserve of state : signal is true;
begin
end if;
end process DISSECT_MACHINE_PROC;
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length)
+DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, TC_BUSY_IN, data_ctr, data_length)
begin
case dissect_current_state is
when IDLE =>
+ state <= x"1";
if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
dissect_next_state <= READ_FRAME;
else
end if;
when READ_FRAME =>
+ state <= x"2";
if (PS_DATA_IN(8) = '1') then
dissect_next_state <= WAIT_FOR_LOAD;
else
end if;
when WAIT_FOR_LOAD =>
- if (PS_SELECTED_IN = '1') then
+ state <= x"3";
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
dissect_next_state <= LOAD_FRAME;
else
dissect_next_state <= WAIT_FOR_LOAD;
end if;
when LOAD_FRAME =>
+ state <= x"4";
if (data_ctr = data_length + 1) then
dissect_next_state <= CLEANUP;
else
end if;
when CLEANUP =>
+ state <= x"5";
dissect_next_state <= IDLE;
end case;
data_ctr <= 2;
elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame
data_ctr <= data_ctr + 1;
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then -- in case of constructing response
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then -- in case of constructing response
data_ctr <= data_ctr + 1;
end if;
end if;
end process DATA_CTR_PROC;
---TC_WR_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then
--- tc_wr <= '1';
--- else
--- tc_wr <= '0';
--- end if;
--- end if;
---end process TC_WR_PROC;
-
DATA_LENGTH_PROC: process(CLK)
begin
if rising_edge(CLK) then
elsif (dissect_current_state = READ_FRAME) then
if (data_ctr < 9) then -- headers
saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0);
- elsif (data_ctr > 8) then -- data
- saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 8 - 1) * 8) <= PS_DATA_IN(7 downto 0);
end if;
elsif (dissect_current_state = LOAD_FRAME) then
saved_headers(7 downto 0) <= x"00";
end if;
end process SAVE_VALUES_PROC;
-----TODO: change it to one register 64B
---fifo : fifo_2048x8
--- PORT map(
--- Reset => RESET,
--- RPReset => RESET,
--- WrClock => CLK,
--- RdClock => CLK,
--- Data => PS_DATA_IN(7 downto 0),
--- WrEn => fifo_wr_en,
--- RdEn => fifo_rd_en,
--- Q => fifo_q,
--- Full => open,
--- Empty => open
--- );
+fifo : fifo_2048x8
+ PORT map(
+ Reset => RESET,
+ RPReset => RESET,
+ WrClock => CLK,
+ RdClock => CLK,
+ Data => PS_DATA_IN(7 downto 0),
+ WrEn => fifo_wr_en,
+ RdEn => fifo_rd_en,
+ Q => fifo_q,
+ Full => open,
+ Empty => open
+ );
-----TODO: change it to synchronous
---fifo_wr_en <= '1' when (dissect_current_state = READ_FRAME and data_ctr > 8) else '0';
---fifo_rd_en <= '1' when (dissect_current_state = LOAD_FRAME and data_ctr > 8) else '0';
+fifo_wr_en <= '1' when (dissect_current_state = READ_FRAME and data_ctr > 8) else '0';
+fifo_rd_en <= '1' when (dissect_current_state = LOAD_FRAME and data_ctr > 8) else '0';
CS_PROC : process(CLK)
begin
checksum_rrr(15 downto 0) <= (others => '0');
elsif (dissect_current_state = READ_FRAME and data_ctr > 4) then
if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then
+ --checksum(7 downto 0) <= checksum(7 downto 0) + PS_DATA_IN(7 downto 0);
checksum_l <= checksum_l + PS_DATA_IN(7 downto 0);
else
+ --checksum(15 downto 8) <= checksum(15 downto 8) + PS_DATA_IN(7 downto 0);
checksum_r <= checksum_r + PS_DATA_IN(7 downto 0);
end if;
- elsif (dissect_current_state = WAIT_FOR_LOAD) then
+ elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then
checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8);
checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8);
elsif (dissect_current_state = LOAD_FRAME and data_ctr = 2) then
TC_DATA_PROC : process(dissect_current_state, data_ctr, saved_headers, saved_data, data_length)
begin
- if rising_edge(CLK) then
- tc_data(8) <= '0';
+ tc_data(8) <= '0';
+
+ if (dissect_current_state = LOAD_FRAME) then
+ if (data_ctr < 10) then -- headers
+ for i in 0 to 7 loop
+ tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i);
+ end loop;
+ else -- data
+ for i in 0 to 7 loop
+ tc_data(i) <= fifo_q(i); --saved_data((data_ctr - 10) * 8 + i);
+ end loop;
- if (dissect_current_state = LOAD_FRAME) then
- if (data_ctr < 10) then -- headers
- for i in 0 to 7 loop
- tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i);
- end loop;
- else -- data
- for i in 0 to 7 loop
- tc_data(i) <= saved_data((data_ctr - 8 - 2) * 8 + i); --fifo_q(i);
- end loop;
-
- -- mark the last byte
- if (data_ctr = data_length + 1) then
- tc_data(8) <= '1';
- end if;
+ -- mark the last byte
+ if (data_ctr = data_length + 1) then
+ tc_data(8) <= '1';
end if;
- else
- tc_data(7 downto 0) <= (others => '0');
end if;
-
- TC_DATA_OUT <= tc_data;
-
+ else
+ tc_data(7 downto 0) <= (others => '0');
end if;
+
end process TC_DATA_PROC;
---TC_WR_EN_OUT <= tc_wr;
+TC_DATA_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ TC_DATA_OUT <= tc_data;
+ end if;
+end process TC_DATA_SYNC;
+
+
+--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1';
+--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0';
PS_RESPONSE_SYNC : process(CLK)
begin
end if;
end process PS_RESPONSE_SYNC;
-TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_UDP_OUT <= x"0000"; -- not used
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"0000"; -- not used
-TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP
-TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0);
+TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
+TC_IP_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
+TC_UDP_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
+
+TC_FRAME_TYPE_OUT <= x"0008";
+TC_DEST_UDP_OUT <= x"0000"; -- not used
+TC_SRC_MAC_OUT <= g_MY_MAC;
+TC_SRC_IP_OUT <= g_MY_IP;
+TC_SRC_UDP_OUT <= x"0000"; -- not used
+TC_IP_PROTOCOL_OUT <= X"01"; -- ICMP
+TC_FLAGS_OFFSET_OUT <= (others => '0'); -- doesn't matter
ADDR_PROC : process(CLK)
begin
end process ADDR_PROC;
-- statistics
---
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
+
+REC_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
+end process REC_FRAMES_PROC;
+
SENT_FRAMES_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end if;
end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0401" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0402" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
+
+RECEIVED_FRAMES_OUT <= rec_frames;
+SENT_FRAMES_OUT <= sent_frames;
+RECEIVED_FRAMES_OUT <= rec_frames;
+SENT_FRAMES_OUT <= sent_frames;
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(CLK)
+begin
+ if rising_edge(CLK) then
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0401" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0402" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+ end if;
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
+ STAT_DATA_RDY_OUT <= '1';
+ else
+ STAT_DATA_RDY_OUT <= '0';
+ end if;
+ end if;
+end process STAT_SYNC;
--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(4) <= '0';
+DEBUG_OUT(7 downto 5) <= "000";
+DEBUG_OUT(8) <= '0';
+DEBUG_OUT(11 downto 9) <= "000";
+DEBUG_OUT(31 downto 12) <= (others => '0');
-- ****
end trb_net16_gbe_response_constructor_Ping;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
---********
--- Response Constructor which responds to Ping messages
---
-
-entity trb_net16_gbe_response_constructor_PseudoPing is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_PseudoPing;
-
-
-architecture trb_net16_gbe_response_constructor_PseudoPing of trb_net16_gbe_response_constructor_PseudoPing is
-
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_response_constructor_Ping : architecture is "GBE_MAIN_group";
-
-attribute syn_encoding : string;
-
-type dissect_states is (IDLE, READ_FRAME, GENERATE_DATA, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "safe,gray";
-
-type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
-signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "safe,gray";
-
-signal rec_frames : std_logic_vector(15 downto 0);
-signal sent_frames : std_logic_vector(15 downto 0);
-
-signal saved_data : std_logic_vector(447 downto 0);
-signal saved_headers : std_logic_vector(63 downto 0);
-
-signal data_ctr : integer range 1 to 1500;
-signal data_length : integer range 1 to 1500;
-signal tc_data : std_logic_vector(8 downto 0);
-
-signal checksum : std_logic_vector(15 downto 0);
-
-signal checksum_l, checksum_r : std_logic_vector(19 downto 0);
-signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0);
-signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0);
-
-signal fifo_wr_en, fifo_rd_en : std_logic;
-signal fifo_q : std_logic_vector(7 downto 0);
-
-
-signal stat_data_temp : std_logic_vector(31 downto 0);
-
-signal tc_wr : std_logic;
-
-signal data_reg : std_logic_vector(511 downto 0);
-signal fifo_data : std_logic_vector(7 downto 0);
-signal gen_ctr : std_logic_vector(15 downto 0);
-signal size_left : std_logic_vector(15 downto 0);
-
-begin
-
---DISSECT_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- dissect_current_state <= IDLE;
--- else
--- dissect_current_state <= dissect_next_state;
--- end if;
--- end if;
---end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length, gen_ctr, size_left, PS_SELECTED_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- dissect_next_state <= READ_FRAME;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when READ_FRAME =>
- if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= GENERATE_DATA;
- else
- dissect_next_state <= READ_FRAME;
- end if;
-
- when GENERATE_DATA =>
- if (gen_ctr = x"07ff") then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= GENERATE_DATA;
- end if;
-
- when WAIT_FOR_LOAD =>
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD_FRAME;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD_FRAME =>
- if (size_left = x"0000") then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD_FRAME;
- end if;
-
- when CLEANUP =>
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-fifo : fifo_2048x8
- PORT map(
- Reset => RESET,
- RPReset => RESET,
- WrClock => CLK,
- RdClock => CLK,
- Data => fifo_data,
- WrEn => fifo_wr_en,
- RdEn => fifo_rd_en, --TC_RD_EN_IN,
- Q => fifo_q,
- Full => open,
- Empty => open
- );
-
-fifo_rd_en <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0';
-fifo_wr_en <= '1' when dissect_current_state = GENERATE_DATA else '0';
-fifo_data <= gen_ctr(7 downto 0);
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE or dissect_current_state = CLEANUP) then
- gen_ctr <= (others => '0');
- elsif (dissect_current_state = GENERATE_DATA) then
- gen_ctr <= gen_ctr + x"1";
- else
- gen_ctr <= gen_ctr;
- end if;
- end if;
-end process;
-
-
-TC_DATA_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = LOAD_FRAME and size_left = x"0000") then
- tc_data(8) <= '1';
- else
- tc_data(8) <= '0';
- end if;
-
- tc_data(7 downto 0) <= fifo_q;
- end if;
-end process TC_DATA_PROC;
-
-TC_DATA_OUT <= tc_data;
-
-PS_RESPONSE_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
- PS_RESPONSE_READY_OUT <= '1';
- else
- PS_RESPONSE_READY_OUT <= '0';
- end if;
-
- if (dissect_current_state = IDLE) then
- PS_BUSY_OUT <= '0';
- else
- PS_BUSY_OUT <= '1';
- end if;
- end if;
-end process PS_RESPONSE_SYNC;
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = GENERATE_DATA) then
- size_left <= x"0500";
- elsif (dissect_current_state = LOAD_FRAME) then
- size_left <= size_left - x"1";
- else
- size_left <= size_left;
- end if;
- end if;
-end process;
-
-TC_FRAME_SIZE_OUT <= x"0500";
-
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_UDP_OUT <= x"c350"; -- not used
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"c350"; -- not used
-TC_IP_PROTOCOL_OUT <= X"11"; -- ICMP
-TC_IDENT_OUT <= x"2" & sent_frames(11 downto 0);
-
-ADDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = READ_FRAME) then
- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
- TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;
- end if;
- end if;
-end process ADDR_PROC;
-
--- statistics
---
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
-SENT_FRAMES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_frames <= (others => '0');
- elsif (dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '1') then
- sent_frames <= sent_frames + x"1";
- end if;
- end if;
-end process SENT_FRAMES_PROC;
---
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---RECEIVED_FRAMES_OUT <= rec_frames;
---SENT_FRAMES_OUT <= sent_frames;
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN, dissect_current_state)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
--- stats_next_state <= LOAD_SENT;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_SENT =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= LOAD_SENT;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_SENT =>
--- stat_data_temp <= x"0401" & sent_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0402" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
---STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-
--- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
--- ****
-
-end trb_net16_gbe_response_constructor_PseudoPing;
-
-
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_BUSY_IN : in std_logic;
+
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
STAT_DATA_RDY_OUT : out std_logic;
attribute syn_encoding : string;
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
-type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_A_WORD, WAIT_ONE, WAIT_TWO, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
---type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP);
+type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_TC, DIVIDE, WAIT_FOR_LOAD, CLEANUP, WAIT_FOR_LOAD_ACK, LOAD_ACK);
signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state: signal is "onehot";
+attribute syn_encoding of dissect_current_state: signal is "safe,gray";
type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP);
signal stats_current_state, stats_next_state : stats_states;
-attribute syn_encoding of stats_current_state : signal is "onehot";
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
signal saved_target_ip : std_logic_vector(31 downto 0);
signal data_ctr : integer range 0 to 30;
+signal state : std_logic_vector(3 downto 0);
signal stat_data_temp : std_logic_vector(31 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal rx_fifo_q : std_logic_vector(17 downto 0);
-signal rx_fifo_qq : std_logic_vector(17 downto 0);
signal rx_fifo_wr, rx_fifo_rd : std_logic;
signal tx_eod, rx_eod : std_logic;
signal tx_fifo_reset : std_logic;
signal gsc_reply_read : std_logic;
signal gsc_init_dataready : std_logic;
-signal gsc_init_dataready_q : std_logic;
signal tx_data_ctr : std_logic_vector(15 downto 0);
signal tx_loaded_ctr : std_logic_vector(15 downto 0);
signal make_reset : std_logic := '0';
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_keep of tx_data_ctr, tx_loaded_ctr, state : signal is true;
+attribute syn_preserve of tx_data_ctr, tx_loaded_ctr, state : signal is true;
+
+signal temp_ctr : std_logic_vector(7 downto 0);
+
+signal gsc_init_read_q : std_logic;
signal fifo_rd_q : std_logic;
signal too_much_data : std_logic;
signal rx_fifo_data : std_logic_vector(8 downto 0);
signal tx_fifo_data : std_logic_vector(17 downto 0);
-signal tc_wr : std_logic;
-signal state : std_logic_vector(3 downto 0);
-signal saved_hdr_1 : std_logic_vector(7 downto 0) := x"ab";
-signal saved_hdr_2 : std_logic_vector(7 downto 0) := x"cd";
-signal saved_hdr_ctr : std_logic_vector(3 downto 0);
-
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_keep of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;
-attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr, tx_fifo_rd, gsc_reply_read, state : signal is true;
-
-
begin
MAKE_RESET_OUT <= make_reset;
Empty => rx_empty
);
---TODO: change to synchronous
+--rx_fifo_wr <= '1' when PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' else '0';
rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or
(gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or
(dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')
else '0'; -- preload first word
-RX_FIFO_WR_SYNC : process(CLK)
+RX_FIFO_SYNC : process(CLK)
begin
if rising_edge(CLK) then
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and (saved_hdr_ctr = "0100" or saved_hdr_ctr = "1000")) then
+ if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
rx_fifo_wr <= '1';
else
rx_fifo_wr <= '0';
end if;
- rx_fifo_data <= PS_DATA_IN;
- end if;
-end process RX_FIFO_WR_SYNC;
-
-SAVED_HDR_CTR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = IDLE and PS_WR_EN_IN = '0' and PS_ACTIVATE_IN = '0') then
- saved_hdr_ctr <= "0001";
- elsif (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr /= "1000") then
- saved_hdr_ctr(3 downto 0) <= saved_hdr_ctr(2 downto 0) & '0';
- else
- saved_hdr_ctr <= saved_hdr_ctr;
- end if;
- end if;
-end process SAVED_HDR_CTR_PROC;
-
-SAVED_HDR_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
- if (saved_hdr_ctr = "0001") then
- saved_hdr_1 <= PS_DATA_IN(7 downto 0);
- saved_hdr_2 <= saved_hdr_2;
- elsif (saved_hdr_ctr = "0010") then
- saved_hdr_2 <= PS_DATA_IN(7 downto 0);
- saved_hdr_1 <= saved_hdr_1;
- else
- saved_hdr_1 <= saved_hdr_1;
- saved_hdr_2 <= saved_hdr_2;
- end if;
- else
- saved_hdr_1 <= saved_hdr_1;
- saved_hdr_2 <= saved_hdr_2;
- end if;
- end if;
-end process SAVED_HDR_PROC;
-
---RX_FIFO_RD_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
---
--- if (dissect_current_state = LOAD_A_WORD) then
+-- if (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) then
+-- rx_fifo_rd <= '1';
+-- elsif (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then
+-- rx_fifo_rd <= '1';
+-- elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then
-- rx_fifo_rd <= '1';
-- else
-- rx_fifo_rd <= '0';
-- end if;
---
----- if (dissect_current_state = WAIT_ONE) then
----- gsc_init_dataready <= '1';
----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '0') then
----- gsc_init_dataready <= '1';
----- else
----- gsc_init_dataready <= '0';
----- end if;
---
----- if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then -- preload the first byte
----- rx_fifo_rd <= '1';
----- elsif (dissect_current_state = LOAD_TO_HUB) then
----- rx_fifo_rd <= '1';
----- elsif (dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then
----- rx_fifo_rd <= '1';
----- else
----- rx_fifo_rd <= '0';
----- end if;
-----
----- if (dissect_current_state = WAIT_FOR_HUB) then
----- gsc_init_dataready <= '1';
----- elsif (dissect_current_state = LOAD_TO_HUB and GSC_INIT_READ_IN = '1') then
----- gsc_init_dataready <= '1';
----- else
----- gsc_init_dataready <= '0';
----- end if;
-----
----- if (dissect_current_state = WAIT_FOR_HUB) then
----- packet_num <= "100";
----- elsif (dissect_current_state = LOAD_TO_HUB) then
----- if (gsc_init_dataready = '1' and packet_num = "100") then
----- packet_num <= "000";
----- elsif (gsc_init_dataready = '1' and packet_num /= "100") then
----- packet_num <= packet_num + "1";
----- else
----- packet_num <= packet_num;
----- end if;
----- else
----- packet_num <= packet_num;
----- end if;
---
--- if (dissect_current_state = READ_FRAME) then
--- packet_num <= "011";
--- elsif (dissect_current_state = LOAD_A_WORD) then
--- if (packet_num = "100") then
--- packet_num <= "000";
--- else
--- packet_num <= packet_num + "1";
--- end if;
--- else
--- packet_num <= packet_num;
--- end if;
---
+
-- GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9);
-- GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
--
--- --GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;
---
----- GSC_INIT_PACKET_NUM_OUT <= packet_num;
---
--- end if;
---end process RX_FIFO_RD_SYNC;
---
---GSC_INIT_DATAREADY_OUT <= '1' when dissect_current_state = WAIT_FOR_HUB else '0';
+-- if (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or (dissect_current_state = WAIT_FOR_HUB) then
+-- gsc_init_dataready <= '1';
+-- else
+-- gsc_init_dataready <= '0';
+-- end if;
+
+ rx_fifo_data <= PS_DATA_IN;
+ end if;
+end process RX_FIFO_SYNC;
-----TODO: add a register
GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9);
-GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
+GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
------- TODO: change it to synchronous
GSC_INIT_PACKET_NUM_OUT <= packet_num;
GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;
gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or
(dissect_current_state = WAIT_FOR_HUB) else '0';
-
+
PACKET_NUM_PROC : process(CLK)
begin
if rising_edge(CLK) then
if (RESET = '1') or (dissect_current_state = IDLE) then
packet_num <= "100";
- elsif (GSC_INIT_READ_IN = '1' and rx_fifo_rd = '1' and packet_num = "100") then
+ elsif (GSC_INIT_READ_IN = '1' and gsc_init_dataready = '1' and packet_num = "100") then
packet_num <= "000";
elsif (rx_fifo_rd = '1' and packet_num /= "100") then
packet_num <= packet_num + "1";
end if;
end process PACKET_NUM_PROC;
---temporairly changed to a smaller fifo
-transmit_fifo : fifo_4kx18x9 --fifo_65536x18x9
+transmit_fifo : fifo_65536x18x9
PORT map(
Reset => tx_fifo_reset,
RPReset => tx_fifo_reset,
Full => tx_full,
Empty => tx_empty
);
+
+tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);
+tx_fifo_data(8) <= '0';
+tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
+tx_fifo_data(17) <= '0';
-TX_FIFO_WR_SYNC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
- tx_fifo_wr <= '1';
- elsif (saved_hdr_ctr = "0010") then
- tx_fifo_wr <= '1';
- else
- tx_fifo_wr <= '0';
- end if;
-
- if (saved_hdr_ctr = "010") then
- tx_fifo_data <= '0' & PS_DATA_IN(7 downto 0) & '0' & x"02";
- else
- tx_fifo_data(7 downto 0) <= GSC_REPLY_DATA_IN(15 downto 8);
- tx_fifo_data(8) <= '0';
- tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
- tx_fifo_data(17) <= '0';
- end if;
- end if;
-end process TX_FIFO_WR_SYNC;
+tx_fifo_wr <= '1' when (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') else '0';
+tx_fifo_reset <= '1' when (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) else '0';
+tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and dissect_current_state = LOAD_FRAME and (tx_frame_loaded /= g_MAX_FRAME_SIZE) else '0';
---TX_FIFO_RD_SYNC : process(CLK)
+--TX_FIFO_SYNC_PROC : process(CLK)
--begin
-- if rising_edge(CLK) then
--- if (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and tx_frame_loaded /= g_MAX_FRAME_SIZE) then
--- tx_fifo_rd <= '1';
+-- if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
+-- tx_fifo_wr <= '1';
-- else
--- tx_fifo_rd <= '0';
--- end if;
+-- tx_fifo_wr <= '0';
+-- end if;
-- end if;
---end process TX_FIFO_RD_SYNC;
-tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' else '0';
-
-TX_FIFO_SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) then
- tx_fifo_reset <= '1';
- else
- tx_fifo_reset <= '0';
- end if;
- end if;
-end process TX_FIFO_SYNC_PROC;
+--end process TX_FIFO_SYNC_PROC;
-TC_DATA_PROC : process(CLK)
+TC_DATA_PROC : process(dissect_current_state, tx_loaded_ctr, tx_data_ctr, tx_frame_loaded, g_MAX_FRAME_SIZE)
begin
- if rising_edge(CLK) then
-
- TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
+ if (dissect_current_state = LOAD_FRAME) then
- --if (tx_loaded_ctr = tx_data_ctr + x"1" or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
- if (tx_loaded_ctr = tx_data_ctr) then
- TC_DATA_OUT(8) <= '1';
+ TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
+
+ if (tx_loaded_ctr = tx_data_ctr or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
+ TC_DATA_OUT(8) <= '1';
+ else
+ TC_DATA_OUT(8) <= '0';
+ end if;
+
+ elsif (dissect_current_state = LOAD_ACK) then
+
+ TC_DATA_OUT(7 downto 0) <= tx_loaded_ctr(7 downto 0);
+
+ if (tx_loaded_ctr = x"0010" + x"1") then
+ TC_DATA_OUT(8) <= '1';
+ else
+ TC_DATA_OUT(8) <= '0';
+ end if;
else
- TC_DATA_OUT(8) <= '0';
+ TC_DATA_OUT <= (others => '0');
end if;
- end if;
end process TC_DATA_PROC;
-GSC_REPLY_READ_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE) then
- gsc_reply_read <= '1';
- else
- gsc_reply_read <= '0';
- end if;
- end if;
-end process GSC_REPLY_READ_PROC;
GSC_REPLY_READ_OUT <= gsc_reply_read;
+gsc_reply_read <= '1' when dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE else '0';
-- counter of data received from TRBNet hub
TX_DATA_CTR_PROC : process(CLK)
if (RESET = '1' or dissect_current_state = IDLE) then
tx_data_ctr <= (others => '0');
elsif (tx_fifo_wr = '1') then
- tx_data_ctr <= tx_data_ctr + x"2";
+ tx_data_ctr(15 downto 1) <= tx_data_ctr(15 downto 1) + x"1";
end if;
end if;
end process TX_DATA_CTR_PROC;
TX_LOADED_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1' or dissect_current_state = IDLE) then
- tx_loaded_ctr <= x"0000";
- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1') then
+ if (RESET = '1' or dissect_current_state = IDLE or dissect_current_state = WAIT_FOR_HUB) then
+ tx_loaded_ctr <= (others => '0');
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' and (tx_frame_loaded /= g_MAX_FRAME_SIZE)) then
+ tx_loaded_ctr <= tx_loaded_ctr + x"1";
+ elsif (dissect_current_state = LOAD_ACK and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then
tx_loaded_ctr <= tx_loaded_ctr + x"1";
end if;
end if;
end process TX_LOADED_CTR_PROC;
+
+--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1';
+--
+--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or
+-- dissect_current_state = CLEANUP or dissect_current_state = WAIT_FOR_LOAD_ACK or
+-- dissect_current_state = LOAD_ACK or dissect_current_state = DIVIDE) and (too_much_data = '0')
+-- else '0';
PS_RESPONSE_SYNC : process(CLK)
begin
if (too_much_data = '0') then
if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then
PS_RESPONSE_READY_OUT <= '1';
+ elsif (dissect_current_state = WAIT_FOR_LOAD_ACK or dissect_current_state = LOAD_ACK or dissect_current_state = DIVIDE) then
+ PS_RESPONSE_READY_OUT <= '1';
else
PS_RESPONSE_READY_OUT <= '0';
end if;
TC_FRAME_TYPE_OUT <= x"0008";
TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;
-TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8);
-TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0);
+TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); --x"a861";
+TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); --x"a861";
TC_SRC_MAC_OUT <= g_MY_MAC;
TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= x"9065"; --x"a861";
+TC_SRC_UDP_OUT <= x"a861";
TC_IP_PROTOCOL_OUT <= x"11";
-TC_IDENT_OUT <= x"3" & reply_ctr(11 downto 0);
-TC_FRAME_SIZE_OUT <= tx_data_ctr;
+FRAME_SIZE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = IDLE) then
+ TC_FRAME_SIZE_OUT <= (others => '0');
+ TC_IP_SIZE_OUT <= (others => '0');
+ elsif (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = DIVIDE) then
+ if (size_left >= g_MAX_FRAME_SIZE) then
+ TC_FRAME_SIZE_OUT <= g_MAX_FRAME_SIZE;
+ TC_IP_SIZE_OUT <= g_MAX_FRAME_SIZE;
+ else
+ TC_FRAME_SIZE_OUT <= size_left(15 downto 0);
+ TC_IP_SIZE_OUT <= size_left(15 downto 0);
+ end if;
+ elsif (dissect_current_state = WAIT_FOR_LOAD_ACK) then
+ TC_FRAME_SIZE_OUT <= x"0010";
+ TC_IP_SIZE_OUT <= x"0010";
+ end if;
+ end if;
+end process FRAME_SIZE_PROC;
+
+TC_UDP_SIZE_OUT <= tx_data_ctr;
---FRAME_SIZE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1' or dissect_current_state = IDLE) then
--- TC_FRAME_SIZE_OUT <= (others => '0');
--- TC_IP_SIZE_OUT <= (others => '0');
--- elsif (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = DIVIDE) then
--- if (size_left >= g_MAX_FRAME_SIZE) then
--- TC_FRAME_SIZE_OUT <= g_MAX_FRAME_SIZE;
--- TC_IP_SIZE_OUT <= g_MAX_FRAME_SIZE;
--- else
--- TC_FRAME_SIZE_OUT <= size_left(15 downto 0);
--- TC_IP_SIZE_OUT <= size_left(15 downto 0);
--- end if;
--- end if;
--- end if;
---end process FRAME_SIZE_PROC;
---
---TC_UDP_SIZE_OUT <= tx_data_ctr;
---
---TC_FLAGS_OFFSET_OUT(15 downto 14) <= "00";
---MORE_FRAGMENTS_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = CLEANUP) then
--- TC_FLAGS_OFFSET_OUT(13) <= '0';
--- elsif ((dissect_current_state = DIVIDE and PS_SELECTED_IN = '1') or (dissect_current_state = WAIT_FOR_LOAD)) then
--- if ((tx_data_ctr - tx_loaded_ctr) < g_MAX_FRAME_SIZE) then
--- TC_FLAGS_OFFSET_OUT(13) <= '0'; -- no more fragments
--- else
--- TC_FLAGS_OFFSET_OUT(13) <= '1'; -- more fragments
--- end if;
--- end if;
--- end if;
---end process MORE_FRAGMENTS_PROC;
---
---OFFSET_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = CLEANUP) then
--- TC_FLAGS_OFFSET_OUT(12 downto 0) <= (others => '0');
--- elsif (dissect_current_state = DIVIDE and PS_SELECTED_IN = '1') then
--- TC_FLAGS_OFFSET_OUT(12 downto 0) <= tx_loaded_ctr(15 downto 3) + x"1";
--- end if;
--- end if;
---end process OFFSET_PROC;
+
+TC_FLAGS_OFFSET_OUT(15 downto 14) <= "00";
+MORE_FRAGMENTS_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = CLEANUP) then
+ TC_FLAGS_OFFSET_OUT(13) <= '0';
+ elsif ((dissect_current_state = DIVIDE and TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') or (dissect_current_state = WAIT_FOR_LOAD)) then
+ if ((tx_data_ctr - tx_loaded_ctr) < g_MAX_FRAME_SIZE) then
+ TC_FLAGS_OFFSET_OUT(13) <= '0'; -- no more fragments
+ else
+ TC_FLAGS_OFFSET_OUT(13) <= '1'; -- more fragments
+ end if;
+ end if;
+ end if;
+end process MORE_FRAGMENTS_PROC;
+
+OFFSET_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = CLEANUP) then
+ TC_FLAGS_OFFSET_OUT(12 downto 0) <= (others => '0');
+ elsif (dissect_current_state = DIVIDE and TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+ TC_FLAGS_OFFSET_OUT(12 downto 0) <= tx_loaded_ctr(15 downto 3) + x"1";
+ end if;
+ end if;
+end process OFFSET_PROC;
DISSECT_MACHINE_PROC : process(CLK)
begin
end if;
end process DISSECT_MACHINE_PROC;
-DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN, tx_frame_loaded, g_MAX_FRAME_SIZE)
+DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, TC_BUSY_IN, data_ctr, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN, tx_frame_loaded, g_MAX_FRAME_SIZE)
begin
case dissect_current_state is
when IDLE =>
- state <= x"0";
+ state <= x"1";
if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
dissect_next_state <= READ_FRAME;
else
end if;
when READ_FRAME =>
- state <= x"1";
+ state <= x"2";
if (PS_DATA_IN(8) = '1') then
- dissect_next_state <= WAIT_FOR_HUB;
+ --if (reset_detected = '1') then -- send ack only if reset command came
+ -- dissect_next_state <= WAIT_FOR_LOAD_ACK;
+ --else
+ dissect_next_state <= WAIT_FOR_HUB;
+ --end if;
else
dissect_next_state <= READ_FRAME;
end if;
+
+-- when WAIT_FOR_LOAD_ACK =>
+-- state <= x"a";
+-- if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+-- dissect_next_state <= LOAD_ACK;
+-- else
+-- dissect_next_state <= WAIT_FOR_LOAD_ACK;
+-- end if;
--
--- when LOAD_A_WORD =>
--- state <= x"2";
--- dissect_next_state <= WAIT_ONE; --WAIT_FOR_HUB;
---
--- when WAIT_ONE =>
--- state <= x"3";
--- dissect_next_state <= WAIT_TWO; --WAIT_FOR_HUB;
---
--- when WAIT_TWO =>
--- state <= x"4";
--- dissect_next_state <= WAIT_FOR_HUB;
+-- when LOAD_ACK =>
+-- state <= x"b";
+-- if (tx_loaded_ctr = x"0010") then
+-- dissect_next_state <= WAIT_FOR_HUB; --CLEANUP;
+-- else
+-- dissect_next_state <= LOAD_ACK;
+-- end if;
when WAIT_FOR_HUB =>
- state <= x"5";
+ state <= x"3";
if (GSC_INIT_READ_IN = '1') then
dissect_next_state <= LOAD_TO_HUB;
else
end if;
when LOAD_TO_HUB =>
- state <= x"3";
+ state <= x"4";
if (rx_fifo_q(17) = '1') then
if (reset_detected = '1') then
dissect_next_state <= CLEANUP;
end if;
when WAIT_FOR_RESPONSE =>
- state <= x"6";
+ state <= x"5";
if (GSC_REPLY_DATAREADY_IN = '1') then
dissect_next_state <= SAVE_RESPONSE;
else
end if;
when SAVE_RESPONSE =>
- state <= x"7";
+ state <= x"6";
if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
if (too_much_data = '0') then
dissect_next_state <= WAIT_FOR_LOAD;
end if;
when WAIT_FOR_LOAD =>
- state <= x"8";
- if (PS_SELECTED_IN = '1') then
+ state <= x"7";
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
dissect_next_state <= LOAD_FRAME;
else
dissect_next_state <= WAIT_FOR_LOAD;
end if;
-
+
when LOAD_FRAME =>
- state <= x"9";
+ state <= x"8";
if (tx_loaded_ctr = tx_data_ctr) then
dissect_next_state <= CLEANUP;
+ elsif (tx_frame_loaded = g_MAX_FRAME_SIZE) then
+ dissect_next_state <= DIVIDE;
else
dissect_next_state <= LOAD_FRAME;
end if;
+
+ when DIVIDE =>
+ state <= x"c";
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+ dissect_next_state <= LOAD_FRAME;
+ else
+ dissect_next_state <= DIVIDE;
+ end if;
when CLEANUP =>
- state <= x"b";
+ state <= x"9";
+ dissect_next_state <= IDLE;
+
+ when others =>
+ state <= x"1";
dissect_next_state <= IDLE;
end case;
end process DISSECT_MACHINE;
----- counter of bytes of currently constructed frame
---FRAME_LOADED_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1' or dissect_current_state = DIVIDE or dissect_current_state = IDLE) then
--- tx_frame_loaded <= (others => '0');
--- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1') then
--- tx_frame_loaded <= tx_frame_loaded + x"1";
--- end if;
--- end if;
---end process FRAME_LOADED_PROC;
---
----- counter down to 0 of bytes that have to be transmitted for a given packet
---SIZE_LEFT_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1' or dissect_current_state = SAVE_RESPONSE) then
--- size_left <= (others => '0');
--- elsif (dissect_current_state = WAIT_FOR_LOAD) then
--- size_left <= tx_data_ctr;
--- elsif (dissect_current_state = LOAD_FRAME and PS_SELECTED_IN = '1' and (tx_frame_loaded /= g_MAX_FRAME_SIZE)) then
--- size_left <= size_left - x"1";
--- end if;
--- end if;
---end process SIZE_LEFT_PROC;
+-- counter of bytes of currently constructed frame
+FRAME_LOADED_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = DIVIDE or dissect_current_state = IDLE) then
+ tx_frame_loaded <= (others => '0');
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then
+ tx_frame_loaded <= tx_frame_loaded + x"1";
+ end if;
+ end if;
+end process FRAME_LOADED_PROC;
+
+-- counter down to 0 of bytes that have to be transmitted for a given packet
+SIZE_LEFT_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = SAVE_RESPONSE) then
+ size_left <= (others => '0');
+ elsif (dissect_current_state = WAIT_FOR_LOAD) then
+ size_left <= tx_data_ctr;
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1' and (tx_frame_loaded /= g_MAX_FRAME_SIZE)) then
+ size_left <= size_left - x"1";
+ end if;
+ end if;
+end process SIZE_LEFT_PROC;
-- reset request packet detection
- RESET_DETECTED_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1' or dissect_current_state = CLEANUP) then
- reset_detected <= '0';
- elsif (PS_DATA_IN(7 downto 0) = x"80" and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' and saved_hdr_ctr = "0100") then--and dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- first byte as 0x80
- reset_detected <= '1';
- end if;
- end if;
- end process RESET_DETECTED_PROC;
-
- MAKE_RESET_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- make_reset <= '0';
- elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
- make_reset <= '1';
- end if;
- end if;
- end process MAKE_RESET_PROC;
+RESET_DETECTED_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = CLEANUP) then
+ reset_detected <= '0';
+ elsif (PS_DATA_IN(7 downto 0) = x"80" and dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- first byte as 0x80
+ reset_detected <= '1';
+ end if;
+ end if;
+end process RESET_DETECTED_PROC;
+
+MAKE_RESET_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ make_reset <= '0';
+ elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
+ make_reset <= '1';
+ end if;
+ end if;
+end process MAKE_RESET_PROC;
-- statistics
---REC_FRAMES_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rec_frames <= (others => '0');
--- elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
--- rec_frames <= rec_frames + x"1";
--- end if;
--- end if;
---end process REC_FRAMES_PROC;
---
--- needed for identification
+REC_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
+end process REC_FRAMES_PROC;
+
REPLY_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end if;
end process REPLY_CTR_PROC;
---
---
---STATS_MACHINE_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- stats_current_state <= IDLE;
--- else
--- stats_current_state <= stats_next_state;
--- end if;
--- end if;
---end process STATS_MACHINE_PROC;
---
---STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr)
---begin
---
--- case (stats_current_state) is
---
--- when IDLE =>
--- if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then
--- stats_next_state <= LOAD_RECEIVED;
--- else
--- stats_next_state <= IDLE;
--- end if;
---
--- when LOAD_RECEIVED =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= LOAD_REPLY;
--- else
--- stats_next_state <= LOAD_RECEIVED;
--- end if;
---
--- when LOAD_REPLY =>
--- if (STAT_DATA_ACK_IN = '1') then
--- stats_next_state <= CLEANUP;
--- else
--- stats_next_state <= LOAD_REPLY;
--- end if;
---
--- when CLEANUP =>
--- stats_next_state <= IDLE;
---
--- end case;
---
---end process STATS_MACHINE;
---
---SELECTOR : process(CLK)
---begin
--- if rising_edge(CLK) then
--- case(stats_current_state) is
---
--- when LOAD_RECEIVED =>
--- stat_data_temp <= x"0502" & rec_frames;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
---
--- when LOAD_REPLY =>
--- stat_data_temp <= x"0503" & reply_ctr;
--- STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
---
--- when others =>
--- stat_data_temp <= (others => '0');
--- STAT_ADDR_OUT <= (others => '0');
---
--- end case;
--- end if;
---end process SELECTOR;
---
---STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
---STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
---STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
---STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
---
---STAT_SYNC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
--- STAT_DATA_RDY_OUT <= '1';
--- else
--- STAT_DATA_RDY_OUT <= '0';
--- end if;
--- end if;
---end process STAT_SYNC;
-----STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
---
----- end of statistics
---
----- **** debug
---DEBUG_OUT(3 downto 0) <= state;
---DEBUG_OUT(4) <= '0';
---DEBUG_OUT(7 downto 5) <= "000";
---DEBUG_OUT(8) <= '0';
---DEBUG_OUT(11 downto 9) <= "000";
---DEBUG_OUT(31 downto 12) <= (others => '0');
----- ****
+
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_REPLY;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when LOAD_REPLY =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_REPLY;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(CLK)
+begin
+ if rising_edge(CLK) then
+ case(stats_current_state) is
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0502" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_REPLY =>
+ stat_data_temp <= x"0503" & reply_ctr;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+ end if;
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then
+ STAT_DATA_RDY_OUT <= '1';
+ else
+ STAT_DATA_RDY_OUT <= '0';
+ end if;
+ end if;
+end process STAT_SYNC;
+--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
+
+-- end of statistics
+
+-- **** debug
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(4) <= '0';
+DEBUG_OUT(7 downto 5) <= "000";
+DEBUG_OUT(8) <= '0';
+DEBUG_OUT(11 downto 9) <= "000";
+DEBUG_OUT(31 downto 12) <= (others => '0');
+-- ****
end architecture RTL;
-- simply clears the fifo from garbage
entity trb_net16_gbe_response_constructor_Trash is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
TC_BUSY_IN : in std_logic;
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-
-entity trb_net16_gbe_response_constructor_TrbNetData is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end trb_net16_gbe_response_constructor_TrbNetData;
-
-
-architecture trb_net16_gbe_response_constructor_TrbNetData of trb_net16_gbe_response_constructor_TrbNetData is
-
-attribute syn_encoding : string;
-
-signal ip_cfg_start : std_logic;
-signal ip_cfg_bank : std_logic_vector(3 downto 0);
-signal ip_cfg_done : std_logic;
-signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
-signal ip_cfg_mem_clk : std_logic;
-
-signal ic_dest_mac : std_logic_vector(47 downto 0);
-signal ic_dest_ip : std_logic_vector(31 downto 0);
-signal ic_dest_udp : std_logic_vector(15 downto 0);
-signal ic_src_mac : std_logic_vector(47 downto 0);
-signal ic_src_ip : std_logic_vector(31 downto 0);
-signal ic_src_udp : std_logic_vector(15 downto 0);
-
-signal pc_wr_en : std_logic;
-signal pc_data : std_logic_vector(7 downto 0);
-signal pc_eod : std_logic;
-signal pc_sos : std_logic;
-signal pc_ready : std_logic;
-signal pc_padding : std_logic;
-signal pc_event_id : std_logic_vector(31 downto 0);
-signal pc_sub_size : std_logic_vector(31 downto 0);
-signal pc_trig_nr : std_logic_vector(31 downto 0);
-signal pc_eos : std_logic;
-signal pc_transmit_on : std_logic;
-
-signal tc_rd_en : std_logic;
-signal tc_data : std_logic_vector(8 downto 0);
-signal tc_size : std_logic_vector(15 downto 0);
-signal tc_sod : std_logic;
-signal pc_trig_type : std_logic_vector(3 downto 0);
-
-type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP);
-signal dissect_current_state, dissect_next_state : dissect_states;
-attribute syn_encoding of dissect_current_state : signal is "onehot";
-
-signal event_bytes : std_logic_vector(15 downto 0);
-signal loaded_bytes : std_logic_vector(15 downto 0);
-signal sent_packets : std_logic_vector(15 downto 0);
-
-begin
-
-
-THE_IP_CONFIGURATOR: ip_configurator
-port map(
- CLK => CLK,
- RESET => RESET,
- -- configuration interface
- START_CONFIG_IN => ip_cfg_start,
- BANK_SELECT_IN => ip_cfg_bank,
- CONFIG_DONE_OUT => ip_cfg_done,
- MEM_ADDR_OUT => ip_cfg_mem_addr,
- MEM_DATA_IN => ip_cfg_mem_data,
- MEM_CLK_OUT => ip_cfg_mem_clk,
- -- information for IP cores
- DEST_MAC_OUT => ic_dest_mac,
- DEST_IP_OUT => ic_dest_ip,
- DEST_UDP_OUT => ic_dest_udp,
- SRC_MAC_OUT => ic_src_mac,
- SRC_IP_OUT => ic_src_ip,
- SRC_UDP_OUT => ic_src_udp,
- MTU_OUT => open,
- -- Debug
- DEBUG_OUT => open
-);
-
-MB_IP_CONFIG: slv_mac_memory
-port map(
- CLK => CLK,
- RESET => RESET,
- BUSY_IN => '0',
- -- Slave bus
- SLV_ADDR_IN => SLV_ADDR_IN,
- SLV_READ_IN => SLV_READ_IN,
- SLV_WRITE_IN => SLV_WRITE_IN,
- SLV_BUSY_OUT => SLV_BUSY_OUT,
- SLV_ACK_OUT => SLV_ACK_OUT,
- SLV_DATA_IN => SLV_DATA_IN,
- SLV_DATA_OUT => SLV_DATA_OUT,
- -- I/O to the backend
- MEM_CLK_IN => ip_cfg_mem_clk,
- MEM_ADDR_IN => ip_cfg_mem_addr,
- MEM_DATA_OUT => ip_cfg_mem_data,
- -- Status lines
- STAT => open
-);
-
-THE_IPU_INTERFACE: trb_net16_gbe_ipu_interface --ipu2gbe
-port map(
- CLK_IPU => CLK,
- CLK_GBE => CLK,
- RESET => RESET,
- --Event information coming from CTS
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- --Information sent to CTS
- --status data, equipped with DHDR
- CTS_DATA_OUT => CTS_DATA_OUT,
- CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_READ_IN => CTS_READ_IN,
- CTS_LENGTH_OUT => CTS_LENGTH_OUT,
- CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- FEE_BUSY_IN => FEE_BUSY_IN,
- -- slow control interface
- START_CONFIG_OUT => ip_cfg_start,
- BANK_SELECT_OUT => ip_cfg_bank,
- CONFIG_DONE_IN => ip_cfg_done,
- DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN,
- DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN,
- MULT_EVT_ENABLE_IN => '0', --CFG_MULT_ENABLE_IN,
- MAX_MESSAGE_SIZE_IN => x"0000_0fd0",
- MIN_MESSAGE_SIZE_IN => x"0000_0007",
- READOUT_CTR_IN => x"00_0000",
- READOUT_CTR_VALID_IN => '0',
- ALLOW_LARGE_IN => '0',
- -- PacketConstructor interface
- PC_WR_EN_OUT => pc_wr_en,
- PC_DATA_OUT => pc_data,
- PC_READY_IN => pc_ready,
- PC_SOS_OUT => pc_sos,
- PC_EOS_OUT => pc_eos,
- PC_EOD_OUT => pc_eod,
- PC_SUB_SIZE_OUT => pc_sub_size,
- PC_TRIG_NR_OUT => pc_trig_nr,
- PC_TRIGGER_TYPE_OUT => pc_trig_type,
- PC_PADDING_OUT => pc_padding,
- MONITOR_OUT => open,
- DEBUG_OUT => open
-);
-
---TODO: add missing values from setup
-PACKET_CONSTRUCTOR : trb_net16_gbe_event_constr --trb_net16_gbe_packet_constr
-port map(
- CLK => CLK,
- RESET => RESET,
- MULT_EVT_ENABLE_IN => '0',
- PC_WR_EN_IN => pc_wr_en,
- PC_DATA_IN => pc_data,
- PC_READY_OUT => pc_ready,
- PC_START_OF_SUB_IN => pc_sos,
- PC_END_OF_SUB_IN => pc_eos,
- PC_END_OF_DATA_IN => pc_eod,
- PC_TRANSMIT_ON_OUT => pc_transmit_on,
- PC_SUB_SIZE_IN => pc_sub_size,
- PC_PADDING_IN => pc_padding,
- PC_DECODING_IN => x"0002_0001", --pc_decoding,
- PC_EVENT_ID_IN => x"0000_8000", --pc_event_id,
- PC_TRIG_NR_IN => pc_trig_nr,
- PC_TRIGGER_TYPE_IN => pc_trig_type,
- PC_QUEUE_DEC_IN => x"0003_0062", --pc_queue_dec,
- PC_MAX_FRAME_SIZE_IN => g_MAX_FRAME_SIZE,
- PC_MAX_QUEUE_SIZE_IN => x"0000_0fd0",
- PC_DELAY_IN => (others => '0'),
- TC_RD_EN_IN => tc_rd_en,
- TC_DATA_OUT => tc_data,
- TC_EVENT_SIZE_OUT => tc_size,
- TC_SOD_OUT => tc_sod,
- DEBUG_OUT => open
-);
-
-tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0';
-
-DISSECT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- dissect_current_state <= IDLE;
- else
- dissect_current_state <= dissect_next_state;
- end if;
- end if;
-end process DISSECT_MACHINE_PROC;
-
-DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN)
-begin
- case dissect_current_state is
-
- when IDLE =>
- if (tc_sod = '1') then
- dissect_next_state <= WAIT_FOR_LOAD;
- else
- dissect_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_LOAD =>
- if (PS_SELECTED_IN = '1') then
- dissect_next_state <= LOAD;
- else
- dissect_next_state <= WAIT_FOR_LOAD;
- end if;
-
- when LOAD =>
- if (event_bytes = loaded_bytes) then
- dissect_next_state <= CLEANUP;
- else
- dissect_next_state <= LOAD;
- end if;
-
- when CLEANUP =>
- dissect_next_state <= IDLE;
-
- end case;
-end process DISSECT_MACHINE;
-
-PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
-PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0';
-
-TC_DATA_OUT <= tc_data;
---TC_DATA_EOD_PROC : process (clk) is
---begin
--- if rising_edge(clk) then
--- if (dissect_current_state = LOAD and event_bytes = loaded_bytes - x"2") then
--- TC_DATA_OUT(8) <= '1';
--- else
--- TC_DATA_OUT(8) <= '0';
--- end if;
--- end if;
---end process TC_DATA_EOD_PROC;
-
-EVENT_BYTES_PROC : process (clk) is
-begin
- if rising_edge(clk) then
- if dissect_current_state = IDLE and tc_sod = '1' then
- event_bytes <= tc_size + x"20"; -- adding termination bytes
- else
- event_bytes <= event_bytes;
- end if;
- end if;
-end process EVENT_BYTES_PROC;
-
-LOADED_BYTES_PROC : process (clk) is
-begin
- if rising_edge(clk) then
- if (dissect_current_state = IDLE) then
- loaded_bytes <= (others => '0');
- elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then
- loaded_bytes <= loaded_bytes + x"1";
- else
- loaded_bytes <= loaded_bytes;
- end if;
- end if;
-end process LOADED_BYTES_PROC;
-
-TC_FRAME_SIZE_OUT <= event_bytes;
-TC_FRAME_TYPE_OUT <= x"0008";
-TC_DEST_MAC_OUT <= ic_dest_mac;
-TC_DEST_IP_OUT <= ic_dest_ip;
-TC_DEST_UDP_OUT <= ic_dest_udp;
-TC_SRC_MAC_OUT <= g_MY_MAC;
-TC_SRC_IP_OUT <= g_MY_IP;
-TC_SRC_UDP_OUT <= ic_src_udp;
-TC_IP_PROTOCOL_OUT <= x"11";
-TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0);
-
-SENT_PACKETS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- sent_packets <= (others => '0');
- elsif (dissect_current_state = IDLE and tc_sod = '1') then
- sent_packets <= sent_packets + x"1";
- end if;
- end if;
-end process SENT_PACKETS_PROC;
-
-
-end trb_net16_gbe_response_constructor_TrbNetData;
-
-
DBG_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
DBG_SELECT_PROTOS_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- SCTRL_DUMMY_SIZE_OUT : out std_logic_vector(15 downto 0);
- SCTRL_DUMMY_PAUSE_OUT : out std_logic_vector(31 downto 0);
-
DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0)
--DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10
);
signal vlan_id : std_logic_vector(31 downto 0);
signal allow_brdcst_eth : std_logic;
signal allow_brdcst_ip : std_logic;
-signal dummy_size : std_logic_vector(15 downto 0);
-signal dummy_pause : std_logic_vector(31 downto 0);
begin
GBE_ALLOWED_IP_OUT <= allowed_ip;
GBE_ALLOWED_UDP_OUT <= allowed_udp;
GBE_VLAN_ID_OUT <= vlan_id;
- SCTRL_DUMMY_SIZE_OUT <= dummy_size;
- SCTRL_DUMMY_PAUSE_OUT <= dummy_pause;
end if;
end process OUT_PROC;
vlan_id <= x"0000_0000"; -- no vlan id by default
allow_brdcst_eth <= '1';
allow_brdcst_ip <= '1';
- dummy_size <= x"0100";
- dummy_pause <= x"0040_0000";
elsif (BUS_WRITE_EN_IN = '1') then
case BUS_ADDR_IN is
when x"04" =>
max_frame <= BUS_DATA_IN(15 downto 0);
- g_MAX_FRAME_SIZE <= BUS_DATA_IN(15 downto 0);
when x"05" =>
if (BUS_DATA_IN = x"0000_0000") then
when x"12" =>
allowed_udp <= BUS_DATA_IN;
-
- when x"13" =>
- dummy_size <= BUS_DATA_IN(15 downto 0);
-
- when x"14" =>
- dummy_pause <= BUS_DATA_IN;
-- gk 28.09.10
when x"fe" =>
allowed_udp <= allowed_udp;
allow_brdcst_eth <= allow_brdcst_eth;
allow_brdcst_ip <= allow_brdcst_ip;
- dummy_size <= dummy_size;
- dummy_pause <= dummy_pause;
end case;
else
when x"12" =>
data_out <= allowed_udp;
-
- when x"13" =>
- data_out(15 downto 0) <= dummy_size;
+
+ -- gk 01.06.10
+ when x"e0" =>
+ data_out <= DBG_IPU2GBE1_IN;
+
+ when x"e1" =>
+ data_out <= DBG_IPU2GBE2_IN;
+
+ when x"e2" =>
+ data_out <= DBG_PC1_IN;
+
+ when x"e3" =>
+ data_out <= DBG_PC2_IN;
+
+ when x"e4" =>
+ data_out <= DBG_FC1_IN;
+
+ when x"e5" =>
+ data_out <= DBG_FC2_IN;
+
+ when x"e6" =>
+ data_out <= DBG_FT1_IN;
+
+ when x"e7" =>
+ data_out <= DBG_FT2_IN;
+
+ when x"e8" =>
+ data_out(15 downto 0) <= DBG_FIFO_Q_IN;
data_out(31 downto 16) <= (others => '0');
+
+ when x"e9" =>
+ data_out <= DBG_IPU2GBE3_IN;
+
+ when x"ea" =>
+ data_out <= DBG_IPU2GBE4_IN;
+
+ when x"eb" =>
+ data_out <= DBG_IPU2GBE5_IN;
+
+ when x"ec" =>
+ data_out <= DBG_IPU2GBE6_IN;
+
+ when x"ed" =>
+ data_out <= DBG_IPU2GBE7_IN;
+
+ when x"ee" =>
+ data_out <= DBG_IPU2GBE8_IN;
+
+ when x"ef" =>
+ data_out <= DBG_IPU2GBE9_IN;
+
+ when x"f0" =>
+ data_out <= DBG_IPU2GBE10_IN;
+
+ when x"f1" =>
+ data_out <= DBG_IPU2GBE11_IN;
+
+ when x"f2" =>
+ data_out <= DBG_IPU2GBE12_IN;
+
+ when x"f3" =>
+ data_out <= MONITOR_BYTES_IN;
+
+ when x"f4" =>
+ data_out <= MONITOR_SENT_IN;
+
+ when x"f5" =>
+ data_out <= MONITOR_DROPPED_IN;
+
+ when x"f6" =>
+ data_out <= MONITOR_SM_IN;
+
+ when x"f7" =>
+ data_out <= MONITOR_LR_IN;
+
+ when x"f8" =>
+ data_out <= MONITOR_HDR_IN;
+
+ when x"f9" =>
+ data_out <= MONITOR_FIFOS_IN;
+
+ when x"fa" =>
+ data_out <= MONITOR_DISCFRM_IN;
+
+ when x"fb" =>
+ data_out <= MONITOR_LINK_DWN_IN;
+
+ when x"fc" =>
+ data_out <= MONITOR_EMPTY_IN;
+
+ --when x"d1" =>
+ -- data_out <= DBG_FR_IN;
+
+ --when x"d2" =>
+ -- data_out <= DBG_RC_IN;
+
+ --when x"d4" =>
+ -- data_out <= DBG_TC_IN;
+
+ -- **** receive debug section
+
+ when x"a0" =>
+ data_out <= DBG_FR_IN(31 downto 0); -- received frames from tsmac | state machine | fifos status
+
+ when x"a1" =>
+ data_out <= DBG_FR_IN(63 downto 32); -- dropped | accepted frames
+
+ when x"a2" =>
+ data_out <= MONITOR_RX_FRAMES_IN;
+
+ when x"a3" =>
+ data_out <= MONITOR_RX_BYTES_IN;
+
+ when x"a4" =>
+ data_out <= MONITOR_RX_BYTES_R_IN;
+
+ when x"a5" =>
+ data_out <= DBG_MC_IN(31 downto 0);
+
+
+ -- *** debug of response constructors
+
+ -- Forward
+ when x"b0" =>
+ data_out(15 downto 0) <= DBG_SELECT_REC_IN(1 * 16 - 1 downto 0 * 16);
+ data_out(31 downto 16) <= DBG_SELECT_SENT_IN(1 * 16 - 1 downto 0 * 16);
+ when x"b1" =>
+ data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32);
+
+ -- ARP
+ when x"b2" =>
+ data_out(15 downto 0) <= DBG_SELECT_REC_IN(2 * 16 - 1 downto 1 * 16);
+ data_out(31 downto 16) <= DBG_SELECT_SENT_IN(2 * 16 - 1 downto 1 * 16);
+ when x"b3" =>
+ data_out <= DBG_SELECT_PROTOS_IN(2 * 32 - 1 downto 1 * 32);
+
+ -- Test
+ when x"b4" =>
+ data_out(15 downto 0) <= DBG_SELECT_REC_IN(3 * 16 - 1 downto 2 * 16);
+ data_out(31 downto 16) <= DBG_SELECT_SENT_IN(3 * 16 - 1 downto 2 * 16);
+ when x"b5" =>
+ data_out <= DBG_SELECT_PROTOS_IN(3 * 32 - 1 downto 2 * 32);
+
+ -- DHCP
+ when x"b6" =>
+ data_out(15 downto 0) <= DBG_SELECT_REC_IN(4 * 16 - 1 downto 3 * 16);
+ data_out(31 downto 16) <= DBG_SELECT_SENT_IN(4 * 16 - 1 downto 3 * 16);
+ when x"b7" =>
+ data_out <= DBG_SELECT_PROTOS_IN(4 * 32 - 1 downto 3 * 32);
- when x"14" =>
- data_out <= dummy_pause;
-
--- -- gk 01.06.10
--- when x"e0" =>
--- data_out <= DBG_IPU2GBE1_IN;
---
--- when x"e1" =>
--- data_out <= DBG_IPU2GBE2_IN;
---
--- when x"e2" =>
--- data_out <= DBG_PC1_IN;
---
--- when x"e3" =>
--- data_out <= DBG_PC2_IN;
---
--- when x"e4" =>
--- data_out <= DBG_FC1_IN;
---
--- when x"e5" =>
--- data_out <= DBG_FC2_IN;
---
--- when x"e6" =>
--- data_out <= DBG_FT1_IN;
---
--- when x"e7" =>
--- data_out <= DBG_FT2_IN;
---
--- when x"e8" =>
--- data_out(15 downto 0) <= DBG_FIFO_Q_IN;
--- data_out(31 downto 16) <= (others => '0');
---
--- when x"e9" =>
--- data_out <= DBG_IPU2GBE3_IN;
---
--- when x"ea" =>
--- data_out <= DBG_IPU2GBE4_IN;
---
--- when x"eb" =>
--- data_out <= DBG_IPU2GBE5_IN;
---
--- when x"ec" =>
--- data_out <= DBG_IPU2GBE6_IN;
---
--- when x"ed" =>
--- data_out <= DBG_IPU2GBE7_IN;
---
--- when x"ee" =>
--- data_out <= DBG_IPU2GBE8_IN;
---
--- when x"ef" =>
--- data_out <= DBG_IPU2GBE9_IN;
---
--- when x"f0" =>
--- data_out <= DBG_IPU2GBE10_IN;
---
--- when x"f1" =>
--- data_out <= DBG_IPU2GBE11_IN;
---
--- when x"f2" =>
--- data_out <= DBG_IPU2GBE12_IN;
---
--- when x"f3" =>
--- data_out <= MONITOR_BYTES_IN;
---
--- when x"f4" =>
--- data_out <= MONITOR_SENT_IN;
---
--- when x"f5" =>
--- data_out <= MONITOR_DROPPED_IN;
---
--- when x"f6" =>
--- data_out <= MONITOR_SM_IN;
---
--- when x"f7" =>
--- data_out <= MONITOR_LR_IN;
---
--- when x"f8" =>
--- data_out <= MONITOR_HDR_IN;
---
--- when x"f9" =>
--- data_out <= MONITOR_FIFOS_IN;
---
--- when x"fa" =>
--- data_out <= MONITOR_DISCFRM_IN;
---
--- when x"fb" =>
--- data_out <= MONITOR_LINK_DWN_IN;
---
--- when x"fc" =>
--- data_out <= MONITOR_EMPTY_IN;
---
--- --when x"d1" =>
--- -- data_out <= DBG_FR_IN;
---
--- --when x"d2" =>
--- -- data_out <= DBG_RC_IN;
---
--- --when x"d4" =>
--- -- data_out <= DBG_TC_IN;
---
--- -- **** receive debug section
---
--- when x"a0" =>
--- data_out <= DBG_FR_IN(31 downto 0); -- received frames from tsmac | state machine | fifos status
---
--- when x"a1" =>
--- data_out <= DBG_FR_IN(63 downto 32); -- dropped | accepted frames
---
--- when x"a2" =>
--- data_out <= MONITOR_RX_FRAMES_IN;
---
--- when x"a3" =>
--- data_out <= MONITOR_RX_BYTES_IN;
---
--- when x"a4" =>
--- data_out <= MONITOR_RX_BYTES_R_IN;
---
--- when x"a5" =>
--- data_out <= DBG_MC_IN(31 downto 0);
---
---
--- -- *** debug of response constructors
---
--- -- Forward
--- when x"b0" =>
--- data_out(15 downto 0) <= DBG_SELECT_REC_IN(1 * 16 - 1 downto 0 * 16);
--- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(1 * 16 - 1 downto 0 * 16);
--- when x"b1" =>
--- data_out <= DBG_SELECT_PROTOS_IN(1 * 32 - 1 downto 0 * 32);
---
--- -- ARP
--- when x"b2" =>
--- data_out(15 downto 0) <= DBG_SELECT_REC_IN(2 * 16 - 1 downto 1 * 16);
--- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(2 * 16 - 1 downto 1 * 16);
--- when x"b3" =>
--- data_out <= DBG_SELECT_PROTOS_IN(2 * 32 - 1 downto 1 * 32);
---
--- -- Test
--- when x"b4" =>
--- data_out(15 downto 0) <= DBG_SELECT_REC_IN(3 * 16 - 1 downto 2 * 16);
--- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(3 * 16 - 1 downto 2 * 16);
--- when x"b5" =>
--- data_out <= DBG_SELECT_PROTOS_IN(3 * 32 - 1 downto 2 * 32);
---
--- -- DHCP
--- when x"b6" =>
--- data_out(15 downto 0) <= DBG_SELECT_REC_IN(4 * 16 - 1 downto 3 * 16);
--- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(4 * 16 - 1 downto 3 * 16);
--- when x"b7" =>
--- data_out <= DBG_SELECT_PROTOS_IN(4 * 32 - 1 downto 3 * 32);
---
--- -- PING
--- when x"b8" =>
--- data_out(15 downto 0) <= DBG_SELECT_REC_IN(5 * 16 - 1 downto 4 * 16);
--- data_out(31 downto 16) <= DBG_SELECT_SENT_IN(5 * 16 - 1 downto 4 * 16);
--- when x"b9" =>
--- data_out <= DBG_SELECT_PROTOS_IN(5 * 32 - 1 downto 4 * 32);
+ -- PING
+ when x"b8" =>
+ data_out(15 downto 0) <= DBG_SELECT_REC_IN(5 * 16 - 1 downto 4 * 16);
+ data_out(31 downto 16) <= DBG_SELECT_SENT_IN(5 * 16 - 1 downto 4 * 16);
+ when x"b9" =>
+ data_out <= DBG_SELECT_PROTOS_IN(5 * 32 - 1 downto 4 * 32);
-- Trash
--when x"b8" =>
use work.trb_net_gbe_protocols.all;
--********
--- doing shit right now
+-- multiplexes the output stream between data and slow control frames
+-- creates slow control frames
entity trb_net16_gbe_transmit_control is
port (
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+-- signals to/from packet constructor
+ PC_READY_IN : in std_logic;
+ PC_DATA_IN : in std_logic_vector(7 downto 0);
+ PC_WR_EN_IN : in std_logic;
+ PC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
+ PC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
+ PC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
+ PC_SOD_IN : in std_logic;
+ PC_EOD_IN : in std_logic;
+ PC_FC_READY_OUT : out std_logic;
+ PC_FC_H_READY_OUT : out std_logic;
+ PC_TRANSMIT_ON_IN : in std_logic;
+
+ -- signals from ip_configurator used by packet constructor
+ IC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ IC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ IC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ IC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ IC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ IC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-- signal to/from main controller
- MC_TRANSMIT_CTRL_IN : in std_logic;
- MC_DATA_IN : in std_logic_vector(8 downto 0);
- MC_WR_EN_IN : in std_logic;
- MC_DATA_NOT_VALID_IN : in std_logic;
- MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
-
- MC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- MC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- MC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- MC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- MC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- MC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
+ MC_TRANSMIT_CTRL_IN : in std_logic; -- slow control frame is waiting to be built and sent
+ MC_TRANSMIT_DATA_IN : in std_logic;
+ MC_DATA_IN : in std_logic_vector(8 downto 0);
+ MC_RD_EN_OUT : out std_logic;
+ MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
+ MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- MC_IDENT_IN : in std_logic_vector(15 downto 0);
+ MC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
+ MC_DEST_IP_IN : in std_logic_vector(31 downto 0);
+ MC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
+ MC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
+ MC_SRC_IP_IN : in std_logic_vector(31 downto 0);
+ MC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
- MC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
- MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
+ MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- MC_FC_H_READY_OUT : out std_logic;
- MC_FC_READY_OUT : out std_logic;
- MC_FC_WR_EN_IN : in std_logic;
+ MC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
+ MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
+ MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
- MC_BUSY_OUT : out std_logic;
- MC_TRANSMIT_DONE_OUT : out std_logic;
+ MC_BUSY_OUT : out std_logic;
+ MC_TRANSMIT_DONE_OUT : out std_logic;
-- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+ FC_DATA_OUT : out std_logic_vector(7 downto 0);
+ FC_WR_EN_OUT : out std_logic;
+ FC_READY_IN : in std_logic;
+ FC_H_READY_IN : in std_logic;
+ FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
+ FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ FC_SOD_OUT : out std_logic;
+ FC_EOD_OUT : out std_logic;
+ FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+
+ DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+ SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+
-- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end trb_net16_gbe_transmit_control;
architecture trb_net16_gbe_transmit_control of trb_net16_gbe_transmit_control is
+--attribute HGROUP : string;
+--attribute HGROUP of trb_net16_gbe_transmit_control : architecture is "GBE_BUF_group";
+
+attribute syn_encoding : string;
+
+type tx_states is (IDLE, TRANSMIT_DATA, TRANSMIT_CTRL, CLEANUP);
+signal tx_current_state, tx_next_state : tx_states;
+attribute syn_encoding of tx_current_state: signal is "safe,gray";
+
+type ctrl_construct_states is (IDLE, WAIT_FOR_FC, LOAD_DATA, CLOSE, CLEANUP);
+signal ctrl_construct_current_state, ctrl_construct_next_state : ctrl_construct_states;
+attribute syn_encoding of ctrl_construct_current_state: signal is "safe,gray";
+
+signal ctrl_sod : std_logic;
+signal delayed_wr_en : std_logic;
+signal delayed_wr_en_q : std_logic;
+signal sent_bytes_ctr : std_logic_vector(15 downto 0);
+signal sent_packets_ctr : std_logic_vector(15 downto 0);
+
+signal state : std_logic_vector(3 downto 0);
+signal state2 : std_logic_vector(3 downto 0);
+signal temp_frame_size : std_logic_vector(15 downto 0);
+signal temp_ip_size : std_logic_vector(15 downto 0);
+
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_keep of temp_frame_size, temp_ip_size : signal is true;
+attribute syn_preserve of temp_frame_size, temp_ip_size : signal is true;
+
+
+begin
+
+temp_frame_size <= MC_FRAME_SIZE_IN;
+temp_ip_size <= MC_IP_SIZE_IN;
+
+DEBUG_OUT(3 downto 0) <= state;
+DEBUG_OUT(7 downto 4) <= state2;
+DEBUG_OUT(31 downto 8) <= (others => '0');
+
+MC_BUSY_OUT <= '0' when (tx_current_state = IDLE)
+ else '1';
+
+MC_TRANSMIT_DONE_OUT <= '1' when (tx_current_state = CLEANUP) else '0';
+
+TX_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ tx_current_state <= IDLE;
+ else
+ tx_current_state <= tx_next_state;
+ end if;
+ end if;
+end process TX_MACHINE_PROC;
+
+TX_MACHINE : process(tx_current_state, MC_TRANSMIT_CTRL_IN, MC_TRANSMIT_DATA_IN, FC_READY_IN, PC_EOD_IN, ctrl_construct_current_state)
begin
+ case tx_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if (FC_READY_IN = '1') then
+-- if (MC_TRANSMIT_DATA_IN = '1') then
+-- tx_next_state <= TRANSMIT_DATA;
+-- elsif (MC_TRANSMIT_CTRL_IN = '1') then
+-- tx_next_state <= TRANSMIT_CTRL;
+ if (MC_TRANSMIT_CTRL_IN = '1') then
+ tx_next_state <= TRANSMIT_CTRL;
+ elsif (MC_TRANSMIT_DATA_IN = '1') then
+ tx_next_state <= TRANSMIT_DATA;
+ else
+ tx_next_state <= IDLE;
+ end if;
+ else
+ tx_next_state <= IDLE;
+ end if;
+
+ when TRANSMIT_DATA =>
+ state <= x"2";
+ if (PC_EOD_IN = '1') then
+ tx_next_state <= CLEANUP;
+ else
+ tx_next_state <= TRANSMIT_DATA;
+ end if;
+
+ when TRANSMIT_CTRL =>
+ state <= x"3";
+ if (ctrl_construct_current_state = CLOSE) then
+ tx_next_state <= CLEANUP;
+ else
+ tx_next_state <= TRANSMIT_CTRL;
+ end if;
+
+ when CLEANUP =>
+ state <= x"4";
+ tx_next_state <= IDLE;
+
+ end case;
+end process TX_MACHINE;
-SYNC_PROC : process(CLK)
+-- in case of data from packet constructor use always IP
+FC_FRAME_TYPE_OUT <= MC_FRAME_TYPE_IN when tx_current_state = TRANSMIT_CTRL else x"0008";
+
+SELECTOR : process(CLK)
begin
if rising_edge(CLK) then
-
- MC_FC_H_READY_OUT <= FC_H_READY_IN;
- MC_FC_READY_OUT <= FC_READY_IN;
- FC_FRAME_TYPE_OUT <= MC_FRAME_TYPE_IN;
+ case tx_current_state is
+
+ when TRANSMIT_DATA =>
+ -- CHANGED FOR SIMPLE FRAME SENDER
+ FC_DATA_OUT <= PC_DATA_IN;
+ FC_SOD_OUT <= PC_SOD_IN;
+ FC_EOD_OUT <= PC_EOD_IN;
+ FC_IP_SIZE_OUT <= PC_IP_SIZE_IN;
+ FC_UDP_SIZE_OUT <= PC_UDP_SIZE_IN;
+ FC_FLAGS_OFFSET_OUT <= PC_FLAGS_OFFSET_IN;
+ FC_IDENT_OUT <= sent_packets_ctr;
+ DEST_MAC_ADDRESS_OUT <= IC_DEST_MAC_ADDRESS_IN;
+ DEST_IP_ADDRESS_OUT <= IC_DEST_IP_ADDRESS_IN;
+ DEST_UDP_PORT_OUT <= IC_DEST_UDP_PORT_IN;
+ SRC_MAC_ADDRESS_OUT <= IC_SRC_MAC_ADDRESS_IN;
+ SRC_IP_ADDRESS_OUT <= IC_SRC_IP_ADDRESS_IN;
+ SRC_UDP_PORT_OUT <= IC_SRC_UDP_PORT_IN;
+
+ FC_IP_PROTOCOL_OUT <= x"11";
+
+
+ when TRANSMIT_CTRL =>
FC_DATA_OUT <= MC_DATA_IN(7 downto 0);
FC_IP_PROTOCOL_OUT <= MC_IP_PROTOCOL_IN;
- if (MC_TRANSMIT_CTRL_IN = '1') then
+ if (ctrl_construct_current_state = WAIT_FOR_FC) and (FC_READY_IN = '1') then
FC_SOD_OUT <= '1';
else
FC_SOD_OUT <= '0';
end if;
- if (MC_DATA_IN(8) = '1') then
+ --if (ctrl_construct_current_state = CLOSE) then
+ if (ctrl_construct_current_state = LOAD_DATA and sent_bytes_ctr = MC_FRAME_SIZE_IN - x"1") then
FC_EOD_OUT <= '1';
else
FC_EOD_OUT <= '0';
end if;
- if (MC_FRAME_TYPE_IN = x"0008") then
+ if (MC_FRAME_TYPE_IN = x"0008") then -- in case of ip
FC_IP_SIZE_OUT <= MC_IP_SIZE_IN;
- FC_UDP_SIZE_OUT <= MC_UDP_SIZE_IN;
+ --if (MC_UDP_SIZE_IN > g_MAX_FRAME_SIZE) then
+ -- FC_UDP_SIZE_OUT <= MC_UDP_SIZE_IN; -- - x"1";
+ --else
+ FC_UDP_SIZE_OUT <= MC_UDP_SIZE_IN;
+ --end if;
else
- FC_IP_SIZE_OUT <= MC_FRAME_SIZE_IN;
- FC_UDP_SIZE_OUT <= MC_FRAME_SIZE_IN;
+ FC_IP_SIZE_OUT <= temp_frame_size; --MC_FRAME_SIZE_IN;
+ FC_UDP_SIZE_OUT <= temp_frame_size; --MC_FRAME_SIZE_IN;
end if;
-
- if (MC_DATA_NOT_VALID_IN = '0' and MC_WR_EN_IN = '1') then
- FC_WR_EN_OUT <= '1';
- else
- FC_WR_EN_OUT <= '0';
- end if;
-
+-- FC_IP_SIZE_OUT <= temp_frame_size; --MC_FRAME_SIZE_IN;
+-- FC_UDP_SIZE_OUT <= temp_frame_size; --MC_FRAME_SIZE_IN;
FC_FLAGS_OFFSET_OUT <= MC_FLAGS_OFFSET_IN;
+ if (ctrl_construct_current_state = WAIT_FOR_FC) and (FC_H_READY_IN = '1') then
+ MC_RD_EN_OUT <= '1';
+ delayed_wr_en <= '0'; --'1';
+ elsif (ctrl_construct_current_state = LOAD_DATA) and (sent_bytes_ctr < MC_FRAME_SIZE_IN - x"2") then -- (sent_bytes_ctr /= MC_FRAME_SIZE_IN) then
+ MC_RD_EN_OUT <= '1';
+ delayed_wr_en <= '1';
+ else
+ MC_RD_EN_OUT <= '0';
+ delayed_wr_en <= '0';
+ end if;
+
DEST_MAC_ADDRESS_OUT <= MC_DEST_MAC_IN;
DEST_IP_ADDRESS_OUT <= MC_DEST_IP_IN;
DEST_UDP_PORT_OUT <= MC_DEST_UDP_IN;
SRC_IP_ADDRESS_OUT <= MC_SRC_IP_IN;
SRC_UDP_PORT_OUT <= MC_SRC_UDP_IN;
- FC_IDENT_OUT <= MC_IDENT_IN;
+ FC_IDENT_OUT <= sent_packets_ctr;
+
+ when others =>
+ MC_RD_EN_OUT <= '0';
+ FC_DATA_OUT <= (others => '0');
+ delayed_wr_en <= '0';
+ FC_SOD_OUT <= '0';
+ FC_EOD_OUT <= '0';
+
+ end case;
+
+ end if;
+end process SELECTOR;
+
+FC_WR_EN_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ delayed_wr_en_q <= delayed_wr_en;
+
+ case tx_current_state is
+ when TRANSMIT_DATA =>
+ FC_WR_EN_OUT <= PC_WR_EN_IN;
+ when TRANSMIT_CTRL =>
+ FC_WR_EN_OUT <= delayed_wr_en_q;
+ when others =>
+ FC_WR_EN_OUT <= '0';
+ end case;
+ end if;
+end process FC_WR_EN_PROC;
+
+
+CTRL_CONSTRUCT_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ ctrl_construct_current_state <= IDLE;
+ else
+ ctrl_construct_current_state <= ctrl_construct_next_state;
+ end if;
end if;
-end process SYNC_PROC;
+end process CTRL_CONSTRUCT_MACHINE_PROC;
+
+CTRL_CONSTRUCT_MACHINE : process(ctrl_construct_current_state, tx_current_state, FC_H_READY_IN, sent_bytes_ctr, MC_FRAME_SIZE_IN)
+begin
+
+ case ctrl_construct_current_state is
+
+ when IDLE =>
+ state2 <= x"1";
+ if (tx_current_state = TRANSMIT_CTRL) then
+ ctrl_construct_next_state <= WAIT_FOR_FC;
+ else
+ ctrl_construct_next_state <= IDLE;
+ end if;
+
+ when WAIT_FOR_FC =>
+ state2 <= x"2";
+ if (FC_H_READY_IN = '1') then
+ ctrl_construct_next_state <= LOAD_DATA;
+ else
+ ctrl_construct_next_state <= WAIT_FOR_FC;
+ end if;
+
+ when LOAD_DATA =>
+ state2 <= x"3";
+ if (sent_bytes_ctr = MC_FRAME_SIZE_IN - x"1") then
+ ctrl_construct_next_state <= CLOSE;
+ else
+ ctrl_construct_next_state <= LOAD_DATA;
+ end if;
+
+ when CLOSE =>
+ state2 <= x"4";
+ ctrl_construct_next_state <= CLEANUP;
+
+ when CLEANUP =>
+ state2 <= x"5";
+ ctrl_construct_next_state <= IDLE;
+
+ end case;
+
+end process CTRL_CONSTRUCT_MACHINE;
+
+SENT_BYTES_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (ctrl_construct_current_state = IDLE) then
+ sent_bytes_ctr <= (others => '0');
+ elsif (delayed_wr_en_q = '1') then
+ sent_bytes_ctr <= sent_bytes_ctr + x"1";
+ end if;
+ end if;
+end process SENT_BYTES_CTR_PROC;
+
+PC_FC_H_READY_OUT <= FC_H_READY_IN when ((tx_current_state = IDLE) or (tx_current_state = TRANSMIT_DATA))
+ else '0';
+
+PC_FC_READY_OUT <= FC_READY_IN when ((tx_current_state = IDLE) or (tx_current_state = TRANSMIT_DATA))
+ else '0';
+
+SENT_PACKETS_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ sent_packets_ctr <= (others => '0');
+ --elsif (tx_current_state = CLEANUP and MC_FLAGS_OFFSET_IN(13) = '0') then
+ elsif (tx_current_state = TRANSMIT_DATA and PC_EOD_IN = '1' and PC_FLAGS_OFFSET_IN(13) = '0') then
+ sent_packets_ctr <= sent_packets_ctr + x"1";
+ elsif (tx_current_state = TRANSMIT_CTRL and ctrl_construct_current_state = CLOSE and MC_FLAGS_OFFSET_IN(13) = '0') then
+ sent_packets_ctr <= sent_packets_ctr + x"1";
+ end if;
+ end if;
+end process SENT_PACKETS_CTR_PROC;
+
+
end trb_net16_gbe_transmit_control;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
-use work.trb_net_gbe_protocols.all;
-
---********
--- performs response constructors readout and splitting into frames
-
-entity trb_net16_gbe_transmit_control2 is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
--- signal to/from main controller
- TC_DATAREADY_IN : in std_logic;
- TC_RD_EN_OUT : out std_logic;
- TC_DATA_IN : in std_logic_vector(7 downto 0);
- TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- TC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- TC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- TC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- TC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- TC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- TC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
- TC_TRANSMISSION_DONE_OUT : out std_logic;
- TC_IDENT_IN : in std_logic_vector(15 downto 0);
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end trb_net16_gbe_transmit_control2;
-
-
-architecture trb_net16_gbe_transmit_control2 of trb_net16_gbe_transmit_control2 is
-
-attribute syn_encoding : string;
-
-type transmit_states is (IDLE, PREPARE_HEADERS, WAIT_FOR_H, TRANSMIT, SEND_ONE, SEND_TWO, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP);
-signal transmit_current_state, transmit_next_state : transmit_states;
-attribute syn_encoding of transmit_current_state : signal is "onehot";
-
-signal tc_rd, tc_rd_q, tc_rd_qq : std_logic;
-signal local_end : std_logic_vector(15 downto 0);
-
-signal actual_frame_bytes, full_packet_size, ip_size, packet_loaded_bytes : std_logic_vector(15 downto 0);
-signal go_to_divide, more_fragments : std_logic;
-signal first_frame : std_logic;
-
-begin
-
-TRANSMIT_MACHINE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- transmit_current_state <= IDLE;
- else
- transmit_current_state <= transmit_next_state;
- end if;
- end if;
-end process TRANSMIT_MACHINE_PROC;
-
-TRANSMIT_MACHINE : process(transmit_current_state, FC_H_READY_IN, TC_DATAREADY_IN, FC_READY_IN, local_end, g_MAX_FRAME_SIZE, actual_frame_bytes, go_to_divide)
-begin
- case transmit_current_state is
-
- when IDLE =>
- if (TC_DATAREADY_IN = '1') then
- transmit_next_state <= PREPARE_HEADERS; --WAIT_FOR_H;
- else
- transmit_next_state <= IDLE;
- end if;
-
- when PREPARE_HEADERS =>
- transmit_next_state<= WAIT_FOR_H;
-
- when WAIT_FOR_H =>
- if (FC_H_READY_IN = '1') then
- transmit_next_state <= TRANSMIT;
- else
- transmit_next_state <= WAIT_FOR_H;
- end if;
-
- when TRANSMIT =>
- if (local_end = x"0000") then
- transmit_next_state <= SEND_ONE;
- else
- if (actual_frame_bytes = g_MAX_FRAME_SIZE - x"1") then
- transmit_next_state <= SEND_ONE;
- else
- transmit_next_state <= TRANSMIT;
- end if;
- end if;
-
- when SEND_ONE =>
- transmit_next_state <= SEND_TWO;
-
- when SEND_TWO =>
- transmit_next_state <= CLOSE;
-
- when CLOSE =>
- transmit_next_state <= WAIT_FOR_TRANS;
-
- when WAIT_FOR_TRANS =>
- if (FC_READY_IN = '1') then
- if (go_to_divide = '1') then
- transmit_next_state <= DIVIDE;
- else
- transmit_next_state <= CLEANUP;
- end if;
- else
- transmit_next_state <= WAIT_FOR_TRANS;
- end if;
-
- when DIVIDE =>
- transmit_next_state <= PREPARE_HEADERS; --WAIT_FOR_H;
-
- when CLEANUP =>
- transmit_next_state <= IDLE;
-
- end case;
-end process TRANSMIT_MACHINE;
-
-tc_rd <= '1' when transmit_current_state = TRANSMIT else '0';
-TC_RD_EN_OUT <= tc_rd;
-
-SYNC_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- tc_rd_q <= tc_rd;
- tc_rd_qq <= tc_rd_q;
- FC_WR_EN_OUT <= tc_rd_qq;
- end if;
-end process SYNC_PROC;
-
-ACTUAL_FRAME_BYTES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then
- actual_frame_bytes <= (others => '0');
- elsif (transmit_current_state = TRANSMIT) then
- actual_frame_bytes <= actual_frame_bytes + x"1";
- else
- actual_frame_bytes <= actual_frame_bytes;
- end if;
- end if;
-end process ACTUAL_FRAME_BYTES_PROC;
-
-GO_TO_DIVIDE_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE or transmit_current_state = DIVIDE) then
- go_to_divide <= '0';
- elsif (transmit_current_state = TRANSMIT and actual_frame_bytes = g_MAX_FRAME_SIZE - x"1") then
- go_to_divide <= '1';
--- elsif (transmit_current_state = SEND_ONE and full_packet_size < packet_loaded_bytes - x"1") then
--- go_to_divide <= '1';
--- elsif (transmit_current_state = SEND_TWO and full_packet_size < packet_loaded_bytes - x"1") then
--- go_to_divide <= '1';
- elsif (transmit_current_state = SEND_ONE and full_packet_size = packet_loaded_bytes) then
- go_to_divide <= '0';
- else
- go_to_divide <= go_to_divide;
- end if;
- end if;
-end process GO_TO_DIVIDE_PROC;
-
-LOCAL_END_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE and TC_DATAREADY_IN = '1') then
- local_end <= TC_FRAME_SIZE_IN - x"1";
- full_packet_size <= TC_FRAME_SIZE_IN;
- elsif (transmit_current_state = TRANSMIT) then
- local_end <= local_end - x"1";
- full_packet_size <= full_packet_size;
- else
- local_end <= local_end;
- full_packet_size <= full_packet_size;
- end if;
- end if;
-end process LOCAL_END_PROC;
-
-FC_DATA_OUT <= TC_DATA_IN;
-FC_SOD_OUT <= '1' when transmit_current_state = WAIT_FOR_H else '0';
-FC_EOD_OUT <= '1' when transmit_current_state = CLOSE else '0';
-
-process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = PREPARE_HEADERS) then
- if (local_end >= g_MAX_FRAME_SIZE) then
- ip_size <= g_MAX_FRAME_SIZE;
- else
- ip_size <= local_end + x"1";
- end if;
- else
- ip_size <= ip_size;
- end if;
- end if;
-end process;
-FC_IP_SIZE_OUT <= ip_size;
-FC_UDP_SIZE_OUT <= full_packet_size; --TC_FRAME_SIZE_IN;
-
-FC_FLAGS_OFFSET_OUT(15 downto 14) <= "00";
-FC_FLAGS_OFFSET_OUT(13) <= more_fragments;
-MORE_FRAGMENTS_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = PREPARE_HEADERS) then
- if (local_end >= g_MAX_FRAME_SIZE) then
- more_fragments <= '1';
- else
- more_fragments <= '0';
- end if;
- else
- more_fragments <= more_fragments;
- end if;
- end if;
-end process MORE_FRAGMENTS_PROC;
-FC_FLAGS_OFFSET_OUT(12 downto 0) <= ('0' & x"000") when first_frame = '1' else (packet_loaded_bytes(15 downto 3) + x"1");
-
-PACKET_LOADED_BYTES_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE) then
- packet_loaded_bytes <= x"0000";
- elsif (transmit_current_state = TRANSMIT) then
- packet_loaded_bytes <= packet_loaded_bytes + x"1";
--- elsif (transmit_current_state = DIVIDE and first_frame = '1') then
--- packet_loaded_bytes <= packet_loaded_bytes + x"8"; -- 8bytes for udp headers added for the first offset
- else
- packet_loaded_bytes <= packet_loaded_bytes;
- end if;
- end if;
-end process PACKET_LOADED_BYTES_PROC;
-
-FIRST_FRAME_PROC : process(CLK)
-begin
- if rising_edge(CLK) then
- if (transmit_current_state = IDLE) then
- first_frame <= '1';
- elsif (transmit_current_state = DIVIDE) then
- first_frame <= '0';
- else
- first_frame <= first_frame;
- end if;
- end if;
-end process FIRST_FRAME_PROC;
-
-
-TC_TRANSMISSION_DONE_OUT <= '1' when transmit_current_state = CLEANUP else '0';
-
-FC_FRAME_TYPE_OUT <= TC_FRAME_TYPE_IN;
-FC_IP_PROTOCOL_OUT <= TC_IP_PROTOCOL_IN;
-DEST_MAC_ADDRESS_OUT <= TC_DEST_MAC_IN;
-DEST_IP_ADDRESS_OUT <= TC_DEST_IP_IN;
-DEST_UDP_PORT_OUT <= TC_DEST_UDP_IN;
-SRC_MAC_ADDRESS_OUT <= TC_SRC_MAC_IN;
-SRC_IP_ADDRESS_OUT <= TC_SRC_IP_IN;
-SRC_UDP_PORT_OUT <= TC_SRC_UDP_IN;
-FC_IDENT_OUT <= TC_IDENT_IN;
-
-end trb_net16_gbe_transmit_control2;
-
-
signal ip_result : std_logic_vector(c_MAX_IP_PROTOCOLS - 1 downto 0);
signal udp_result : std_logic_vector(c_MAX_UDP_PROTOCOLS - 1 downto 0);
signal partially_valid : std_logic; -- only protocols, vlan to be checked
-signal zeros : std_logic_vector(c_MAX_FRAME_TYPES - 1 downto 0);
begin
-- DO NOT TOUCH
IP_RESULTS_GEN : for i in 0 to c_MAX_IP_PROTOCOLS - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and ALLOWED_IP_PROTOCOLS_IN(i) = '1' then
- ip_result(i) <= '1';
- else
- ip_result(i) <= '0';
- end if;
- end if;
-end process;
--- ip_result(i) <= '1' when (
--- IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and
--- ALLOWED_IP_PROTOCOLS_IN(i) = '1'
--- ) else '0';
+ ip_result(i) <= '1' when (
+ IP_PROTOCOLS(i) = IP_PROTOCOLS_IN and
+ ALLOWED_IP_PROTOCOLS_IN(i) = '1'
+ ) else '0';
+
+
end generate IP_RESULTS_GEN;
UDP_RESULTS_GEN : for i in 0 to c_MAX_UDP_PROTOCOLS - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and ALLOWED_UDP_PROTOCOLS_IN(i) = '1' then
- udp_result(i) <= '1';
- else
- udp_result(i) <= '0';
- end if;
- end if;
-end process;
--- udp_result(i) <= '1' when (
--- UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and
--- ALLOWED_UDP_PROTOCOLS_IN(i) = '1'
--- ) else '0';
+
+ udp_result(i) <= '1' when (
+ UDP_PROTOCOLS(i) = UDP_PROTOCOL_IN and
+ ALLOWED_UDP_PROTOCOLS_IN(i) = '1'
+ ) else '0';
end generate UDP_RESULTS_GEN;
RESULT_GEN : for i in 0 to c_MAX_FRAME_TYPES - 1 generate
-process(CLK)
-begin
- if rising_edge(CLK) then
- if FRAME_TYPES(i) = FRAME_TYPE_IN and ALLOWED_TYPES_IN(i) = '1' then
- result(i) <= '1';
- else
- result(i) <= '0';
- end if;
- end if;
-end process;
--- result(i) <= '1' when (
--- FRAME_TYPES(i) = FRAME_TYPE_IN and
--- ALLOWED_TYPES_IN(i) = '1'
--- ) else '0';
+
+ result(i) <= '1' when (
+ FRAME_TYPES(i) = FRAME_TYPE_IN and
+ ALLOWED_TYPES_IN(i) = '1'
+ ) else '0';
end generate RESULT_GEN;
else -- do not accept other protocols than udp and icmp inside ip
partially_valid <= '0';
end if;
- elsif (result /= zeros) then-- other frame
- partially_valid <= '1'; --or_all(result);
- else
- partially_valid <= '0';
+ else -- other frame
+ partially_valid <= or_all(result);
end if;
end if;
end process PARTIALLY_VALID_PROC;
-VALID_OUT_PROC : process(CLK) --partially_valid, SAVED_VLAN_ID_IN, VLAN_ID_IN)
+VALID_OUT_PROC : process(partially_valid, SAVED_VLAN_ID_IN, VLAN_ID_IN)
begin
- if rising_edge(CLK) then
+ --if rising_edge(CLK) then
-- if (RESET = '1') then
-- VALID_OUT <= '0';
if (partially_valid = '1') then
else
VALID_OUT <= '0';
end if;
- end if;
+ --end if;
end process VALID_OUT_PROC;
--if rising_edge(CLK) then
-- gk 20.07.10
---INC_DATA_CTR_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_saved_ctr = '1') then
--- inc_data_ctr <= (others => '0');
--- elsif (sf_wr_en = '1') and (data_req = '1') then
--- inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
--- end if;
--- end if;
---end process INC_DATA_CTR_proc;
+INC_DATA_CTR_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (rst_saved_ctr = '1') then
+ inc_data_ctr <= (others => '0');
+ elsif (sf_wr_en = '1') and (data_req = '1') then
+ inc_data_ctr(31 downto 1) <= inc_data_ctr(31 downto 1) + x"1";
+ end if;
+ end if;
+end process INC_DATA_CTR_proc;
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
rem_phase_comb <= '1';
end if;
when WAIT_TO_REMOVE =>
- if (rem_ctr = x"a") then
+ state2 <= x"2";
+ if (rem_ctr = x"a") then
loadNextState <= DECIDE;
else
loadNextState <= WAIT_TO_REMOVE;
end if;
when DECIDE =>
- if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
+ state2 <= x"2";
+ if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then
loadNextState <= PAUSE_BEFORE_DROP1;
drop_large_comb <= '1';
elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10
loadNextState <= WAIT_PC;
end if;
when PAUSE_BEFORE_DROP1 =>
- loadNextState <= PAUSE_BEFORE_DROP2;
+ state2 <= x"2";
+ loadNextState <= PAUSE_BEFORE_DROP2;
pc_sos_comb <= '1';
when PAUSE_BEFORE_DROP2 =>
- loadNextState <= DROP;
+ state2 <= x"2";
+ loadNextState <= DROP;
drop_event_comb <= '1';
-- gk 23.07.10
when DROP =>
end if;
-- gk 25.07.10
when DROP_SUBSUB =>
- if (load_sub_done = '1') then
+ state2 <= x"e";
+ if (load_sub_done = '1') then
if( padding_needed = '0' ) then
loadNextState <= CALCC;
else
PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
-- gk 25.07.10
---INVALID_STATS_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- dropped_lr_events_ctr <= (others => '0');
--- dropped_sm_events_ctr <= (others => '0');
--- headers_invalid_ctr <= (others => '0');
--- dropped_ctr <= (others => '0');
--- invalid_hsize_ctr <= (others => '0');
--- found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
--- elsif (rst_regs = '1') then
--- invalid_hsize_lock <= '0';
--- elsif (drop_small = '1') then
--- dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_large = '1') then
--- dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (drop_headers = '1') then
--- headers_invalid_ctr <= headers_invalid_ctr + x"1";
--- dropped_ctr <= dropped_ctr + x"1";
--- elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
--- invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
--- invalid_hsize_lock <= '1';
--- -- gk 01.10.10
--- elsif (found_empty_evt = '1') then
--- found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
--- end if;
--- end if;
---end process INVALID_STATS_PROC;
+INVALID_STATS_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ dropped_lr_events_ctr <= (others => '0');
+ dropped_sm_events_ctr <= (others => '0');
+ headers_invalid_ctr <= (others => '0');
+ dropped_ctr <= (others => '0');
+ invalid_hsize_ctr <= (others => '0');
+ found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10
+ elsif (rst_regs = '1') then
+ invalid_hsize_lock <= '0';
+ elsif (drop_small = '1') then
+ dropped_sm_events_ctr <= dropped_sm_events_ctr + x"1";
+ dropped_ctr <= dropped_ctr + x"1";
+ elsif (drop_large = '1') then
+ dropped_lr_events_ctr <= dropped_lr_events_ctr + x"1";
+ dropped_ctr <= dropped_ctr + x"1";
+ elsif (drop_headers = '1') then
+ headers_invalid_ctr <= headers_invalid_ctr + x"1";
+ dropped_ctr <= dropped_ctr + x"1";
+ elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
+ invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
+ invalid_hsize_lock <= '1';
+ -- gk 01.10.10
+ elsif (found_empty_evt = '1') then
+ found_empty_evt_ctr <= found_empty_evt_ctr + x"1";
+ end if;
+ end if;
+end process INVALID_STATS_PROC;
-- gk 05.08.10
INVALID_H_PROC : process(CLK)
------------------------------------------------------------------------------------------
-- Debug signals
---debug(0) <= sf_full;
---debug(1) <= sf_empty;
---debug(2) <= sf_afull;
---debug(3) <= sf_aempty;
---
---debug(7 downto 4) <= state2;
---
---debug(11 downto 8) <= state;
---
---dbg_bs_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(15 downto 12) <= (others => '0');
--- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
--- debug(15 downto 12) <= bank_select;
--- end if;
--- end if;
---end process dbg_bs_proc;
---
---debug(16) <= config_done;
---debug(17) <= '0'; --remove_done;
---debug(18) <= read_done;
---debug(19) <= padding_needed;
---
---debug(20) <= load_sub_done;
---
---dbg_cts_inf_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(39 downto 32) <= (others => '0');
--- elsif ( save_addr = '1' ) then
--- debug(39 downto 32) <= CTS_INFORMATION_IN;
--- end if;
--- end if;
---end process dbg_cts_inf_proc;
---
---debug(47 downto 40) <= (others => '0');
---
---
---debug(63 downto 48) <= actual_message_size(15 downto 0);
---
---dbg_pc_sub_size_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(81 downto 64) <= (others => '0');
--- elsif (loadCurrentState = DECIDE) then
--- debug(81 downto 64) <= pc_sub_size;
--- end if;
--- end if;
---end process dbg_pc_sub_size_proc;
---
---dbg_empty_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') or (rst_regs = '1') then
--- debug(84 downto 82) <= (others => '0');
--- elsif (read_size = 2) then
--- debug(82) <= sf_empty;
--- elsif (read_size = 1) then
--- debug(83) <= sf_empty;
--- elsif (read_size = 0) then
--- debug(84) <= sf_empty;
--- end if;
--- end if;
---end process dbg_empty_proc;
---
---debug(95 downto 85) <= (others => '0');
---
---dbg_inc_ctr_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- debug(127 downto 96) <= (others => '1');
--- elsif (saveCurrentState = SCLOSE) then
--- debug(127 downto 96) <= inc_data_ctr;
--- end if;
--- end if;
---end process dbg_inc_ctr_proc;
---
---debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
---debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
---
---debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
---debug(191 downto 176) <= (others => '0');
---
---dbg_cts_q_proc : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- cts_len_q <= (others => '0');
--- cts_rnd_q <= (others => '0');
--- cts_trg_q <= (others => '0');
--- cts_addr_q <= (others => '0');
--- elsif (cts_len_saved = '1') then
--- cts_len_q <= cts_len(16 downto 1);
--- cts_addr_q <= cts_addr;
--- cts_rnd_q <= cts_rnd;
--- cts_trg_q <= cts_trg;
--- end if;
--- end if;
---end process dbg_cts_q_proc;
-
---debug(207 downto 192) <= cts_trg_q;
---debug(223 downto 208) <= cts_rnd_q;
---debug(239 downto 224) <= cts_addr_q;
---debug(255 downto 240) <= cts_len_q;
---debug(271 downto 256) <= first_run_trg;
---debug(287 downto 272) <= first_run_addr;
---
---debug(303 downto 288) <= saved_events_ctr;
---debug(319 downto 304) <= loaded_events_ctr;
---
---debug(335 downto 320) <= constr_events_ctr(15 downto 0);
---debug(351 downto 336) <= dropped_ctr(15 downto 0);
---
---debug(367 downto 352) <= invalid_hsize_ctr;
---debug(383 downto 368) <= (others => '0');
---
---MONITOR_OUT(31 downto 0) <= constr_events_ctr;
---MONITOR_OUT(63 downto 32) <= dropped_ctr;
---MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
---MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
---MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
---MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
---MONITOR_OUT(191 downto 164) <= (others => '0');
---MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
+debug(0) <= sf_full;
+debug(1) <= sf_empty;
+debug(2) <= sf_afull;
+debug(3) <= sf_aempty;
+
+debug(7 downto 4) <= state2;
+
+debug(11 downto 8) <= state;
+
+dbg_bs_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ debug(15 downto 12) <= (others => '0');
+ elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
+ debug(15 downto 12) <= bank_select;
+ end if;
+ end if;
+end process dbg_bs_proc;
+
+debug(16) <= config_done;
+debug(17) <= '0'; --remove_done;
+debug(18) <= read_done;
+debug(19) <= padding_needed;
+
+debug(20) <= load_sub_done;
+
+dbg_cts_inf_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ debug(39 downto 32) <= (others => '0');
+ elsif ( save_addr = '1' ) then
+ debug(39 downto 32) <= CTS_INFORMATION_IN;
+ end if;
+ end if;
+end process dbg_cts_inf_proc;
+
+debug(47 downto 40) <= (others => '0');
+
+
+debug(63 downto 48) <= actual_message_size(15 downto 0);
+
+dbg_pc_sub_size_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ debug(81 downto 64) <= (others => '0');
+ elsif (loadCurrentState = DECIDE) then
+ debug(81 downto 64) <= pc_sub_size;
+ end if;
+ end if;
+end process dbg_pc_sub_size_proc;
+
+dbg_empty_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (rst_regs = '1') then
+ debug(84 downto 82) <= (others => '0');
+ elsif (read_size = 2) then
+ debug(82) <= sf_empty;
+ elsif (read_size = 1) then
+ debug(83) <= sf_empty;
+ elsif (read_size = 0) then
+ debug(84) <= sf_empty;
+ end if;
+ end if;
+end process dbg_empty_proc;
+
+debug(95 downto 85) <= (others => '0');
+
+dbg_inc_ctr_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ debug(127 downto 96) <= (others => '1');
+ elsif (saveCurrentState = SCLOSE) then
+ debug(127 downto 96) <= inc_data_ctr;
+ end if;
+ end if;
+end process dbg_inc_ctr_proc;
+
+debug(143 downto 128) <= dropped_sm_events_ctr(15 downto 0);
+debug(159 downto 144) <= dropped_lr_events_ctr(15 downto 0);
+
+debug(175 downto 160) <= headers_invalid_ctr(15 downto 0);
+debug(191 downto 176) <= (others => '0');
+
+dbg_cts_q_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ cts_len_q <= (others => '0');
+ cts_rnd_q <= (others => '0');
+ cts_trg_q <= (others => '0');
+ cts_addr_q <= (others => '0');
+ elsif (cts_len_saved = '1') then
+ cts_len_q <= cts_len(16 downto 1);
+ cts_addr_q <= cts_addr;
+ cts_rnd_q <= cts_rnd;
+ cts_trg_q <= cts_trg;
+ end if;
+ end if;
+end process dbg_cts_q_proc;
+
+debug(207 downto 192) <= cts_trg_q;
+debug(223 downto 208) <= cts_rnd_q;
+debug(239 downto 224) <= cts_addr_q;
+debug(255 downto 240) <= cts_len_q;
+debug(271 downto 256) <= first_run_trg;
+debug(287 downto 272) <= first_run_addr;
+
+debug(303 downto 288) <= saved_events_ctr;
+debug(319 downto 304) <= loaded_events_ctr;
+
+debug(335 downto 320) <= constr_events_ctr(15 downto 0);
+debug(351 downto 336) <= dropped_ctr(15 downto 0);
+
+debug(367 downto 352) <= invalid_hsize_ctr;
+debug(383 downto 368) <= (others => '0');
+
+MONITOR_OUT(31 downto 0) <= constr_events_ctr;
+MONITOR_OUT(63 downto 32) <= dropped_ctr;
+MONITOR_OUT(95 downto 64) <= headers_invalid_ctr;
+MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr;
+MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
+MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
+MONITOR_OUT(191 downto 164) <= (others => '0');
+MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10
-- Outputs
FEE_READ_OUT <= fee_read;
PC_SUB_SIZE_OUT <= b"0000_0000_0000_00" & pc_sub_size;
PC_PADDING_OUT <= padding_needed;
---DEBUG_OUT <= debug;
+DEBUG_OUT <= debug;
end architecture;
\ No newline at end of file
-- );\r
-- end component;\r
\r
-component sgmii_gbe_pcs35 --sgmii_gbe_pcs36 -- sgmii_gbe_pcs35\r
+component sgmii_gbe_pcs35\r
port( rst_n : in std_logic;\r
signal_detect : in std_logic;\r
gbe_mode : in std_logic;\r
\r
\r
\r
- SGMII_GBE_PCS : sgmii_gbe_pcs35 --sgmii_gbe_pcs36 --sgmii_gbe_pcs35\r
+ SGMII_GBE_PCS : sgmii_gbe_pcs35\r
port map(\r
rst_n => GSR_N,\r
signal_detect => signal_detected,\r
package trb_net_gbe_components is
-component trb_net16_gbe_transmit_control2 is
-port (
- CLK : in std_logic;
- RESET : in std_logic;
-
--- signal to/from main controller
- TC_DATAREADY_IN : in std_logic;
- TC_RD_EN_OUT : out std_logic;
- TC_DATA_IN : in std_logic_vector(7 downto 0);
- TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- TC_DEST_MAC_IN : in std_logic_vector(47 downto 0);
- TC_DEST_IP_IN : in std_logic_vector(31 downto 0);
- TC_DEST_UDP_IN : in std_logic_vector(15 downto 0);
- TC_SRC_MAC_IN : in std_logic_vector(47 downto 0);
- TC_SRC_IP_IN : in std_logic_vector(31 downto 0);
- TC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
- TC_IDENT_IN : in std_logic_vector(15 downto 0);
- TC_TRANSMISSION_DONE_OUT : out std_logic;
-
--- signal to/from frame constructor
- FC_DATA_OUT : out std_logic_vector(7 downto 0);
- FC_WR_EN_OUT : out std_logic;
- FC_READY_IN : in std_logic;
- FC_H_READY_IN : in std_logic;
- FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter
- FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
- FC_SOD_OUT : out std_logic;
- FC_EOD_OUT : out std_logic;
- FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
-
- DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
-
--- debug
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_event_constr is
-port(
- RESET : in std_logic;
- CLK : in std_logic;
- MULT_EVT_ENABLE_IN : in std_logic; -- gk 06.10.10
- -- ports for user logic
- PC_WR_EN_IN : in std_logic; -- write into queueConstr from userLogic
- PC_DATA_IN : in std_logic_vector(7 downto 0);
- PC_READY_OUT : out std_logic;
- PC_START_OF_SUB_IN : in std_logic;
- PC_END_OF_SUB_IN : in std_logic; -- gk 07.10.10
- PC_END_OF_DATA_IN : in std_logic;
- PC_TRANSMIT_ON_OUT : out std_logic;
- -- queue and subevent layer headers
- PC_SUB_SIZE_IN : in std_logic_vector(31 downto 0); -- store and swap
- PC_PADDING_IN : in std_logic; -- gk 29.03.10
- PC_DECODING_IN : in std_logic_vector(31 downto 0); -- swap
- PC_EVENT_ID_IN : in std_logic_vector(31 downto 0); -- swap
- PC_TRIG_NR_IN : in std_logic_vector(31 downto 0); -- store and swap!
- PC_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
- PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap
- PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP
- PC_MAX_QUEUE_SIZE_IN : in std_logic_vector(31 downto 0);
- PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10
- -- FrameConstructor ports
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_EVENT_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SOD_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
-end component;
-
-component trb_net16_gbe_ipu_interface is
- port (
- CLK_IPU : in std_logic;
- CLK_GBE : in std_logic;
- RESET : in std_logic;
- -- IPU interface directed toward the CTS
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- -- slow control interface
- START_CONFIG_OUT : out std_logic; -- reconfigure MACs/IPs/ports/packet size
- BANK_SELECT_OUT : out std_logic_vector(3 downto 0); -- configuration page address
- CONFIG_DONE_IN : in std_logic; -- configuration finished
- DATA_GBE_ENABLE_IN : in std_logic; -- IPU data is forwarded to GbE
- DATA_IPU_ENABLE_IN : in std_logic; -- IPU data is forwarded to CTS / TRBnet
- MULT_EVT_ENABLE_IN : in std_logic;
- MAX_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue -- gk 08.04.10
- MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
- READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
- READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
- -- PacketConstructor interface
- ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
- PC_WR_EN_OUT : out std_logic;
- PC_DATA_OUT : out std_logic_vector (7 downto 0);
- PC_READY_IN : in std_logic;
- PC_SOS_OUT : out std_logic;
- PC_EOS_OUT : out std_logic; -- gk 07.10.10
- PC_EOD_OUT : out std_logic;
- PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
- PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
- PC_PADDING_OUT : out std_logic;
- PC_TRIGGER_TYPE_OUT : out std_logic_vector(3 downto 0);
- MONITOR_OUT : out std_logic_vector(223 downto 0);
- DEBUG_OUT : out std_logic_vector(383 downto 0)
- );
-end component;
component trb_net16_gbe_buf is
generic(
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- MC_BUSY_IN : in std_logic;
+
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
+ MC_BUSY_IN : in std_logic;
-- counters from response constructors
RECEIVED_FRAMES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
MAKE_RESET_OUT : out std_logic;
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-
-- input for statistics from outside
STAT_DATA_IN : in std_logic_vector(31 downto 0);
STAT_ADDR_IN : in std_logic_vector(7 downto 0);
MC_LINK_OK_OUT : out std_logic;
MC_RESET_LINK_IN : in std_logic;
- MC_IDLE_TOO_LONG_OUT : out std_logic;
-- signals to/from receive controller
RC_FRAME_WAITING_IN : in std_logic;
RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-- signals to/from transmit controller
- TC_TRANSMIT_CTRL_OUT : out std_logic;
+ TC_TRANSMIT_CTRL_OUT : out std_logic; -- slow control frame is waiting to be built and sent
+ TC_TRANSMIT_DATA_OUT : out std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_RD_EN_IN : in std_logic;
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
TC_TRANSMIT_DONE_IN : in std_logic;
+-- signals to/from packet constructor
+ PC_READY_IN : in std_logic;
+ PC_TRANSMIT_ON_IN : in std_logic;
+ PC_SOD_IN : in std_logic;
+
-- signals to/from sgmii/gbe pcs_an_complete
PCS_AN_COMPLETE_IN : in std_logic;
GSC_REPLY_READ_OUT : out std_logic;
GSC_BUSY_IN : in std_logic;
- -- signal for data readout
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-
MAKE_RESET_OUT : out std_logic;
-- signal to/from Host interface of TriSpeed MAC
CLK : in std_logic; -- system clock
RESET : in std_logic;
+-- signals to/from packet constructor
+ PC_READY_IN : in std_logic;
+ PC_DATA_IN : in std_logic_vector(7 downto 0);
+ PC_WR_EN_IN : in std_logic;
+ PC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
+ PC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
+ PC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
+ PC_SOD_IN : in std_logic;
+ PC_EOD_IN : in std_logic;
+ PC_FC_READY_OUT : out std_logic;
+ PC_FC_H_READY_OUT : out std_logic;
+ PC_TRANSMIT_ON_IN : in std_logic;
+
+ -- signals from ip_configurator used by packet constructor
+ IC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ IC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ IC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ IC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ IC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ IC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
-- signal to/from main controller
MC_TRANSMIT_CTRL_IN : in std_logic; -- slow control frame is waiting to be built and sent
+ MC_TRANSMIT_DATA_IN : in std_logic;
MC_DATA_IN : in std_logic_vector(8 downto 0);
- MC_DATA_NOT_VALID_IN : in std_logic;
- MC_WR_EN_IN : in std_logic;
+ MC_RD_EN_OUT : out std_logic;
MC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
MC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0);
MC_SRC_UDP_IN : in std_logic_vector(15 downto 0);
MC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
- MC_IDENT_IN : in std_logic_vector(15 downto 0);
MC_IP_SIZE_IN : in std_logic_vector(15 downto 0);
MC_UDP_SIZE_IN : in std_logic_vector(15 downto 0);
MC_FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
- MC_FC_H_READY_OUT : out std_logic;
- MC_FC_READY_OUT : out std_logic;
- MC_FC_WR_EN_IN : in std_logic;
-
MC_BUSY_OUT : out std_logic;
MC_TRANSMIT_DONE_OUT : out std_logic;
MIN_MESSAGE_SIZE_IN : in std_logic_vector(31 downto 0); -- gk 20.07.10
READOUT_CTR_IN : in std_logic_vector(23 downto 0); -- gk 26.04.10
READOUT_CTR_VALID_IN : in std_logic; -- gk 26.04.10
-
--- SCTRL_DUMMY_SIZE_IN : in std_logic_vector(15 downto 0);
--- SCTRL_DUMMY_PAUSE_IN : in std_logic_vector(31 downto 0);
-
-- PacketConstructor interface
ALLOW_LARGE_IN : in std_logic; -- gk 21.07.10
PC_WR_EN_OUT : out std_logic;
DBG_SELECT_SENT_IN : in std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
DBG_SELECT_PROTOS_IN : in std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
- SCTRL_DUMMY_SIZE_OUT : out std_logic_vector(15 downto 0);
- SCTRL_DUMMY_PAUSE_OUT : out std_logic_vector(31 downto 0);
-
DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0)
--DBG_FIFO_RESET_OUT : out std_logic
);
);
end component;
-component fifo_4kx18x9 is
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-
component fifo_2048x8x16 is
port(
Data : in std_logic_vector(8 downto 0);
);
end component;
-component fifo_4kx8_ecp3 is
-port(
- Data : in std_logic_vector(7 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
component statts_mem is
port (
WrAddress: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0));
end component;
---component slv_mac_memory is
---port(
--- CLK : in std_logic;
--- RESET : in std_logic;
--- BUSY_IN : in std_logic;
--- -- Slave bus
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
--- SLV_READ_IN : in std_logic;
--- SLV_WRITE_IN : in std_logic;
--- SLV_BUSY_OUT : out std_logic;
--- SLV_ACK_OUT : out std_logic;
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- I/O to the backend
--- MEM_CLK_IN : in std_logic;
--- MEM_ADDR_IN : in std_logic_vector(7 downto 0);
--- MEM_DATA_OUT : out std_logic_vector(31 downto 0);
--- -- Status lines
--- STAT : out std_logic_vector(31 downto 0) -- DEBUG
---);
---end component;
-
-component fifo_32kx16x8_mb2
-port(
- Data : in std_logic_vector(17 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmEmptyThresh : in std_logic_vector(15 downto 0);
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(8 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- RCNT : out std_logic_vector(16 downto 0);
- Empty : out std_logic;
- AlmostEmpty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic
-);
-end component;
-
-component fifo_64kx9
-port (
- Data : in std_logic_vector(8 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(8 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_16kx18x9 is
- port (
- Data: in std_logic_vector(17 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- AmEmptyThresh: in std_logic_vector(14 downto 0);
- AmFullThresh: in std_logic_vector(13 downto 0);
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
- AlmostFull: out std_logic);
-end component;
-
-component fifo_32k_9 is
- port (
- Data: in std_logic_vector(8 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(8 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end component;
-
-
-component fifo_512x32x8
-port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
-component fifo_512x8
-port (
- Data : in std_logic_vector(7 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic
-);
-end component;
-
end package;
\ No newline at end of file
signal g_MY_MAC : std_logic_vector(47 downto 0);
-- size of ethernet frame use for fragmentation of outgoing packets
-signal g_MAX_FRAME_SIZE : std_logic_vector(15 downto 0) := x"0200"; -- set up in main controller
+signal g_MAX_FRAME_SIZE : std_logic_vector(15 downto 0); -- set up in main controller
--signal g_MAX_PACKET_SIZE : std_logic_vector(15 downto 0);
constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
-constant c_MAX_PROTOCOLS : integer range 1 to 16 := 4; --5; --4; --5;
+constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5;
constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
-constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 4;
+constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 3;
type frame_types_a is array(c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0);
constant FRAME_TYPES : frame_types_a := (x"0800", x"0806");
-- this are the destination ports of the incoming packet
type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
-constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"6590", x"7530", x"7531"); --x"6590", x"7530", x"7531"); --x"61a8", x"7530", x"7531");
+constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"61a8", x"7530");
-- DHCP client, SCTRL, STATs
component trb_net16_gbe_response_constructor_Forward is
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_WR_EN_OUT : out std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_RD_EN_IN : in std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_WR_EN_OUT : out std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
end component;
component trb_net16_gbe_response_constructor_Trash is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_SIZE_LEFT_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
TC_BUSY_IN : in std_logic;
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_RD_EN_IN : in std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
CLK : in std_logic; -- system clock
RESET : in std_logic;
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
-
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
-component trb_net16_gbe_response_constructor_PseudoPing is
-generic ( STAT_ADDRESS_BASE : integer := 0
-);
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
-- INTERFACE
PS_DATA_IN : in std_logic_vector(8 downto 0);
PS_WR_EN_IN : in std_logic;
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_WR_EN_OUT : out std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_RD_EN_IN : in std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0);
+ TC_BUSY_IN : in std_logic;
STAT_DATA_OUT : out std_logic_vector(31 downto 0);
STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- TC_WR_EN_OUT : out std_logic;
+ TC_RD_EN_IN : in std_logic;
TC_DATA_OUT : out std_logic_vector(8 downto 0);
TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
);
end component;
-component trb_net16_gbe_response_constructor_TrbNetData is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
-
--- INTERFACE
- PS_DATA_IN : in std_logic_vector(8 downto 0);
- PS_WR_EN_IN : in std_logic;
- PS_ACTIVATE_IN : in std_logic;
- PS_RESPONSE_READY_OUT : out std_logic;
- PS_BUSY_OUT : out std_logic;
- PS_SELECTED_IN : in std_logic;
- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
-
- TC_RD_EN_IN : in std_logic;
- TC_DATA_OUT : out std_logic_vector(8 downto 0);
- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
-
- STAT_DATA_OUT : out std_logic_vector(31 downto 0);
- STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
- STAT_DATA_RDY_OUT : out std_logic;
- STAT_DATA_ACK_IN : in std_logic;
- RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
- SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
--- END OF INTERFACE
-
- -- CTS interface
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic;
- CTS_READ_IN : in std_logic;
- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- -- Data payload interface
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
- -- ip configurator
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_BUSY_OUT : out std_logic;
- SLV_ACK_OUT : out std_logic;
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-
- CFG_GBE_ENABLE_IN : in std_logic;
- CFG_IPU_ENABLE_IN : in std_logic;
- CFG_MULT_ENABLE_IN : in std_logic;
-
--- debug
- DEBUG_OUT : out std_logic_vector(31 downto 0)
-);
-end component;
-
end package;
jspc29 / trbnet.git / commitdiff