*** empty log message ***

diff --git a/lattice/scm/lattice_ecp2m_fifo.vhd b/lattice/scm/lattice_ecp2m_fifo.vhd
new file mode 100644 (file)
index 0000000..a580566
--- /dev/null
+++ b/lattice/scm/lattice_ecp2m_fifo.vhd
@@ -0,0 +1,277 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+package lattice_ecp2m_fifo is
+
+  component fifo_var_oreg is
+    generic(
+      FIFO_WIDTH                   : integer range 1 to 64 := 36;
+      FIFO_DEPTH                   : integer range 1 to 16 := 8
+      );
+    port(
+      Data                         : in  std_logic_vector(FIFO_WIDTH-1 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(FIFO_DEPTH-1 downto 0);
+      Q                            : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+      WCNT                         : out std_logic_vector(FIFO_DEPTH downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+  component fifo_36x256_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(7 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(8 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x512_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(8 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(9 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x1k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(9 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(10 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x2k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(10 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(11 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x4k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(11 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(12 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x8k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(12 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(13 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_36x16k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(12 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(13 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+  component fifo_36x32k_oreg
+    port (
+      Data                         : in  std_logic_vector(35 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(13 downto 0);
+      Q                            : out std_logic_vector(35 downto 0);
+      WCNT                         : out std_logic_vector(14 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+  component fifo_18x256_oreg
+    port (
+      Data                         : in  std_logic_vector(17 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(7 downto 0);
+      Q                            : out std_logic_vector(17 downto 0);
+      WCNT                         : out std_logic_vector(8 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_18x512_oreg
+    port (
+      Data                         : in  std_logic_vector(17 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(8 downto 0);
+      Q                            : out std_logic_vector(17 downto 0);
+      WCNT                         : out std_logic_vector(9 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_18x1k_oreg
+    port (
+      Data                         : in  std_logic_vector(17 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(9 downto 0);
+      Q                            : out std_logic_vector(17 downto 0);
+      WCNT                         : out std_logic_vector(10 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_18x2k_oreg
+    port (
+      Data                         : in  std_logic_vector(17 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(10 downto 0);
+      Q                            : out std_logic_vector(17 downto 0);
+      WCNT                         : out std_logic_vector(11 downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+
+
+  component fifo_18x16_media_interface is
+    port (
+      Data: in  std_logic_vector(17 downto 0);
+      Clock: in  std_logic;
+      WrEn: in  std_logic;
+      RdEn: in  std_logic;
+      Reset: in  std_logic;
+      Q: out  std_logic_vector(17 downto 0);
+      WCNT: out  std_logic_vector(4 downto 0);
+      Empty: out  std_logic;
+      Full: out  std_logic;
+      AlmostEmpty: out  std_logic
+      );
+  end component;
+
+  component fifo_19x16_obuf is
+      port (
+          Data: in  std_logic_vector(18 downto 0);
+          Clock: in  std_logic;
+          WrEn: in  std_logic;
+          RdEn: in  std_logic;
+          Reset: in  std_logic;
+          AmEmptyThresh: in  std_logic_vector(3 downto 0);
+          AmFullThresh: in  std_logic_vector(3 downto 0);
+          Q: out  std_logic_vector(18 downto 0);
+          Empty: out  std_logic;
+          Full: out  std_logic;
+          AlmostEmpty: out  std_logic;
+          AlmostFull: out  std_logic);
+  end component;
+
+
+
+end package;
\ No newline at end of file

diff --git a/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.lpc b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.lpc
new file mode 100644 (file)
index 0000000..3809386
--- /dev/null
+++ b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.lpc
@@ -0,0 +1,55 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=-7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=trb_net16_med_scm_scp_gbe_0
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=06/22/2010
+Time=14:56:25
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+QuadMode=Gigabit Ethernet
+enChannel0=1
+enChannel1=0
+enChannel2=0
+enChannel3=0
+enAlign0=0
+enAlign1=0
+enAlign2=0
+enControlPorts=0
+enSystemBus=0
+en10gLsm=0
+ClkSelect=FPGA Logic Sourced Transmit/Receive Reference Clocks
+BitClkRate=2
+RefClkMult=10X
+RefClkRate=200
+BusWidth=16
+IntClkRate=100
+AmpBoost=Disabled
+Bit1=1
+Word1=FF
+Bit2=1
+Word2=7C
+Bit3=1
+Word3=7C
+enQuad=0
+QuadGroup=Group 0

diff --git a/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.txt b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.txt
new file mode 100644 (file)
index 0000000..9d57951
--- /dev/null
+++ b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.txt
@@ -0,0 +1,40 @@
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCS quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCS quad to the final design requirements.
+# channel_0 is in "Gigabit Ethernet" mode
+# channel_1 is in "Disabled" mode
+# channel_2 is in "Disabled" mode
+# channel_3 is in "Disabled" mode
+
+ch0 13 03  # Powerup Channel
+ch0 00 09  # rx_sof enabled
+quad 00 00
+quad 01 E4  
+quad 28 50  # Reference clock multiplier
+quad 29 11  # FPGA sourced refclk
+quad 02 00  # ref_pclk source is ch0
+# quad 18 00  # Gigabit Ethernet Mode
+quad 14 7F  # Word Alignment Mask
+quad 15 03  # +ve K
+quad 16 7C  # -ve K
+quad 0D 97  # Watermark level on CTC
+quad 0E 0B  # insertion/deletion control of CTC
+quad 11 BC  # /I2/ pattern for CTC match
+quad 12 50
+quad 13 04
+quad 1D 57  # GbE Tx CRC polynomial
+quad 1E 1E  # GbE Rx CRC polynomial
+quad 19 0C  # FPGA bus width is 16-bit/20-bit
+ch0 14 90  # 16% pre-emphasis 
+ch0 15 10  # +6dB equalization
+
+# These lines must appear last in the autoconfig file.  These lines apply the correct 
+# reset sequence to the PCS block upon bitstream configuration
+quad 41 00  # de-assert serdes_rst
+quad 40 ff  # assert datapath reset for all channels
+quad 40 00  # de-assert datapath reset for all channels
+
+
+

diff --git a/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.vhd b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.vhd
new file mode 100644 (file)
index 0000000..623c97c
--- /dev/null
+++ b/media_interfaces/scm_sfp/trb_net16_med_scm_scp_gbe_0.vhd
@@ -0,0 +1,2385 @@
+
+
+-- channel_0 is in "Gigabit Ethernet" mode
+-- channel_1 is in "Disabled" mode
+-- channel_2 is in "Disabled" mode
+-- channel_3 is in "Disabled" mode
+
+--synopsys translate_off
+
+library pcsa_work;
+use pcsa_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSA is
+GENERIC(
+  CONFIG_FILE : String  := "trb_net16_med_scm_scp_gbe_0.txt"
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+
+end PCSA;
+
+architecture PCSA_arch of PCSA is
+
+component PCSA_sim
+GENERIC(
+  CONFIG_FILE : String
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+
+begin
+
+PCSA_sim_inst : PCSA_sim 
+generic map (
+  CONFIG_FILE => CONFIG_FILE)
+port map (
+  HDINP0 => HDINP0,
+  HDINN0 => HDINN0,
+  HDINP1 => HDINP1,
+  HDINN1 => HDINN1,
+  HDINP2 => HDINP2,
+  HDINN2 => HDINN2,
+  HDINP3 => HDINP3,
+  HDINN3 => HDINN3,
+  HDOUTP0 => HDOUTP0,
+  HDOUTN0 => HDOUTN0,
+  HDOUTP1 => HDOUTP1,
+  HDOUTN1 => HDOUTN1,
+  HDOUTP2 => HDOUTP2,
+  HDOUTN2 => HDOUTN2,
+  HDOUTP3 => HDOUTP3,
+  HDOUTN3 => HDOUTN3,
+  REFCLKP => REFCLKP,
+  REFCLKN => REFCLKN,
+  RXREFCLKP => RXREFCLKP,
+  RXREFCLKN => RXREFCLKN,
+  FFC_QUAD_RST => FFC_QUAD_RST,
+  FFC_MACRO_RST => FFC_MACRO_RST,
+  FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,
+  FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,
+  FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,
+  FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,
+  FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,
+  FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,
+  FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,
+  FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,
+  FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,
+  FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,
+  FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,
+  FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,
+  FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+  FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+  FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+  FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+  FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+  FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+  FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+  FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+  FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+  FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+  FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+  FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+  FFC_PCIE_TX_0 => FFC_PCIE_TX_0,
+  FFC_PCIE_TX_1 => FFC_PCIE_TX_1,
+  FFC_PCIE_TX_2 => FFC_PCIE_TX_2,
+  FFC_PCIE_TX_3 => FFC_PCIE_TX_3,
+  FFC_PCIE_RX_0 => FFC_PCIE_RX_0,
+  FFC_PCIE_RX_1 => FFC_PCIE_RX_1,
+  FFC_PCIE_RX_2 => FFC_PCIE_RX_2,
+  FFC_PCIE_RX_3 => FFC_PCIE_RX_3,
+  FFC_SD_0 => FFC_SD_0,
+  FFC_SD_1 => FFC_SD_1,
+  FFC_SD_2 => FFC_SD_2,
+  FFC_SD_3 => FFC_SD_3,
+  FFC_EN_CGA_0 => FFC_EN_CGA_0,
+  FFC_EN_CGA_1 => FFC_EN_CGA_1,
+  FFC_EN_CGA_2 => FFC_EN_CGA_2,
+  FFC_EN_CGA_3 => FFC_EN_CGA_3,
+  FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,
+  FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,
+  FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,
+  FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,
+  FFC_AB_RESET => FFC_AB_RESET,
+  FFC_CD_RESET => FFC_CD_RESET,
+  FFS_LS_STATUS_0 => FFS_LS_STATUS_0,
+  FFS_LS_STATUS_1 => FFS_LS_STATUS_1,
+  FFS_LS_STATUS_2 => FFS_LS_STATUS_2,
+  FFS_LS_STATUS_3 => FFS_LS_STATUS_3,
+  FFS_AB_STATUS => FFS_AB_STATUS,
+  FFS_CD_STATUS => FFS_CD_STATUS,
+  FFS_AB_ALIGNED => FFS_AB_ALIGNED,
+  FFS_CD_ALIGNED => FFS_CD_ALIGNED,
+  FFS_AB_FAILED => FFS_AB_FAILED,
+  FFS_CD_FAILED => FFS_CD_FAILED,
+  FFS_RLOS_LO0 => FFS_RLOS_LO0,
+  FFS_RLOS_LO1 => FFS_RLOS_LO1,
+  FFS_RLOS_LO2 => FFS_RLOS_LO2,
+  FFS_RLOS_LO3 => FFS_RLOS_LO3,
+  FFC_FB_LB_0 => FFC_FB_LB_0,
+  FFC_FB_LB_1 => FFC_FB_LB_1,
+  FFC_FB_LB_2 => FFC_FB_LB_2,
+  FFC_FB_LB_3 => FFC_FB_LB_3,
+  FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+  FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+  FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+  FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+  FFS_CC_ORUN_0 => FFS_CC_ORUN_0,
+  FFS_CC_ORUN_1 => FFS_CC_ORUN_1,
+  FFS_CC_ORUN_2 => FFS_CC_ORUN_2,
+  FFS_CC_ORUN_3 => FFS_CC_ORUN_3,
+  FFS_CC_URUN_0 => FFS_CC_URUN_0,
+  FFS_CC_URUN_1 => FFS_CC_URUN_1,
+  FFS_CC_URUN_2 => FFS_CC_URUN_2,
+  FFS_CC_URUN_3 => FFS_CC_URUN_3,
+  FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+  FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+  BS4PAD_0 => BS4PAD_0,
+  BS4PAD_1 => BS4PAD_1,
+  BS4PAD_2 => BS4PAD_2,
+  BS4PAD_3 => BS4PAD_3,
+  RDATAO_7 => RDATAO_7,
+  RDATAO_6 => RDATAO_6,
+  RDATAO_5 => RDATAO_5,
+  RDATAO_4 => RDATAO_4,
+  RDATAO_3 => RDATAO_3,
+  RDATAO_2 => RDATAO_2,
+  RDATAO_1 => RDATAO_1,
+  RDATAO_0 => RDATAO_0,
+  INTO => INTO,
+  ADDRI_7 => ADDRI_7,
+  ADDRI_6 => ADDRI_6,
+  ADDRI_5 => ADDRI_5,
+  ADDRI_4 => ADDRI_4,
+  ADDRI_3 => ADDRI_3,
+  ADDRI_2 => ADDRI_2,
+  ADDRI_1 => ADDRI_1,
+  ADDRI_0 => ADDRI_0,
+  WDATAI_7 => WDATAI_7,
+  WDATAI_6 => WDATAI_6,
+  WDATAI_5 => WDATAI_5,
+  WDATAI_4 => WDATAI_4,
+  WDATAI_3 => WDATAI_3,
+  WDATAI_2 => WDATAI_2,
+  WDATAI_1 => WDATAI_1,
+  WDATAI_0 => WDATAI_0,
+  RDI => RDI,
+  WSTBI => WSTBI,
+  CS_CHIF_0 => CS_CHIF_0,
+  CS_CHIF_1 => CS_CHIF_1,
+  CS_CHIF_2 => CS_CHIF_2,
+  CS_CHIF_3 => CS_CHIF_3,
+  CS_QIF => CS_QIF,
+  QUAD_ID_1 => QUAD_ID_1,
+  QUAD_ID_0 => QUAD_ID_0,
+  FF_SYSCLK_P1 => FF_SYSCLK_P1,
+  FF_SYSCLK0 => FF_SYSCLK0,
+  FF_SYSCLK1 => FF_SYSCLK1,
+  FF_SYSCLK2 => FF_SYSCLK2,
+  FF_SYSCLK3 => FF_SYSCLK3,
+  FF_RXCLK_P1 => FF_RXCLK_P1,
+  FF_RXCLK_P2 => FF_RXCLK_P2,
+  FF_RXCLK0 => FF_RXCLK0,
+  FF_RXCLK1 => FF_RXCLK1,
+  FF_RXCLK2 => FF_RXCLK2,
+  FF_RXCLK3 => FF_RXCLK3,
+  QUAD_CLK => QUAD_CLK,
+  GRP_CLK_P1_3 => GRP_CLK_P1_3,
+  GRP_CLK_P1_2 => GRP_CLK_P1_2,
+  GRP_CLK_P1_1 => GRP_CLK_P1_1,
+  GRP_CLK_P1_0 => GRP_CLK_P1_0,
+  GRP_CLK_P2_3 => GRP_CLK_P2_3,
+  GRP_CLK_P2_2 => GRP_CLK_P2_2,
+  GRP_CLK_P2_1 => GRP_CLK_P2_1,
+  GRP_CLK_P2_0 => GRP_CLK_P2_0,
+  GRP_START_3 => GRP_START_3,
+  GRP_START_2 => GRP_START_2,
+  GRP_START_1 => GRP_START_1,
+  GRP_START_0 => GRP_START_0,
+  GRP_DONE_3 => GRP_DONE_3,
+  GRP_DONE_2 => GRP_DONE_2,
+  GRP_DONE_1 => GRP_DONE_1,
+  GRP_DONE_0 => GRP_DONE_0,
+  GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,
+  GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,
+  GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,
+  GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,
+  IQA_START_LS => IQA_START_LS,
+  IQA_DONE_LS => IQA_DONE_LS,
+  IQA_AND_FP1_LS => IQA_AND_FP1_LS,
+  IQA_AND_FP0_LS => IQA_AND_FP0_LS,
+  IQA_OR_FP1_LS => IQA_OR_FP1_LS,
+  IQA_OR_FP0_LS => IQA_OR_FP0_LS,
+  IQA_RST_N => IQA_RST_N,
+  FF_TCLK0 => FF_TCLK0,
+  FF_TCLK1 => FF_TCLK1,
+  FF_TCLK2 => FF_TCLK2,
+  FF_TCLK3 => FF_TCLK3,
+  FF_RCLK0 => FF_RCLK0,
+  FF_RCLK1 => FF_RCLK1,
+  FF_RCLK2 => FF_RCLK2,
+  FF_RCLK3 => FF_RCLK3,
+  TCK_FMACP => TCK_FMACP,
+  FF_TXD_0_23 => FF_TXD_0_23,
+  FF_TXD_0_22 => FF_TXD_0_22,
+  FF_TXD_0_21 => FF_TXD_0_21,
+  FF_TXD_0_20 => FF_TXD_0_20,
+  FF_TXD_0_19 => FF_TXD_0_19,
+  FF_TXD_0_18 => FF_TXD_0_18,
+  FF_TXD_0_17 => FF_TXD_0_17,
+  FF_TXD_0_16 => FF_TXD_0_16,
+  FF_TXD_0_15 => FF_TXD_0_15,
+  FF_TXD_0_14 => FF_TXD_0_14,
+  FF_TXD_0_13 => FF_TXD_0_13,
+  FF_TXD_0_12 => FF_TXD_0_12,
+  FF_TXD_0_11 => FF_TXD_0_11,
+  FF_TXD_0_10 => FF_TXD_0_10,
+  FF_TXD_0_9 => FF_TXD_0_9,
+  FF_TXD_0_8 => FF_TXD_0_8,
+  FF_TXD_0_7 => FF_TXD_0_7,
+  FF_TXD_0_6 => FF_TXD_0_6,
+  FF_TXD_0_5 => FF_TXD_0_5,
+  FF_TXD_0_4 => FF_TXD_0_4,
+  FF_TXD_0_3 => FF_TXD_0_3,
+  FF_TXD_0_2 => FF_TXD_0_2,
+  FF_TXD_0_1 => FF_TXD_0_1,
+  FF_TXD_0_0 => FF_TXD_0_0,
+  FB_RXD_0_23 => FB_RXD_0_23,
+  FB_RXD_0_22 => FB_RXD_0_22,
+  FB_RXD_0_21 => FB_RXD_0_21,
+  FB_RXD_0_20 => FB_RXD_0_20,
+  FB_RXD_0_19 => FB_RXD_0_19,
+  FB_RXD_0_18 => FB_RXD_0_18,
+  FB_RXD_0_17 => FB_RXD_0_17,
+  FB_RXD_0_16 => FB_RXD_0_16,
+  FB_RXD_0_15 => FB_RXD_0_15,
+  FB_RXD_0_14 => FB_RXD_0_14,
+  FB_RXD_0_13 => FB_RXD_0_13,
+  FB_RXD_0_12 => FB_RXD_0_12,
+  FB_RXD_0_11 => FB_RXD_0_11,
+  FB_RXD_0_10 => FB_RXD_0_10,
+  FB_RXD_0_9 => FB_RXD_0_9,
+  FB_RXD_0_8 => FB_RXD_0_8,
+  FB_RXD_0_7 => FB_RXD_0_7,
+  FB_RXD_0_6 => FB_RXD_0_6,
+  FB_RXD_0_5 => FB_RXD_0_5,
+  FB_RXD_0_4 => FB_RXD_0_4,
+  FB_RXD_0_3 => FB_RXD_0_3,
+  FB_RXD_0_2 => FB_RXD_0_2,
+  FB_RXD_0_1 => FB_RXD_0_1,
+  FB_RXD_0_0 => FB_RXD_0_0,
+  FF_TXD_1_23 => FF_TXD_1_23,
+  FF_TXD_1_22 => FF_TXD_1_22,
+  FF_TXD_1_21 => FF_TXD_1_21,
+  FF_TXD_1_20 => FF_TXD_1_20,
+  FF_TXD_1_19 => FF_TXD_1_19,
+  FF_TXD_1_18 => FF_TXD_1_18,
+  FF_TXD_1_17 => FF_TXD_1_17,
+  FF_TXD_1_16 => FF_TXD_1_16,
+  FF_TXD_1_15 => FF_TXD_1_15,
+  FF_TXD_1_14 => FF_TXD_1_14,
+  FF_TXD_1_13 => FF_TXD_1_13,
+  FF_TXD_1_12 => FF_TXD_1_12,
+  FF_TXD_1_11 => FF_TXD_1_11,
+  FF_TXD_1_10 => FF_TXD_1_10,
+  FF_TXD_1_9 => FF_TXD_1_9,
+  FF_TXD_1_8 => FF_TXD_1_8,
+  FF_TXD_1_7 => FF_TXD_1_7,
+  FF_TXD_1_6 => FF_TXD_1_6,
+  FF_TXD_1_5 => FF_TXD_1_5,
+  FF_TXD_1_4 => FF_TXD_1_4,
+  FF_TXD_1_3 => FF_TXD_1_3,
+  FF_TXD_1_2 => FF_TXD_1_2,
+  FF_TXD_1_1 => FF_TXD_1_1,
+  FF_TXD_1_0 => FF_TXD_1_0,
+  FB_RXD_1_23 => FB_RXD_1_23,
+  FB_RXD_1_22 => FB_RXD_1_22,
+  FB_RXD_1_21 => FB_RXD_1_21,
+  FB_RXD_1_20 => FB_RXD_1_20,
+  FB_RXD_1_19 => FB_RXD_1_19,
+  FB_RXD_1_18 => FB_RXD_1_18,
+  FB_RXD_1_17 => FB_RXD_1_17,
+  FB_RXD_1_16 => FB_RXD_1_16,
+  FB_RXD_1_15 => FB_RXD_1_15,
+  FB_RXD_1_14 => FB_RXD_1_14,
+  FB_RXD_1_13 => FB_RXD_1_13,
+  FB_RXD_1_12 => FB_RXD_1_12,
+  FB_RXD_1_11 => FB_RXD_1_11,
+  FB_RXD_1_10 => FB_RXD_1_10,
+  FB_RXD_1_9 => FB_RXD_1_9,
+  FB_RXD_1_8 => FB_RXD_1_8,
+  FB_RXD_1_7 => FB_RXD_1_7,
+  FB_RXD_1_6 => FB_RXD_1_6,
+  FB_RXD_1_5 => FB_RXD_1_5,
+  FB_RXD_1_4 => FB_RXD_1_4,
+  FB_RXD_1_3 => FB_RXD_1_3,
+  FB_RXD_1_2 => FB_RXD_1_2,
+  FB_RXD_1_1 => FB_RXD_1_1,
+  FB_RXD_1_0 => FB_RXD_1_0,
+  FF_TXD_2_23 => FF_TXD_2_23,
+  FF_TXD_2_22 => FF_TXD_2_22,
+  FF_TXD_2_21 => FF_TXD_2_21,
+  FF_TXD_2_20 => FF_TXD_2_20,
+  FF_TXD_2_19 => FF_TXD_2_19,
+  FF_TXD_2_18 => FF_TXD_2_18,
+  FF_TXD_2_17 => FF_TXD_2_17,
+  FF_TXD_2_16 => FF_TXD_2_16,
+  FF_TXD_2_15 => FF_TXD_2_15,
+  FF_TXD_2_14 => FF_TXD_2_14,
+  FF_TXD_2_13 => FF_TXD_2_13,
+  FF_TXD_2_12 => FF_TXD_2_12,
+  FF_TXD_2_11 => FF_TXD_2_11,
+  FF_TXD_2_10 => FF_TXD_2_10,
+  FF_TXD_2_9 => FF_TXD_2_9,
+  FF_TXD_2_8 => FF_TXD_2_8,
+  FF_TXD_2_7 => FF_TXD_2_7,
+  FF_TXD_2_6 => FF_TXD_2_6,
+  FF_TXD_2_5 => FF_TXD_2_5,
+  FF_TXD_2_4 => FF_TXD_2_4,
+  FF_TXD_2_3 => FF_TXD_2_3,
+  FF_TXD_2_2 => FF_TXD_2_2,
+  FF_TXD_2_1 => FF_TXD_2_1,
+  FF_TXD_2_0 => FF_TXD_2_0,
+  FB_RXD_2_23 => FB_RXD_2_23,
+  FB_RXD_2_22 => FB_RXD_2_22,
+  FB_RXD_2_21 => FB_RXD_2_21,
+  FB_RXD_2_20 => FB_RXD_2_20,
+  FB_RXD_2_19 => FB_RXD_2_19,
+  FB_RXD_2_18 => FB_RXD_2_18,
+  FB_RXD_2_17 => FB_RXD_2_17,
+  FB_RXD_2_16 => FB_RXD_2_16,
+  FB_RXD_2_15 => FB_RXD_2_15,
+  FB_RXD_2_14 => FB_RXD_2_14,
+  FB_RXD_2_13 => FB_RXD_2_13,
+  FB_RXD_2_12 => FB_RXD_2_12,
+  FB_RXD_2_11 => FB_RXD_2_11,
+  FB_RXD_2_10 => FB_RXD_2_10,
+  FB_RXD_2_9 => FB_RXD_2_9,
+  FB_RXD_2_8 => FB_RXD_2_8,
+  FB_RXD_2_7 => FB_RXD_2_7,
+  FB_RXD_2_6 => FB_RXD_2_6,
+  FB_RXD_2_5 => FB_RXD_2_5,
+  FB_RXD_2_4 => FB_RXD_2_4,
+  FB_RXD_2_3 => FB_RXD_2_3,
+  FB_RXD_2_2 => FB_RXD_2_2,
+  FB_RXD_2_1 => FB_RXD_2_1,
+  FB_RXD_2_0 => FB_RXD_2_0,
+  FF_TXD_3_23 => FF_TXD_3_23,
+  FF_TXD_3_22 => FF_TXD_3_22,
+  FF_TXD_3_21 => FF_TXD_3_21,
+  FF_TXD_3_20 => FF_TXD_3_20,
+  FF_TXD_3_19 => FF_TXD_3_19,
+  FF_TXD_3_18 => FF_TXD_3_18,
+  FF_TXD_3_17 => FF_TXD_3_17,
+  FF_TXD_3_16 => FF_TXD_3_16,
+  FF_TXD_3_15 => FF_TXD_3_15,
+  FF_TXD_3_14 => FF_TXD_3_14,
+  FF_TXD_3_13 => FF_TXD_3_13,
+  FF_TXD_3_12 => FF_TXD_3_12,
+  FF_TXD_3_11 => FF_TXD_3_11,
+  FF_TXD_3_10 => FF_TXD_3_10,
+  FF_TXD_3_9 => FF_TXD_3_9,
+  FF_TXD_3_8 => FF_TXD_3_8,
+  FF_TXD_3_7 => FF_TXD_3_7,
+  FF_TXD_3_6 => FF_TXD_3_6,
+  FF_TXD_3_5 => FF_TXD_3_5,
+  FF_TXD_3_4 => FF_TXD_3_4,
+  FF_TXD_3_3 => FF_TXD_3_3,
+  FF_TXD_3_2 => FF_TXD_3_2,
+  FF_TXD_3_1 => FF_TXD_3_1,
+  FF_TXD_3_0 => FF_TXD_3_0,
+  FB_RXD_3_23 => FB_RXD_3_23,
+  FB_RXD_3_22 => FB_RXD_3_22,
+  FB_RXD_3_21 => FB_RXD_3_21,
+  FB_RXD_3_20 => FB_RXD_3_20,
+  FB_RXD_3_19 => FB_RXD_3_19,
+  FB_RXD_3_18 => FB_RXD_3_18,
+  FB_RXD_3_17 => FB_RXD_3_17,
+  FB_RXD_3_16 => FB_RXD_3_16,
+  FB_RXD_3_15 => FB_RXD_3_15,
+  FB_RXD_3_14 => FB_RXD_3_14,
+  FB_RXD_3_13 => FB_RXD_3_13,
+  FB_RXD_3_12 => FB_RXD_3_12,
+  FB_RXD_3_11 => FB_RXD_3_11,
+  FB_RXD_3_10 => FB_RXD_3_10,
+  FB_RXD_3_9 => FB_RXD_3_9,
+  FB_RXD_3_8 => FB_RXD_3_8,
+  FB_RXD_3_7 => FB_RXD_3_7,
+  FB_RXD_3_6 => FB_RXD_3_6,
+  FB_RXD_3_5 => FB_RXD_3_5,
+  FB_RXD_3_4 => FB_RXD_3_4,
+  FB_RXD_3_3 => FB_RXD_3_3,
+  FB_RXD_3_2 => FB_RXD_3_2,
+  FB_RXD_3_1 => FB_RXD_3_1,
+  FB_RXD_3_0 => FB_RXD_3_0,
+  TCK_FMAC => TCK_FMAC,
+  COUT_21 => COUT_21,
+  COUT_20 => COUT_20,
+  COUT_19 => COUT_19,
+  COUT_18 => COUT_18,
+  COUT_17 => COUT_17,
+  COUT_16 => COUT_16,
+  COUT_15 => COUT_15,
+  COUT_14 => COUT_14,
+  COUT_13 => COUT_13,
+  COUT_12 => COUT_12,
+  COUT_11 => COUT_11,
+  COUT_10 => COUT_10,
+  COUT_9 => COUT_9,
+  COUT_8 => COUT_8,
+  COUT_7 => COUT_7,
+  COUT_6 => COUT_6,
+  COUT_5 => COUT_5,
+  COUT_4 => COUT_4,
+  COUT_3 => COUT_3,
+  COUT_2 => COUT_2,
+  COUT_1 => COUT_1,
+  COUT_0 => COUT_0,
+  CIN_12 => CIN_12,
+  CIN_11 => CIN_11,
+  CIN_10 => CIN_10,
+  CIN_9 => CIN_9,
+  CIN_8 => CIN_8,
+  CIN_7 => CIN_7,
+  CIN_6 => CIN_6,
+  CIN_5 => CIN_5,
+  CIN_4 => CIN_4,
+  CIN_3 => CIN_3,
+  CIN_2 => CIN_2,
+  CIN_1 => CIN_1,
+  CIN_0 => CIN_0,
+  TESTCLK_MACO => TESTCLK_MACO
+);
+
+end PCSA_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library SC;
+use SC.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+
+entity trb_net16_med_scm_scp_gbe_0 is
+   GENERIC (USER_CONFIG_FILE    :  String := "trb_net16_med_scm_scp_gbe_0.txt");
+ port (
+-- serdes clk pins --
+  rxrefclk, refclk : in std_logic;
+  hdinp_0, hdinn_0 : in std_logic;
+  hdoutp_0, hdoutn_0 : out std_logic;
+  tclk_0, rclk_0 : in std_logic;
+  tx_rst_0, rx_rst_0 : in std_logic;
+  ref_0_sclk : out std_logic;
+  txd_0 : in std_logic_vector (15 downto 0);
+  tx_en_0, tx_er_0, tx_crc_insert_0, tx_sfd_0 : in std_logic_vector (1 downto 0);
+  rxd_0 : out std_logic_vector (15 downto 0);
+  rx_dv_0, rx_er_0, rx_crc_eop_0, rx_sfd_0 : out std_logic_vector (1 downto 0);
+
+
+
+  quad_rst, serdes_rst : in std_logic;
+  ref_pclk : out std_logic);
+
+end trb_net16_med_scm_scp_gbe_0;
+
+architecture trb_net16_med_scm_scp_gbe_0_arch of trb_net16_med_scm_scp_gbe_0 is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+component PCSA
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String
+  );
+--synopsys translate_on
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+   attribute IS_ASB: string;
+   attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;
+   attribute CH0_RX_MAXRATE: string;
+   attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH1_RX_MAXRATE: string;
+   attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH2_RX_MAXRATE: string;
+   attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH3_RX_MAXRATE: string;
+   attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH0_TX_MAXRATE: string;
+   attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH1_TX_MAXRATE: string;
+   attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH2_TX_MAXRATE: string;
+   attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH3_TX_MAXRATE: string;
+   attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute AMP_BOOST: string;
+   attribute AMP_BOOST of PCSA_INST : label is "DISABLED";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSA_INST : PCSA
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map  ( 
+  REFCLKP => fpsc_vlo,
+  REFCLKN => fpsc_vlo,
+  RXREFCLKP => fpsc_vlo,
+  RXREFCLKN => fpsc_vlo,
+  FFC_CK_CORE_RX => rxrefclk,
+  FFC_CK_CORE_TX => refclk,
+  CS_CHIF_0 => fpsc_vlo,
+  CS_CHIF_1 => fpsc_vlo,
+  CS_CHIF_2 => fpsc_vlo,
+  CS_CHIF_3 => fpsc_vlo,
+  CS_QIF => fpsc_vlo,
+  QUAD_ID_0 => fpsc_vlo,
+  QUAD_ID_1 => fpsc_vlo,
+  ADDRI_0 => fpsc_vlo,
+  ADDRI_1 => fpsc_vlo,
+  ADDRI_2 => fpsc_vlo,
+  ADDRI_3 => fpsc_vlo,
+  ADDRI_4 => fpsc_vlo,
+  ADDRI_5 => fpsc_vlo,
+  ADDRI_6 => fpsc_vlo,
+  ADDRI_7 => fpsc_vlo,
+  WDATAI_0 => fpsc_vlo,
+  WDATAI_1 => fpsc_vlo,
+  WDATAI_2 => fpsc_vlo,
+  WDATAI_3 => fpsc_vlo,
+  WDATAI_4 => fpsc_vlo,
+  WDATAI_5 => fpsc_vlo,
+  WDATAI_6 => fpsc_vlo,
+  WDATAI_7 => fpsc_vlo,
+  RDI => fpsc_vlo,
+  WSTBI => fpsc_vlo,
+  GRP_CLK_P1_0 => fpsc_vlo,
+  GRP_CLK_P1_1 => fpsc_vlo,
+  GRP_CLK_P1_2 => fpsc_vlo,
+  GRP_CLK_P1_3 => fpsc_vlo,
+  GRP_CLK_P2_0 => fpsc_vlo,
+  GRP_CLK_P2_1 => fpsc_vlo,
+  GRP_CLK_P2_2 => fpsc_vlo,
+  GRP_CLK_P2_3 => fpsc_vlo,
+  GRP_START_0 => fpsc_vlo,
+  GRP_START_1 => fpsc_vlo,
+  GRP_START_2 => fpsc_vlo,
+  GRP_START_3 => fpsc_vlo,
+  GRP_DONE_0 => fpsc_vlo,
+  GRP_DONE_1 => fpsc_vlo,
+  GRP_DONE_2 => fpsc_vlo,
+  GRP_DONE_3 => fpsc_vlo,
+  GRP_DESKEW_ERROR_0 => fpsc_vlo,
+  GRP_DESKEW_ERROR_1 => fpsc_vlo,
+  GRP_DESKEW_ERROR_2 => fpsc_vlo,
+  GRP_DESKEW_ERROR_3 => fpsc_vlo,
+-- to sysbusa
+  RDATAO_0 => open,
+  RDATAO_1 => open,
+  RDATAO_2 => open,
+  RDATAO_3 => open,
+  RDATAO_4 => open,
+  RDATAO_5 => open,
+  RDATAO_6 => open,
+  RDATAO_7 => open,
+  INTO => open,
+  QUAD_CLK => open,
+  IQA_START_LS => open,
+  IQA_DONE_LS => open,
+  IQA_AND_FP1_LS => open,
+  IQA_AND_FP0_LS => open,
+  IQA_OR_FP1_LS => open,
+  IQA_OR_FP0_LS => open,
+  IQA_RST_N => open,
+
+  FF_TXD_0_19 => txd_0(15),
+  FF_TXD_0_18 => txd_0(14),
+  FF_TXD_0_17 => txd_0(13),
+  FF_TXD_0_16 => txd_0(12),
+  FF_TXD_0_15 => txd_0(11),
+  FF_TXD_0_14 => txd_0(10),
+  FF_TXD_0_13 => txd_0(9),
+  FF_TXD_0_12 => txd_0(8),
+  FF_TXD_0_7 => txd_0(7),
+  FF_TXD_0_6 => txd_0(6),
+  FF_TXD_0_5 => txd_0(5),
+  FF_TXD_0_4 => txd_0(4),
+  FF_TXD_0_3 => txd_0(3),
+  FF_TXD_0_2 => txd_0(2),
+  FF_TXD_0_1 => txd_0(1),
+  FF_TXD_0_0 => txd_0(0),
+  FB_RXD_0_19 => rxd_0(15),
+  FB_RXD_0_18 => rxd_0(14),
+  FB_RXD_0_17 => rxd_0(13),
+  FB_RXD_0_16 => rxd_0(12),
+  FB_RXD_0_15 => rxd_0(11),
+  FB_RXD_0_14 => rxd_0(10),
+  FB_RXD_0_13 => rxd_0(9),
+  FB_RXD_0_12 => rxd_0(8),
+  FB_RXD_0_7 => rxd_0(7),
+  FB_RXD_0_6 => rxd_0(6),
+  FB_RXD_0_5 => rxd_0(5),
+  FB_RXD_0_4 => rxd_0(4),
+  FB_RXD_0_3 => rxd_0(3),
+  FB_RXD_0_2 => rxd_0(2),
+  FB_RXD_0_1 => rxd_0(1),
+  FB_RXD_0_0 => rxd_0(0),
+
+  FF_TXD_0_20 => tx_en_0(1),
+  FF_TXD_0_8 => tx_en_0(0),
+  FB_RXD_0_20 => rx_dv_0(1),
+  FB_RXD_0_8 => rx_dv_0(0),
+
+  FF_TXD_0_21 => tx_er_0(1),
+  FF_TXD_0_9 => tx_er_0(0),
+
+  FF_TXD_0_22 => tx_crc_insert_0(1),
+  FF_TXD_0_10 => tx_crc_insert_0(0),
+
+  FF_TXD_0_23 => tx_sfd_0(1),
+  FF_TXD_0_11 => tx_sfd_0(0),
+
+  FB_RXD_0_21 => rx_er_0(1),
+  FB_RXD_0_9 => rx_er_0(0),
+
+  FB_RXD_0_22 => rx_sfd_0(1),
+  FB_RXD_0_10 => rx_sfd_0(0),
+
+  FB_RXD_0_23 => rx_crc_eop_0(1),
+  FB_RXD_0_11 => rx_crc_eop_0(0),
+
+  FF_TXD_1_19 => fpsc_vlo,
+  FF_TXD_1_18 => fpsc_vlo,
+  FF_TXD_1_17 => fpsc_vlo,
+  FF_TXD_1_16 => fpsc_vlo,
+  FF_TXD_1_15 => fpsc_vlo,
+  FF_TXD_1_14 => fpsc_vlo,
+  FF_TXD_1_13 => fpsc_vlo,
+  FF_TXD_1_12 => fpsc_vlo,
+  FF_TXD_1_7 => fpsc_vlo,
+  FF_TXD_1_6 => fpsc_vlo,
+  FF_TXD_1_5 => fpsc_vlo,
+  FF_TXD_1_4 => fpsc_vlo,
+  FF_TXD_1_3 => fpsc_vlo,
+  FF_TXD_1_2 => fpsc_vlo,
+  FF_TXD_1_1 => fpsc_vlo,
+  FF_TXD_1_0 => fpsc_vlo,
+  FB_RXD_1_19 => open,
+  FB_RXD_1_18 => open,
+  FB_RXD_1_17 => open,
+  FB_RXD_1_16 => open,
+  FB_RXD_1_15 => open,
+  FB_RXD_1_14 => open,
+  FB_RXD_1_13 => open,
+  FB_RXD_1_12 => open,
+  FB_RXD_1_7 => open,
+  FB_RXD_1_6 => open,
+  FB_RXD_1_5 => open,
+  FB_RXD_1_4 => open,
+  FB_RXD_1_3 => open,
+  FB_RXD_1_2 => open,
+  FB_RXD_1_1 => open,
+  FB_RXD_1_0 => open,
+
+  FF_TXD_1_20 => fpsc_vlo,
+  FF_TXD_1_8 => fpsc_vlo,
+  FB_RXD_1_20 => open,
+  FB_RXD_1_8 => open,
+
+  FF_TXD_1_21 => fpsc_vlo,
+  FF_TXD_1_9 => fpsc_vlo,
+
+  FF_TXD_1_22 => fpsc_vlo,
+  FF_TXD_1_10 => fpsc_vlo,
+  FF_TXD_1_23 => fpsc_vlo,
+  FF_TXD_1_11 => fpsc_vlo,
+
+  FB_RXD_1_21 => open,
+  FB_RXD_1_9 => open,
+
+  FB_RXD_1_22 => open,
+  FB_RXD_1_10 => open,
+
+  FB_RXD_1_23 => open,
+  FB_RXD_1_11 => open,
+
+  FF_TXD_2_19 => fpsc_vlo,
+  FF_TXD_2_18 => fpsc_vlo,
+  FF_TXD_2_17 => fpsc_vlo,
+  FF_TXD_2_16 => fpsc_vlo,
+  FF_TXD_2_15 => fpsc_vlo,
+  FF_TXD_2_14 => fpsc_vlo,
+  FF_TXD_2_13 => fpsc_vlo,
+  FF_TXD_2_12 => fpsc_vlo,
+  FF_TXD_2_7 => fpsc_vlo,
+  FF_TXD_2_6 => fpsc_vlo,
+  FF_TXD_2_5 => fpsc_vlo,
+  FF_TXD_2_4 => fpsc_vlo,
+  FF_TXD_2_3 => fpsc_vlo,
+  FF_TXD_2_2 => fpsc_vlo,
+  FF_TXD_2_1 => fpsc_vlo,
+  FF_TXD_2_0 => fpsc_vlo,
+  FB_RXD_2_19 => open,
+  FB_RXD_2_18 => open,
+  FB_RXD_2_17 => open,
+  FB_RXD_2_16 => open,
+  FB_RXD_2_15 => open,
+  FB_RXD_2_14 => open,
+  FB_RXD_2_13 => open,
+  FB_RXD_2_12 => open,
+  FB_RXD_2_7 => open,
+  FB_RXD_2_6 => open,
+  FB_RXD_2_5 => open,
+  FB_RXD_2_4 => open,
+  FB_RXD_2_3 => open,
+  FB_RXD_2_2 => open,
+  FB_RXD_2_1 => open,
+  FB_RXD_2_0 => open,
+
+  FF_TXD_2_20 => fpsc_vlo,
+  FF_TXD_2_8 => fpsc_vlo,
+  FB_RXD_2_20 => open,
+  FB_RXD_2_8 => open,
+
+  FF_TXD_2_21 => fpsc_vlo,
+  FF_TXD_2_9 => fpsc_vlo,
+
+  FF_TXD_2_22 => fpsc_vlo,
+  FF_TXD_2_10 => fpsc_vlo,
+  FF_TXD_2_23 => fpsc_vlo,
+  FF_TXD_2_11 => fpsc_vlo,
+
+  FB_RXD_2_21 => open,
+  FB_RXD_2_9 => open,
+
+  FB_RXD_2_22 => open,
+  FB_RXD_2_10 => open,
+
+  FB_RXD_2_23 => open,
+  FB_RXD_2_11 => open,
+
+  FF_TXD_3_19 => fpsc_vlo,
+  FF_TXD_3_18 => fpsc_vlo,
+  FF_TXD_3_17 => fpsc_vlo,
+  FF_TXD_3_16 => fpsc_vlo,
+  FF_TXD_3_15 => fpsc_vlo,
+  FF_TXD_3_14 => fpsc_vlo,
+  FF_TXD_3_13 => fpsc_vlo,
+  FF_TXD_3_12 => fpsc_vlo,
+  FF_TXD_3_7 => fpsc_vlo,
+  FF_TXD_3_6 => fpsc_vlo,
+  FF_TXD_3_5 => fpsc_vlo,
+  FF_TXD_3_4 => fpsc_vlo,
+  FF_TXD_3_3 => fpsc_vlo,
+  FF_TXD_3_2 => fpsc_vlo,
+  FF_TXD_3_1 => fpsc_vlo,
+  FF_TXD_3_0 => fpsc_vlo,
+  FB_RXD_3_19 => open,
+  FB_RXD_3_18 => open,
+  FB_RXD_3_17 => open,
+  FB_RXD_3_16 => open,
+  FB_RXD_3_15 => open,
+  FB_RXD_3_14 => open,
+  FB_RXD_3_13 => open,
+  FB_RXD_3_12 => open,
+  FB_RXD_3_7 => open,
+  FB_RXD_3_6 => open,
+  FB_RXD_3_5 => open,
+  FB_RXD_3_4 => open,
+  FB_RXD_3_3 => open,
+  FB_RXD_3_2 => open,
+  FB_RXD_3_1 => open,
+  FB_RXD_3_0 => open,
+
+  FF_TXD_3_20 => fpsc_vlo,
+  FF_TXD_3_8 => fpsc_vlo,
+  FB_RXD_3_20 => open,
+  FB_RXD_3_8 => open,
+
+  FF_TXD_3_21 => fpsc_vlo,
+  FF_TXD_3_9 => fpsc_vlo,
+
+  FF_TXD_3_22 => fpsc_vlo,
+  FF_TXD_3_10 => fpsc_vlo,
+  FF_TXD_3_23 => fpsc_vlo,
+  FF_TXD_3_11 => fpsc_vlo,
+
+  FB_RXD_3_21 => open,
+  FB_RXD_3_9 => open,
+
+  FB_RXD_3_22 => open,
+  FB_RXD_3_10 => open,
+
+  FB_RXD_3_23 => open,
+  FB_RXD_3_11 => open,
+
+  HDINP0 => hdinp_0,
+  HDINN0 => hdinn_0,
+  HDOUTP0 => hdoutp_0,
+  HDOUTN0 => hdoutn_0,
+  FF_SYSCLK0 => ref_0_sclk,
+  FF_RXCLK0 => open,
+  FFC_LANE_TX_RST0 => tx_rst_0,
+  FFC_LANE_RX_RST0 => rx_rst_0,
+  FF_TCLK0 => tclk_0,
+  FF_RCLK0 => rclk_0,
+  HDINP1 => fpsc_vlo,
+  HDINN1 => fpsc_vlo,
+  HDOUTP1 => open,
+  HDOUTN1 => open,
+  FF_SYSCLK1 => open,
+  FF_RXCLK1 => open,
+  FFC_LANE_TX_RST1 => fpsc_vlo,
+  FFC_LANE_RX_RST1 => fpsc_vlo,
+  FF_TCLK1 => fpsc_vlo,
+  FF_RCLK1 => fpsc_vlo,
+  HDINP2 => fpsc_vlo,
+  HDINN2 => fpsc_vlo,
+  HDOUTP2 => open,
+  HDOUTN2 => open,
+  FF_SYSCLK2 => open,
+  FF_RXCLK2 => open,
+  FFC_LANE_TX_RST2 => fpsc_vlo,
+  FFC_LANE_RX_RST2 => fpsc_vlo,
+  FF_TCLK2 => fpsc_vlo,
+  FF_RCLK2 => fpsc_vlo,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  HDOUTP3 => open,
+  HDOUTN3 => open,
+  FF_SYSCLK3 => open,
+  FF_RXCLK3 => open,
+  FFC_LANE_TX_RST3 => fpsc_vlo,
+  FFC_LANE_RX_RST3 => fpsc_vlo,
+  FF_TCLK3 => fpsc_vlo,
+  FF_RCLK3 => fpsc_vlo,
+
+  FFC_PCIE_EI_EN_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCIE_TX_0 => fpsc_vlo,
+  FFC_PCIE_RX_0 => fpsc_vlo,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFC_PCIE_EI_EN_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCIE_TX_1 => fpsc_vlo,
+  FFC_PCIE_RX_1 => fpsc_vlo,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFC_PCIE_EI_EN_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCIE_TX_2 => fpsc_vlo,
+  FFC_PCIE_RX_2 => fpsc_vlo,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFC_PCIE_EI_EN_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCIE_TX_3 => fpsc_vlo,
+  FFC_PCIE_RX_3 => fpsc_vlo,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+
+  FFC_SD_0 => fpsc_vlo,
+  FFC_SD_1 => fpsc_vlo,
+  FFC_SD_2 => fpsc_vlo,
+  FFC_SD_3 => fpsc_vlo,
+
+  FFC_EN_CGA_0 => fpsc_vlo,
+  FFC_EN_CGA_1 => fpsc_vlo,
+  FFC_EN_CGA_2 => fpsc_vlo,
+  FFC_EN_CGA_3 => fpsc_vlo,
+
+  FFC_ALIGN_EN_0 => fpsc_vlo,
+  FFC_ALIGN_EN_1 => fpsc_vlo,
+  FFC_ALIGN_EN_2 => fpsc_vlo,
+  FFC_ALIGN_EN_3 => fpsc_vlo,
+
+  FFC_FB_LB_0 => fpsc_vlo,
+  FFC_FB_LB_1 => fpsc_vlo,
+  FFC_FB_LB_2 => fpsc_vlo,
+  FFC_FB_LB_3 => fpsc_vlo,
+
+  FFS_LS_STATUS_0 => open,
+  FFS_LS_STATUS_1 => open,
+  FFS_LS_STATUS_2 => open,
+  FFS_LS_STATUS_3 => open,
+
+  FFS_CC_ORUN_0 => open,
+  FFS_CC_URUN_0 => open,
+  FFS_CC_ORUN_1 => open,
+  FFS_CC_URUN_1 => open,
+  FFS_CC_ORUN_2 => open,
+  FFS_CC_URUN_2 => open,
+  FFS_CC_ORUN_3 => open,
+  FFS_CC_URUN_3 => open,
+
+  FFC_AB_RESET => fpsc_vlo,
+
+  FFS_AB_STATUS => open,
+  FFS_AB_ALIGNED => open,
+  FFS_AB_FAILED => open,
+
+  FFC_CD_RESET => fpsc_vlo,
+  FFS_CD_STATUS => open,
+
+  FFS_CD_ALIGNED => open,
+  FFS_CD_FAILED => open,
+  BS4PAD_0 => open,
+  BS4PAD_1 => open,
+  BS4PAD_2 => open,
+  BS4PAD_3 => open,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  TCK_FMAC => open,
+  TCK_FMACP => fpsc_vlo,
+  FF_SYSCLK_P1 => ref_pclk,
+  FF_RXCLK_P1 => open,
+  FF_RXCLK_P2 => open,
+  FFC_QUAD_RST => quad_rst,
+  FFS_RLOS_LO0 => open,
+  FFS_RLOS_LO1 => open,
+  FFS_RLOS_LO2 => open,
+  FFS_RLOS_LO3 => open,
+  COUT_21 => open,
+  COUT_20 => open,
+  COUT_19 => open,
+  COUT_18 => open,
+  COUT_17 => open,
+  COUT_16 => open,
+  COUT_15 => open,
+  COUT_14 => open,
+  COUT_13 => open,
+  COUT_12 => open,
+  COUT_11 => open,
+  COUT_10 => open,
+  COUT_9 => open,
+  COUT_8 => open,
+  COUT_7 => open,
+  COUT_6 => open,
+  COUT_5 => open,
+  COUT_4 => open,
+  COUT_3 => open,
+  COUT_2 => open,
+  COUT_1 => open,
+  COUT_0 => open,
+  CIN_12 => fpsc_vlo,
+  CIN_11 => fpsc_vlo,
+  CIN_10 => fpsc_vlo,
+  CIN_9 => fpsc_vlo,
+  CIN_8 => fpsc_vlo,
+  CIN_7 => fpsc_vlo,
+  CIN_6 => fpsc_vlo,
+  CIN_5 => fpsc_vlo,
+  CIN_4 => fpsc_vlo,
+  CIN_3 => fpsc_vlo,
+  CIN_2 => fpsc_vlo,
+  CIN_1 => fpsc_vlo,
+  CIN_0 => fpsc_vlo,
+  TESTCLK_MACO => fpsc_vlo,
+  FFC_MACRO_RST => serdes_rst);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+  
+end trb_net16_med_scm_scp_gbe_0_arch ;

diff --git a/pinout/TRB_HUB2_FPGA1.lpf b/pinout/TRB_HUB2_FPGA1.lpf
index ce6eeba5b5c020ce1ad00e988e47519825d9175c..d4c1c889f81ddc76ee2e33923018a4b31b6024b1 100755 (executable)
--- a/pinout/TRB_HUB2_FPGA1.lpf
+++ b/pinout/TRB_HUB2_FPGA1.lpf
@@ -420,32 +420,32 @@ BLOCK ASYNCPATHS ;
 # Test Connectors\r
 # 0-10 on JTESTCON1, 11-26 on JTESTCON2\r
 #########################################\r
-#   LOCATE COMP  "TEST1_0"       SITE "AE13";\r
-#   LOCATE COMP  "TEST1_1"       SITE "AD14";\r
-#   LOCATE COMP  "TEST1_2"       SITE "AE15";\r
-#   LOCATE COMP  "TEST1_3"       SITE "AF15";\r
-#   LOCATE COMP  "TEST1_4"       SITE "AH14";\r
-#   LOCATE COMP  "TEST1_5"       SITE "AG15";\r
-#   LOCATE COMP  "TEST1_6"       SITE "AF16";\r
-#   LOCATE COMP  "TEST1_7"       SITE "AH15";\r
-#   LOCATE COMP  "TEST1_8"       SITE "AC16";\r
-#   LOCATE COMP  "TEST1_9"       SITE "AE16";\r
-#   LOCATE COMP  "TEST1_10"      SITE "AK15";\r
-#   LOCATE COMP  "TEST1_11"      SITE "AK16";\r
-#   LOCATE COMP  "TEST1_12"      SITE "AJ16";\r
-#   LOCATE COMP  "TEST1_13"      SITE "E15";\r
-#   LOCATE COMP  "TEST1_14"      SITE "E18";\r
-#   LOCATE COMP  "TEST1_15"      SITE "D18";\r
-#   LOCATE COMP  "TEST1_16"      SITE "C17";\r
-#   LOCATE COMP  "TEST1_17"      SITE "J16";\r
-#   LOCATE COMP  "TEST1_18"      SITE "G15";\r
-#   LOCATE COMP  "TEST1_19"      SITE "C16";\r
-#   LOCATE COMP  "TEST1_20"      SITE "D16";\r
-#   LOCATE COMP  "TEST1_21"      SITE "J15";\r
-#   LOCATE COMP  "TEST1_22"      SITE "H15";\r
-#   LOCATE COMP  "TEST1_23"      SITE "A15";\r
-#   LOCATE COMP  "TEST1_24"      SITE "B15";\r
-#   LOCATE COMP  "TEST1_25"      SITE "F15";\r
-#   LOCATE COMP  "TEST1_26"      SITE "E16";\r
-#   DEFINE PORT GROUP "test1_group" "TEST1*" ;\r
-#   IOBUF GROUP "test1_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
+  LOCATE COMP  "TEST1_0"         SITE "AE13";\r
+  LOCATE COMP  "TEST1_1"         SITE "AD14";\r
+  LOCATE COMP  "TEST1_2"         SITE "AE15";\r
+  LOCATE COMP  "TEST1_3"         SITE "AF15";\r
+  LOCATE COMP  "TEST1_4"         SITE "AH14";\r
+  LOCATE COMP  "TEST1_5"         SITE "AG15";\r
+  LOCATE COMP  "TEST1_6"         SITE "AF16";\r
+  LOCATE COMP  "TEST1_7"         SITE "AH15";\r
+  LOCATE COMP  "TEST1_8"         SITE "AC16";\r
+  LOCATE COMP  "TEST1_9"         SITE "AE16";\r
+  LOCATE COMP  "TEST1_10"        SITE "AK15";\r
+  LOCATE COMP  "TEST1_11"        SITE "AK16";\r
+  LOCATE COMP  "TEST1_12"        SITE "AJ16";\r
+  LOCATE COMP  "TEST1_13"        SITE "E15";\r
+  LOCATE COMP  "TEST1_14"        SITE "E18";\r
+  LOCATE COMP  "TEST1_15"        SITE "D18";\r
+  LOCATE COMP  "TEST1_16"        SITE "C17";\r
+  LOCATE COMP  "TEST1_17"        SITE "J16";\r
+  LOCATE COMP  "TEST1_18"        SITE "G15";\r
+  LOCATE COMP  "TEST1_19"        SITE "C16";\r
+  LOCATE COMP  "TEST1_20"        SITE "D16";\r
+  LOCATE COMP  "TEST1_21"        SITE "J15";\r
+  LOCATE COMP  "TEST1_22"        SITE "H15";\r
+  LOCATE COMP  "TEST1_23"        SITE "A15";\r
+  LOCATE COMP  "TEST1_24"        SITE "B15";\r
+  LOCATE COMP  "TEST1_25"        SITE "F15";\r
+  LOCATE COMP  "TEST1_26"        SITE "E16";\r
+  DEFINE PORT GROUP "test1_group" "TEST1*" ;\r
+  IOBUF GROUP "test1_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r

diff --git a/pinout/mdc_oep3.lpf b/pinout/mdc_oep3.lpf
index 54338a21280a278eaaa76de65a15a4405d80c93b..ee10ef8e6dd397385291a7b061333a981c46f602 100644 (file)
--- a/pinout/mdc_oep3.lpf
+++ b/pinout/mdc_oep3.lpf
@@ -109,41 +109,44 @@ IOBUF  PORT  "COM_STOP_P" IO_TYPE=LVDS25;
 
   LOCATE COMP  "CMS"        SITE "R2";
   LOCATE COMP  "GDE"        SITE "F16";
-# LOCATE COMP  "INITN"      SITE "H11";
-  LOCATE COMP  "MODD"        SITE "P3";
-  IOBUF PORT   "MODD" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
-
-# LOCATE COMP  "PROGRAMN"   SITE "N12";
+  LOCATE COMP  "MODD"       SITE "P3";
   LOCATE COMP  "RDYI"       SITE "P16";
   LOCATE COMP  "RES"        SITE "P4";
-  IOBUF PORT   "RES" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
   LOCATE COMP  "TACK"       SITE "P14";
-  IOBUF PORT   "TACK" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  LOCATE COMP  "TAOD"       SITE "T5";
+  LOCATE COMP  "TDST"       SITE "R16";
+  LOCATE COMP  "TOK"        SITE "P2";
+  LOCATE COMP  "TRDYO"      SITE "P15";
+  LOCATE COMP  "TRSV"       SITE "T4";
+  LOCATE COMP  "WRM"        SITE "R15";
+
+  IOBUF PORT   "CMS"   IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "GDE"   IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "MODD"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "RDYI"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "RES"   IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TACK"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TAOD"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TDST"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TOK"   IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TRDYO" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "TRSV"  IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+  IOBUF PORT   "WRM"   IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
+# LOCATE COMP  "INITN"      SITE "H11";
+# LOCATE COMP  "PROGRAMN"   SITE "N12";
 # LOCATE COMP  "TADS_0"     SITE "N9";
 # LOCATE COMP  "TADS_1"     SITE "P10";
-  LOCATE COMP  "TAOD"       SITE "T5";
-  IOBUF PORT   "TAOD" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
 # LOCATE COMP  "TCDE_0"     SITE "R13";
 # LOCATE COMP  "TDRA"       SITE "N10";
 # LOCATE COMP  "TDRB"       SITE "T14";
 # LOCATE COMP  "TDRE"       SITE "R11";
-  LOCATE COMP  "TDST"       SITE "R16";
-  IOBUF PORT   "TDST" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
 # LOCATE COMP  "TENB"       SITE "T11";
 # LOCATE COMP  "TENR"       SITE "T13";
-  LOCATE COMP  "TOK"        SITE "P2";
-  IOBUF PORT   "TOK" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
-
 # LOCATE COMP  "TOR"        SITE "R14";
-
-  LOCATE COMP  "TRDYO"      SITE "P15";
 # LOCATE COMP  "TREN"       SITE "T12";
-  LOCATE COMP  "TRSV"       SITE "T4";
-  LOCATE COMP  "WRM"        SITE "R15";
-  IOBUF PORT   "WRM" IO_TYPE=LVTTL33 PULLMODE=DOWN ;
-
-#  LOCATE COMP  "ADI_0"      SITE "L9";
-#  LOCATE COMP  "ADI_1"      SITE "M9";
+# LOCATE COMP  "ADI_0"      SITE "L9";
+# LOCATE COMP  "ADI_1"      SITE "M9";
 
 ################################################################
 #Logic Analyzer Connection (Jan)

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 1a369ec07bae75ca3c4b17e03d203d33eeed13ca..5892ab47605559d2a5f89b6753f837acaea1b436 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -28,7 +28,7 @@ entity trb_net16_hub_base is
     CLOCK_FREQUENCY         : integer range 1 to 200 := 100;
     USE_ONEWIRE             : integer range 0 to 2 := c_YES;
   --media interfaces
-    MII_NUMBER              : integer range 2 to c_MAX_MII_PER_HUB := 12;
+    MII_NUMBER              : integer range 2 to c_MAX_MII_PER_HUB := 4;
     MII_IBUF_DEPTH          : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
     MII_IS_UPLINK           : hub_mii_config_t := (others => c_YES);
     MII_IS_DOWNLINK         : hub_mii_config_t := (others => c_YES);
@@ -97,6 +97,8 @@ entity trb_net16_hub_base is
     MPLEX_STAT                   : out std_logic_vector (MII_NUMBER*32-1 downto 0);
     STAT_REGS                    : out std_logic_vector (16*32-1 downto 0);  --Status of custom STAT regs
     STAT_CTRL_REGS               : out std_logic_vector (8*32-1 downto 0);  --Status of custom CTRL regs
+    IOBUF_STAT_INIT_OBUF_DEBUG   : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
+    IOBUF_STAT_REPLY_OBUF_DEBUG  : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
 
     --Debugging registers
     STAT_DEBUG                   : out std_logic_vector (31 downto 0);      --free status regs for debugging
@@ -209,8 +211,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal IOBUF_STAT_GEN               : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
   signal IOBUF_IBUF_BUFFER            : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
   signal IOBUF_CTRL_GEN               : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
-  signal IOBUF_STAT_INIT_OBUF_DEBUG   : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
-  signal IOBUF_STAT_REPLY_OBUF_DEBUG  : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
   signal IOBUF_STAT_DATA_COUNTER      : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
 
   signal resync : std_logic_vector(MII_NUMBER-1 downto 0);
@@ -300,6 +300,9 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
 
   signal mii_error               : std_logic_vector(31 downto 0);
 
+  signal iobuf_stat_init_obuf_debug_i   : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
+  signal iobuf_stat_reply_obuf_debug_i  : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
+
   attribute syn_preserve : boolean;
   attribute syn_keep : boolean;
   attribute syn_preserve of m_DATA_IN : signal is true;
@@ -308,8 +311,19 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   attribute syn_keep of m_DATAREADY_IN : signal is true;
   attribute syn_preserve of m_PACKET_NUM_IN : signal is true;
   attribute syn_keep of m_PACKET_NUM_IN : signal is true;
+
   attribute syn_preserve of m_PACKET_NUM_OUT : signal is true;
   attribute syn_keep of m_PACKET_NUM_OUT : signal is true;
+  attribute syn_preserve of m_DATA_OUT : signal is true;
+  attribute syn_keep of m_DATA_OUT : signal is true;
+  attribute syn_preserve of m_DATAREADY_OUT : signal is true;
+  attribute syn_keep of m_DATAREADY_OUT : signal is true;
+
+  attribute syn_preserve of m_READ_OUT : signal is true;
+  attribute syn_keep of m_READ_OUT : signal is true;
+  attribute syn_preserve of m_READ_IN : signal is true;
+  attribute syn_keep of m_READ_IN : signal is true;
+
   attribute syn_keep of reset_i : signal is true;
 
   attribute syn_hier : string;
@@ -425,7 +439,8 @@ MED_DATA_OUT       <= buf_MED_DATA_OUT;
             IBUF_DEPTH =>  calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
             USE_CHECKSUM          => USE_CHECKSUM(k),
             IBUF_SECURE_MODE      => IBUF_SECURE_MODE,
-            SBUF_VERSION          => std_SBUF_VERSION,
+            SBUF_VERSION          => 0,
+            SBUF_VERSION_OBUF     => 5,
             OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
             USE_ACKNOWLEDGE       => cfg_USE_ACKNOWLEDGE(k),
             USE_VENDOR_CORES      => USE_VENDOR_CORES,
@@ -480,8 +495,8 @@ MED_DATA_OUT       <= buf_MED_DATA_OUT;
             CTRL_OBUF_settings(15 downto  4) => (others => '0'),
             CTRL_OBUF_settings(19 downto 16) => HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
             CTRL_OBUF_settings(31 downto 20) => (others => '0'),
-            STAT_INIT_OBUF_DEBUG   => IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32),
-            STAT_REPLY_OBUF_DEBUG  => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32),
+            STAT_INIT_OBUF_DEBUG   => iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32),
+            STAT_REPLY_OBUF_DEBUG  => iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32),
             TIMER_TICKS_IN(0)      => timer_us_tick,
             TIMER_TICKS_IN(1)      => timer_ms_tick,
             CTRL_STAT              => iobuf_ctrl_stat(k*16+15 downto k*16)
@@ -499,8 +514,8 @@ MED_DATA_OUT       <= buf_MED_DATA_OUT;
         iobuf_stat_gen((i+1)*32-1 downto i*32) <= (others => '0');
         IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
         IOBUF_CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0');
-        IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
-        IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
+        iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0');
+        iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0');
 
 
         IOBUF : trb_net16_term_buf
@@ -1380,10 +1395,10 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
     end process;
 
   gen_ack_waiting : for i in 0 to MII_NUMBER-1 generate
-    HC_STAT_ack_waiting(i)     <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+0)*32+20);
-    HC_STAT_ack_waiting(32+i)  <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+1)*32+20);
-    HC_STAT_ack_waiting(64+i)  <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+2)*32+20);
-    HC_STAT_ack_waiting(96+i)  <= IOBUF_STAT_INIT_OBUF_DEBUG((i*4+3)*32+20);
+    HC_STAT_ack_waiting(i)     <= iobuf_stat_init_obuf_debug_i((i*4+0)*32+20);
+    HC_STAT_ack_waiting(32+i)  <= iobuf_stat_init_obuf_debug_i((i*4+1)*32+20);
+    HC_STAT_ack_waiting(64+i)  <= iobuf_stat_init_obuf_debug_i((i*4+2)*32+20);
+    HC_STAT_ack_waiting(96+i)  <= iobuf_stat_init_obuf_debug_i((i*4+3)*32+20);
   end generate;
 
   HC_STAT_ack_waiting( 0+31 downto  0+MII_NUMBER) <= (others => '0');
@@ -1408,7 +1423,8 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
   buf_STAT_DEBUG(31 downto 0) <= (others => '0');
 
 
-
+  IOBUF_STAT_INIT_OBUF_DEBUG <= iobuf_stat_init_obuf_debug_i;
+  IOBUF_STAT_REPLY_OBUF_DEBUG <= iobuf_stat_reply_obuf_debug_i;
   IOBUF_CTRL_GEN <= (others => '0');
   --map regio registers to stat & ctrl outputs
   COMMON_CTRL_REGS      <= HC_COMMON_CTRL_REGS;

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index 4d970f03d9b90f7338859af8c7ca48bc8980d3fd..d27748e41c227d2d790232ae50972646b0e36f5d 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -171,7 +171,8 @@ package trb_net16_hub_func is
     MPLEX_STAT            : out std_logic_vector (MII_NUMBER*32-1 downto 0);
     STAT_REGS             : out std_logic_vector (8*32-1 downto 0);  --Status of custom STAT regs
     STAT_CTRL_REGS        : out std_logic_vector (8*32-1 downto 0);  --Status of custom CTRL regs
-
+    IOBUF_STAT_INIT_OBUF_DEBUG   : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
+    IOBUF_STAT_REPLY_OBUF_DEBUG  : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
 
     --Debugging registers
     STAT_DEBUG            : out std_logic_vector (31 downto 0);      --free status regs for debugging

diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd
index a64cddda864683a2cf7acccd87b961600ae5a2c4..1295b39efb254a8251c56b671840775b3f825cb0 100644 (file)
--- a/trb_net16_iobuf.vhd
+++ b/trb_net16_iobuf.vhd
@@ -14,6 +14,7 @@ entity trb_net16_iobuf is
     IBUF_DEPTH            : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
     IBUF_SECURE_MODE      : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
     SBUF_VERSION          : integer range 0 to 1 := std_SBUF_VERSION;
+    SBUF_VERSION_OBUF     : integer range 0 to 5 := std_SBUF_VERSION;
     OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
     USE_ACKNOWLEDGE       : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
     USE_CHECKSUM          : integer range 0 to 1 := c_YES;
@@ -176,7 +177,7 @@ begin
         DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH,
         USE_ACKNOWLEDGE  => USE_ACKNOWLEDGE,
         USE_CHECKSUM     => USE_CHECKSUM,
-        SBUF_VERSION     => SBUF_VERSION
+        SBUF_VERSION     => SBUF_VERSION_OBUF
         )
       port map (
         CLK       => CLK,
@@ -228,7 +229,7 @@ begin
         DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH,
         USE_ACKNOWLEDGE  => USE_ACKNOWLEDGE,
         USE_CHECKSUM     => USE_CHECKSUM,
-        SBUF_VERSION     => SBUF_VERSION
+        SBUF_VERSION     => SBUF_VERSION_OBUF
         )
       port map (
         CLK       => CLK,

diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd
index 2d17da227023092935a56631f7b48c4ceb60ffb9..0694e00d29adba606bf5b782ee096a9d17d4a8e2 100644 (file)
--- a/trb_net16_obuf.vhd
+++ b/trb_net16_obuf.vhd
@@ -12,7 +12,7 @@ entity trb_net16_obuf is
     USE_CHECKSUM     : integer range 0 to 1 := c_YES;
     DATA_COUNT_WIDTH : integer range 1 to 7 := std_DATA_COUNT_WIDTH;
                            -- max used buffer size is 2**DATA_COUNT_WIDTH.
-    SBUF_VERSION     : integer range 0 to 4 := std_SBUF_VERSION
+    SBUF_VERSION     : integer range 0 to 5 := std_SBUF_VERSION
     );
   port(
     --  Misc
@@ -183,6 +183,7 @@ begin
       SYN_DATA_OUT => MED_DATA_OUT,
       SYN_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT,
       SYN_READ_IN => MED_READ_IN,
+      DEBUG_OUT   => STAT_DEBUG(15 downto 0),
       STAT_BUFFER => sbuf_status
       );
 
@@ -526,18 +527,11 @@ begin
 ---------------------------------------------------------------------
 -- Debug output
 ---------------------------------------------------------------------
-  STAT_DEBUG(0)    <= '0'; --comb_dataready;
-  STAT_DEBUG(3 downto 1) <= "000"; --transfer_counter;
-  STAT_DEBUG(4) <= '0'; --buf_MED_DATAREADY_OUT;
-  STAT_DEBUG(7 downto 5) <= "000"; --buf_MED_PACKET_NUM_OUT;
-  STAT_DEBUG(8) <= '0'; --sbuf_free;
-  STAT_DEBUG(9) <= '0'; --comb_next_read;
-  STAT_DEBUG(10) <= '0'; --SEND_ACK_IN;
-  STAT_DEBUG(11) <= '0'; --reg_SEND_ACK_IN;
-  STAT_DEBUG(12) <= '0'; --RESET;
-  STAT_DEBUG(14 downto 13) <= std_logic_vector(TRANSMITTED_BUFFERS);
-  STAT_DEBUG(17 downto 15) <= REC_BUFFER_SIZE_IN(2 downto 0);
+
+  STAT_DEBUG(17 downto 16) <= "00";
   STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0);  --used in hub monitoring!
-  STAT_DEBUG(20) <= wait_for_ack_timeout; --used in hub monitoring
-  STAT_DEBUG(31 downto 21) <= (others => '0');
+  STAT_DEBUG(20) <= wait_for_ack_timeout;                    --used in hub monitoring
+  STAT_DEBUG(22 downto 21) <= std_logic_vector(TRANSMITTED_BUFFERS);
+  STAT_DEBUG(25 downto 23) <= REC_BUFFER_SIZE_IN(2 downto 0);
+  STAT_DEBUG(31 downto 26) <= (others => '0');
 end architecture;

diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd
index 74e726ecb4df2e62b4c952fcb2e2278f1996ba6e..928399b89de8b3520e5fb1cb3e5f8e35409a72f7 100644 (file)
--- a/trb_net16_sbuf.vhd
+++ b/trb_net16_sbuf.vhd
@@ -46,6 +46,7 @@ entity trb_net16_sbuf is
     SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1  downto 0);
     SYN_READ_IN       : in  STD_LOGIC;
     -- Status and control port
+    DEBUG_OUT         : out std_logic_vector(15 downto 0);
     STAT_BUFFER       : out STD_LOGIC
     );
 end entity;
@@ -53,6 +54,7 @@ end entity;
 architecture trb_net16_sbuf_arch of trb_net16_sbuf is
 
 signal comb_in, syn_out : std_logic_vector (c_DATA_WIDTH + c_NUM_WIDTH - 1 downto 0);
+signal tmp : std_logic;
 
 begin
   comb_in(c_DATA_WIDTH - 1 downto 0) <= COMB_DATA_IN;
@@ -153,6 +155,10 @@ begin
         SYN_DATAREADY_OUT  => SYN_DATAREADY_OUT,
         SYN_DATA_OUT       => syn_out,
         SYN_READ_IN        => SYN_READ_IN,
+        DEBUG(6 downto 0)  => DEBUG_OUT(6 downto 0),
+        DEBUG(7)           => tmp,
+        DEBUG_WCNT         => DEBUG_OUT(11 downto 7),
+        DEBUG_BSM          => DEBUG_OUT(15 downto 12),
         STAT_BUFFER        => STAT_BUFFER
         );
   end generate;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 119aaeeb514e7a38f966838da9f550e796bd325a..6c0ac5016886137014ca126e75ad21ebcffdf48d 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -1141,7 +1141,8 @@ package trb_net_components is
     generic (
       IBUF_DEPTH            : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
       IBUF_SECURE_MODE      : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
-      SBUF_VERSION          : integer range 0 to 5 := std_SBUF_VERSION;
+      SBUF_VERSION          : integer range 0 to 1 := std_SBUF_VERSION;
+      SBUF_VERSION_OBUF     : integer range 0 to 5 := std_SBUF_VERSION;
       OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
       USE_ACKNOWLEDGE       : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
       USE_CHECKSUM          : integer range 0 to 1 := c_YES;
@@ -2232,6 +2233,7 @@ package trb_net_components is
       SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
       SYN_READ_IN       : in  STD_LOGIC;
       -- Status and control port
+      DEBUG_OUT          : out std_logic_vector(15 downto 0);
       STAT_BUFFER       : out STD_LOGIC
       );
   end component;
@@ -2328,20 +2330,23 @@ package trb_net_components is
   component trb_net_sbuf5 is
     port(
       --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
+      CLK                : in  std_logic;
+      RESET              : in  std_logic;
+      CLK_EN             : in  std_logic;
       -- input
-      COMB_DATAREADY_IN  : in  STD_LOGIC;
-      COMB_next_READ_OUT : out STD_LOGIC;
-      COMB_DATA_IN       : in  STD_LOGIC_VECTOR (18 downto 0);
+      COMB_DATAREADY_IN  : in  std_logic;
+      COMB_next_READ_OUT : out std_logic;
+      COMB_DATA_IN       : in  std_logic_vector(18 downto 0);
       -- output
-      SYN_DATAREADY_OUT  : out STD_LOGIC;
-      SYN_DATA_OUT       : out STD_LOGIC_VECTOR (18 downto 0); -- Data word
-      SYN_READ_IN        : in  STD_LOGIC;
+      SYN_DATAREADY_OUT  : out std_logic;
+      SYN_DATA_OUT       : out std_logic_vector(18 downto 0); -- Data word
+      SYN_READ_IN        : in  std_logic;
       -- Status and control port
-      STAT_BUFFER        : out STD_LOGIC
-      );
+      DEBUG              : out std_logic_vector(7 downto 0);
+      DEBUG_BSM          : out std_logic_vector(3 downto 0);
+      DEBUG_WCNT         : out std_logic_vector(4 downto 0);
+      STAT_BUFFER        : out std_logic
+    );
   end component;
 
   component slv_mac_memory is

diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd
index 2c65aed081df71d2cce93e6cd837ee7ddd190596..0624e0f15670d5bc49abaf880af55432dadf2c35 100644 (file)
--- a/trb_net_sbuf.vhd
+++ b/trb_net_sbuf.vhd
@@ -42,6 +42,7 @@ entity trb_net_sbuf is
     SYN_DATA_OUT       : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
     SYN_READ_IN        : in  STD_LOGIC;
     -- Status and control port
+    DEBUG_OUT          : out std_logic_vector(15 downto 0);
     STAT_BUFFER        : out STD_LOGIC
     );
 end trb_net_sbuf;

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index 75cc0f043f9c19f3dc115e5cda7fe2b93405c97c..bdccb2fd5f5a98a5d4d9f6aedb8cfede3fe684dc 100644 (file)
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -1,4 +1,4 @@
--- sbuf5: sends only full packets. \r
+-- sbuf5: sends only full packets.\r
 -- This version is optimized for safety, not speed.\r
 -- Speed can be gained by "looking ahead" on the write side of FIFO, especially by\r
 -- monitoring the comb_dataready_in signal to gain one clock cycle.\r
@@ -66,9 +66,9 @@ end component fifo_19x16_obuf;
 -- RD4 : third word output reg, fourth word prefetch, wait state for handshake of third data word\r
 -- RD5 : fourth word output reg, fifth word prefetch, wait state for handshake of forth data word\r
 --       => decision: continous data stream or stalling as FIFO runs empty!\r
--- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission \r
+-- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission\r
 --       if new data is available in FIFO\r
--- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word, \r
+-- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word,\r
 --       continue data stream or stall if for complete packet\r
 \r
 type STATES is (IDLE, RD1, RD2, RDI, RD3, RD4, RD5, RDO, RDW);\r
@@ -177,13 +177,13 @@ begin
        case CURRENT_STATE is\r
                when IDLE   =>  if( fifo_wcnt > 0 ) then\r
                                                        -- we have at least one data word in FIFO, so we prefetch it\r
-                                                       NEXT_STATE   <= RD1; \r
+                                                       NEXT_STATE   <= RD1;\r
                                                        fifo_rd_en_x <= '1';\r
                                                else\r
                                                        NEXT_STATE   <= IDLE;\r
                                                end if;\r
                when RD1    =>  if( fifo_wcnt > 0 ) then\r
-                                                       -- second data word is available in FIFO, so we prefetch it and \r
+                                                       -- second data word is available in FIFO, so we prefetch it and\r
                                                        -- forward the first word to the output register\r
                                                        NEXT_STATE   <= RD2;\r
                                                        fifo_rd_en_x <= '1';\r
@@ -226,7 +226,7 @@ begin
                                                        NEXT_STATE      <= RD4;\r
                                                end if;\r
                when RD5    =>  syn_dataready_x <= '1';\r
-                                               -- DANGER. This is the key state for decisions here. \r
+                                               -- DANGER. This is the key state for decisions here.\r
                                                -- There are many ways to do it the wrong way, depending on the FIFO fill level.\r
                                                if   ( (SYN_READ_IN = '1') and (fifo_wcnt < 2) ) then\r
                                                        -- fourth word of packet has been transfered, and FIFO has not seen any new packet word.\r
@@ -268,8 +268,8 @@ begin
                                                        update_x        <= '1';\r
                                                else\r
                                                        NEXT_STATE      <= RDW;\r
-                                                       syn_dataready_x <= '1'; \r
-                                               end if;                                         \r
+                                                       syn_dataready_x <= '1';\r
+                                               end if;\r
                when others =>  NEXT_STATE <= IDLE;\r
        end case;\r
 end process STATE_TRANSFORM;\r