signal word_count : integer range 0 to 31;
signal bit_count : integer range 0 to 31;
signal time_count : integer range 0 to 7;
+ signal readback : std_logic_vector(31 downto 0);
type fsm_t is (IDLE, WAIT_STATE, SET, FINISH);
signal fsm_state : fsm_t;
BUS_DATA_OUT <= ram(addr);
elsif BUS_ADDR_IN(0) = '1' then
BUS_DATA_OUT <= ctrl_reg;
+ elsif BUS_ADDR_IN(1) = '1' then
+ BUS_DATA_OUT <= readback;
else --if BUS_ADDR_IN(1) = '0' then
BUS_DATA_OUT(15 downto 0) <= chipselect_reg;
BUS_DATA_OUT(31 downto 16) <= x"0000";
end if;
else
fsm_state <= WAIT_STATE;
+ readback <= readback(30 downto 0) & SPI_SDI_IN;
end if;
when FINISH =>
if time_count = 0 and spi_sck = '0' then
time_count <= 7;
spi_sck <= not spi_sck;
+ readback <= readback(30 downto 0) & SPI_SDI_IN;
elsif time_count = 0 and spi_sck = '1' then
fsm_state <= IDLE;
else
signal recv_bit_ready, next_recv_bit_ready : std_logic;
signal output_tmp, next_output_tmp : std_logic;
signal word : std_logic_vector(15 downto 0);
- signal ram_addr : std_logic_vector(2 downto 0);
+ signal ram_addr : std_logic_vector(2 downto 0) := "000";
signal ram_wr : std_logic;
signal send_rom, next_send_rom : std_logic;
signal conv_temp, next_conv_temp : std_logic;