on the way...

diff --git a/special/clockbox.vhd b/special/clockbox.vhd
index 6c6f4d14b7e910acc0548c741a111a6188c2152c..596f1e4ab96df7812521aa577b5a708317c84158 100644 (file)
--- a/special/clockbox.vhd
+++ b/special/clockbox.vhd
@@ -23,12 +23,6 @@ architecture clockbox_arch of clockbox is
 -- state machine signals\r
 \r
 -- Signals\r
-  signal ping_i         : std_logic;\r
-  signal pong_i         : std_logic;\r
-  signal ping_q         : std_logic;\r
-  signal pong_q         : std_logic;\r
-  signal ping_qq        : std_logic;\r
-  signal pong_qq        : std_logic;\r
 \r
   attribute HGROUP : string;\r
   attribute BBOX   : string;\r
@@ -41,21 +35,20 @@ architecture clockbox_arch of clockbox is
   \r
 begin\r
 \r
----------------------------------------------------------------------------\r
--- we want all logic in here in one PFU (defined timing)!\r
----------------------------------------------------------------------------\r
+  THE_PING_POINT: entity clockpoint\r
+  port map(\r
+    SAMPLE_CLK    => SAMPLE_CLK,\r
+    DATA_IN       => PING_IN,\r
+    CLK_DATA      => CLK_PING,\r
+    DATA_OUT      => PING_OUT\r
+  );\r
 \r
-  ping_i  <= PING_IN when rising_edge(CLK_PING);\r
-  pong_i  <= PONG_IN when rising_edge(CLK_PONG);\r
-  ping_q  <= ping_i when rising_edge(SAMPLE_CLK);\r
-  pong_q  <= pong_i when rising_edge(SAMPLE_CLK);\r
-  ping_qq <= ping_q when rising_edge(SAMPLE_CLK);\r
-  pong_qq <= pong_q when rising_edge(SAMPLE_CLK);\r
-  \r
----------------------------------------------------------------------------\r
--- outputs\r
----------------------------------------------------------------------------\r
-  PING_OUT <= ping_qq;\r
-  PONG_OUT <= pong_qq;\r
+  THE_PONG_POINT: entity clockpoint\r
+  port map(\r
+    SAMPLE_CLK    => SAMPLE_CLK,\r
+    DATA_IN       => PONG_IN,\r
+    CLK_DATA      => CLK_PONG,\r
+    DATA_OUT      => PONG_OUT\r
+  );\r
 \r
 end architecture;\r

diff --git a/special/clockpoint.vhd b/special/clockpoint.vhd
new file mode 100644 (file)
index 0000000..3d5bf6f
--- /dev/null
+++ b/special/clockpoint.vhd
@@ -0,0 +1,51 @@
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity clockpoint is\r
+  port(\r
+    SAMPLE_CLK    : in  std_logic;\r
+    DATA_IN       : in  std_logic;\r
+    CLK_DATA      : in  std_logic;\r
+    DATA_OUT      : out std_logic\r
+  );\r
+end entity clockpoint;\r
+\r
+architecture clockpoint_arch of clockpoint is\r
+\r
+-- Components\r
+\r
+-- state machine signals\r
+\r
+-- Signals\r
+  signal data_i         : std_logic;\r
+  signal data_q         : std_logic;\r
+  signal data_qq        : std_logic;\r
+\r
+  attribute HGROUP : string;\r
+  attribute BBOX   : string;\r
+  attribute HGROUP of clockpoint_arch : architecture is "clockpoint_group";\r
+  attribute BBOX   of clockpoint_arch : architecture is "1,1";\r
+  attribute syn_sharing : string;\r
+  attribute syn_sharing of clockpoint_arch : architecture is "off";\r
+  attribute syn_hier : string;\r
+  attribute syn_hier of clockpoint_arch : architecture is "hard";\r
+  \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- we want all logic in here in one PFU (defined timing)!\r
+---------------------------------------------------------------------------\r
+\r
+  data_i  <= DATA_IN when rising_edge(CLK_DATA);\r
+  data_q  <= data_i when rising_edge(SAMPLE_CLK);\r
+  data_qq <= data_q when rising_edge(SAMPLE_CLK);\r
+  \r
+---------------------------------------------------------------------------\r
+-- outputs\r
+---------------------------------------------------------------------------\r
+  DATA_OUT <= data_qq;\r
+\r
+end architecture;\r