Move threshold FPGA design files to new vhdlbasics repository

diff --git a/thresholds/compile.pl b/thresholds/compile.pl
index 3dfb1e066f400e5989d33fe1563b26e2395d1d54..8a19aa687e9ce69f56c9c1ed9bf6f366dcc1b061 120000 (symlink)
--- a/thresholds/compile.pl
+++ b/thresholds/compile.pl
@@ -1 +1 @@
-/home/adrian/git/trb3sc/scripts/compile.pl
\ No newline at end of file
+../../trb3sc/scripts/compile.pl
\ No newline at end of file

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index 55e559c4c819a5decfa524088ca0aad3f47d132e..7b41ec9f8405a85752e54c54c2ea3c2897ff03b4 100644 (file)
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -4,23 +4,16 @@
 
 #project files
 
-#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
-
-#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
-#add file -vhdl -lib work "./test/machxo3lf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
 add_file -vhdl -lib work "../../logicbox/UFM_control/UFM_control.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/flash.vhd"
-
 
-#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
-#add_file -vhdl -lib work "cores/efb.vhd"
-add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
-add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+add_file -vhdl    -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
+add_file -vhdl    -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
 
 add_file -vhdl -lib work "thresholds.vhd"
 
@@ -43,7 +36,7 @@ set_option -technology MACHXO3LF
 #set_option -part LCMXO3LF_6900C
 #set_option -package BG256C
 set_option -part LCMXO3LF_4300E
-set_option -package UWG81
+set_option -package UWG81CTR
 set_option -speed_grade -5
 set_option -part_companion ""
 

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index 1f4d8e04622debc25da8419121633f8a4615f6fe..ac2b97d94342614ba2a934b1a18ae04c09bb1527 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -343,7 +343,8 @@ THE_SED : entity work.sedcheck
 ---------------------------------------------------------------------------        \r
 THE_PWM_GEN : entity work.pwm_generator\r
   generic map(\r
-    CHANNELS => 16\r
+    CHANNELS => 16,\r
+    DOWNSAMPLE => 16\r
     )\r
   port map(\r
     CLK        => clk_i,\r