+++ /dev/null
-<!DOCTYPE PLL>
-<lattice:project>
- <spirit:component>
- <spirit:vendor>LATTICE</spirit:vendor>
- <spirit:library>LOCAL</spirit:library>
- <spirit:name>PLL</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:fileSets>
- <spirit:fileset>
- <spirit:name>Diamond_Synthesis</spirit:name>
- <spirit:group>synthesis</spirit:group>
- </spirit:fileset>
- <spirit:fileset>
- <spirit:name>Diamond_Simulation</spirit:name>
- <spirit:group>simulation</spirit:group>
- </spirit:fileset>
- </spirit:fileSets>
- <spirit:componentGenerators/>
- <spirit:model>
- <spirit:views/>
- <spirit:ports>
- <spirit:port>
- <spirit:name>pll_in200_out100_CLKI</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKI</spirit:displayName>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKI</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>pll_in200_out100_CLKOP</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKOP</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKOP</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>pll_in200_out100_CLKOS</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKOS</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="exportFrom">pll_in200_out100.CLKOS</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>pll_in200_out100_LOCK</spirit:name>
- <spirit:displayName>pll_in200_out100_LOCK</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="exportFrom">pll_in200_out100.LOCK</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <lattice:device>LFE5UM-85F-8MG285C</lattice:device>
- <lattice:synthesis>synplify</lattice:synthesis>
- <lattice:date>2015-03-17.15:29:30</lattice:date>
- <lattice:modified>2015-03-17.15:44:52</lattice:modified>
- <lattice:diamond>3.4.0.80</lattice:diamond>
- <lattice:language>VHDL</lattice:language>
- <lattice:attributes>
- <lattice:attribute lattice:name="AddComponent">true</lattice:attribute>
- <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConnect">true</lattice:attribute>
- <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
- <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
- <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
- </lattice:attributes>
- <lattice:elements/>
- <lattice:lpc/>
- <lattice:groups/>
- </spirit:vendorExtensions>
- </spirit:component>
- <spirit:design>
- <spirit:vendor>LATTICE</spirit:vendor>
- <spirit:library>LOCAL</spirit:library>
- <spirit:name>PLL</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>pll_in200_out100</spirit:instanceName>
- <spirit:componentRef>
- <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
- <spirit:library>LEGACY</spirit:library>
- <spirit:name>PLL</spirit:name>
- <spirit:version>5.7</spirit:version>
- <spirit:fileSets>
- <spirit:fileset>
- <spirit:name>Diamond_Simulation</spirit:name>
- <spirit:group>simulation</spirit:group>
- <spirit:file>
- <spirit:name>./pll_in200_out100/pll_in200_out100.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileset>
- <spirit:fileset>
- <spirit:name>Diamond_Synthesis</spirit:name>
- <spirit:group>synthesis</spirit:group>
- <spirit:file>
- <spirit:name>./pll_in200_out100/pll_in200_out100.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileset>
- </spirit:fileSets>
- <spirit:componentGenerators>
- <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
- <spirit:name>Configuration</spirit:name>
- <spirit:apiType>none</spirit:apiType>
- <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
- <spirit:group>CONFIG</spirit:group>
- </spirit:componentGenerator>
- <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
- <spirit:name>CreateNGD</spirit:name>
- <spirit:apiType>none</spirit:apiType>
- <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
- <spirit:group>CONFIG</spirit:group>
- </spirit:componentGenerator>
- <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
- <spirit:name>Generation</spirit:name>
- <spirit:apiType>none</spirit:apiType>
- <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
- <spirit:group>GENERATE</spirit:group>
- </spirit:componentGenerator>
- </spirit:componentGenerators>
- <spirit:model>
- <spirit:views/>
- <spirit:ports>
- <spirit:port>
- <spirit:name>CLKI</spirit:name>
- <spirit:displayName>CLKI</spirit:displayName>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- </spirit:port>
- <spirit:port>
- <spirit:name>CLKOP</spirit:name>
- <spirit:displayName>CLKOP</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>CLKOS</spirit:name>
- <spirit:displayName>CLKOS</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>LOCK</spirit:name>
- <spirit:displayName>LOCK</spirit:displayName>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <lattice:synthesis>synplify</lattice:synthesis>
- <lattice:modified>2015-03-17.15:44:52</lattice:modified>
- <lattice:attributes>
- <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
- <lattice:attribute lattice:name="BBox">false</lattice:attribute>
- <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
- <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
- <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
- <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
- <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
- <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
- <lattice:attribute lattice:name="Resource">IO:2;PLL:1;DLL:0</lattice:attribute>
- </lattice:attributes>
- <lattice:elements>
- <lattice:element>
- <lattice:name>CLKI</lattice:name>
- <lattice:type>IO</lattice:type>
- <lattice:attributes>
- <lattice:attribute lattice:name="Block_Name">Inst1_IB</lattice:attribute>
- <lattice:attribute lattice:name="CLK_SRC">true</lattice:attribute>
- <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
- <lattice:attribute lattice:name="ElementType">IO</lattice:attribute>
- <lattice:attribute lattice:name="isPort">true</lattice:attribute>
- </lattice:attributes>
- </lattice:element>
- <lattice:element>
- <lattice:name>CLKI~</lattice:name>
- <lattice:type>IO</lattice:type>
- <lattice:attributes>
- <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
- <lattice:attribute lattice:name="ElementType">IO</lattice:attribute>
- <lattice:attribute lattice:name="ngd">true</lattice:attribute>
- </lattice:attributes>
- </lattice:element>
- <lattice:element>
- <lattice:name>pll_in200_out100</lattice:name>
- <lattice:type>GXPLL</lattice:type>
- <lattice:attributes>
- <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
- <lattice:attribute lattice:name="ElementType">GXPLL</lattice:attribute>
- </lattice:attributes>
- </lattice:element>
- </lattice:elements>
- <lattice:lpc>
- <lattice:lpcsection lattice:name="Device"/>
- <lattice:lpcentry>
- <lattice:lpckey>Family</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>OperatingCondition</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Package</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">CSFBGA285</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PartName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8MG285C</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PartType</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SpeedGrade</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Status</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">C</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="IP"/>
- <lattice:lpcentry>
- <lattice:lpckey>CoreName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreRevision</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">5.7</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreStatus</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreType</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Date</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">03/17/2015</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ModuleName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">pll_in200_out100</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SourceFormat</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Time</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">15:42:59</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>VendorName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="Parameters"/>
- <lattice:lpcentry>
- <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKI_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.000000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">6</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200.000000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Destination</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>EDIF</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Expression</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">None</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>FRACN_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>IO</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>IOBUF</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Order</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">None</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PLL_BW</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8.185</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>REFERENCE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>VCO_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>VHDL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Verilog</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="Command"/>
- <lattice:lpcentry>
- <lattice:lpckey>cmd_line</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">-w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1</lattice:lpcvalue>
- </lattice:lpcentry>
- </lattice:lpc>
- <lattice:groups>
- <lattice:group>
- <lattice:name>GXPLL</lattice:name>
- <lattice:category>1</lattice:category>
- <lattice:attributes>
- <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupHide">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupType">GXPLL</lattice:attribute>
- </lattice:attributes>
- <lattice:elementref>pll_in200_out100</lattice:elementref>
- </lattice:group>
- <lattice:group>
- <lattice:name>IO</lattice:name>
- <lattice:category>1</lattice:category>
- <lattice:attributes>
- <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupHide">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupType">IO</lattice:attribute>
- </lattice:attributes>
- <lattice:elementref>CLKI</lattice:elementref>
- <lattice:elementref>CLKI~</lattice:elementref>
- </lattice:group>
- <lattice:group>
- <lattice:name>pll</lattice:name>
- <lattice:category>0</lattice:category>
- <lattice:attributes>
- <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
- <lattice:attribute lattice:name="GroupType">PLL</lattice:attribute>
- </lattice:attributes>
- <lattice:elementref>CLKI</lattice:elementref>
- <lattice:elementref>CLKI~</lattice:elementref>
- <lattice:elementref>pll_in200_out100</lattice:elementref>
- </lattice:group>
- </lattice:groups>
- </spirit:vendorExtensions>
- </spirit:componentRef>
- </spirit:componentInstance>
- </spirit:componentInstances>
- <spirit:adHocConnections>
- <spirit:adHocConnection>
- <spirit:name>pll_in200_out100_CLKI</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKI</spirit:displayName>
- <spirit:vendorExtensions>
- <lattice:attributes>
- <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
- </lattice:attributes>
- </spirit:vendorExtensions>
- <spirit:internalPortReference spirit:portRef="CLKI" spirit:componentRef="pll_in200_out100"/>
- <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKI"/>
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>pll_in200_out100_CLKOP</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKOP</spirit:displayName>
- <spirit:internalPortReference spirit:portRef="CLKOP" spirit:componentRef="pll_in200_out100"/>
- <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKOP"/>
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>pll_in200_out100_CLKOS</spirit:name>
- <spirit:displayName>pll_in200_out100_CLKOS</spirit:displayName>
- <spirit:internalPortReference spirit:portRef="CLKOS" spirit:componentRef="pll_in200_out100"/>
- <spirit:externalPortReference spirit:portRef="pll_in200_out100_CLKOS"/>
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>pll_in200_out100_LOCK</spirit:name>
- <spirit:displayName>pll_in200_out100_LOCK</spirit:displayName>
- <spirit:internalPortReference spirit:portRef="LOCK" spirit:componentRef="pll_in200_out100"/>
- <spirit:externalPortReference spirit:portRef="pll_in200_out100_LOCK"/>
- </spirit:adHocConnection>
- </spirit:adHocConnections>
- </spirit:design>
-</lattice:project>
+++ /dev/null
-main called
-main 10
-main 20
-main 30
-main 40
-main 50
-main 60
-main 70
-main 80
-main 90
-main 100
-main 110
-MainAppInit 10
-MainAppInit 20
-MainAppInit 30
-MainAppInit 40
+++ /dev/null
-PROJECT: pll_in200_out100
- working_path: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results"
- module: pll_in200_out100
- verilog_file_list: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
- vlog_std_v2001: true
- constraint_file_name: "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
- suffix_name: edn
- output_file_name: pll_in200_out100
- write_prf: true
- disable_io_insertion: true
- force_gsr: false
- frequency: 100
- fanout_limit: 50
- retiming: false
- pipe: false
- part: LFE5UM-85F
- speed_grade: 8
-
+++ /dev/null
-(edif pll_in200_out100
- (edifVersion 2 0 0)
- (edifLevel 0)
- (keywordMap (keywordLevel 0))
- (status
- (written
- (timestamp 2015 3 17 15 43 11)
- (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80"))))
- (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc ")
- (library ORCLIB
- (edifLevel 0)
- (technology
- (numberDefinition))
- (cell EHXPLLL
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port CLKI
- (direction INPUT))
- (port CLKFB
- (direction INPUT))
- (port PHASESEL1
- (direction INPUT))
- (port PHASESEL0
- (direction INPUT))
- (port PHASEDIR
- (direction INPUT))
- (port PHASESTEP
- (direction INPUT))
- (port PHASELOADREG
- (direction INPUT))
- (port STDBY
- (direction INPUT))
- (port PLLWAKESYNC
- (direction INPUT))
- (port RST
- (direction INPUT))
- (port ENCLKOP
- (direction INPUT))
- (port ENCLKOS
- (direction INPUT))
- (port ENCLKOS2
- (direction INPUT))
- (port ENCLKOS3
- (direction INPUT))
- (port CLKOP
- (direction OUTPUT))
- (port CLKOS
- (direction OUTPUT))
- (port CLKOS2
- (direction OUTPUT))
- (port CLKOS3
- (direction OUTPUT))
- (port LOCK
- (direction OUTPUT))
- (port INTLOCK
- (direction OUTPUT))
- (port REFCLK
- (direction OUTPUT))
- (port CLKINTFB
- (direction OUTPUT)))))
- (cell VHI
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port Z
- (direction OUTPUT)))))
- (cell VLO
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port Z
- (direction OUTPUT)))))
- (cell IB
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port I
- (direction INPUT))
- (port O
- (direction OUTPUT)))))
- (cell pll_in200_out100
- (cellType GENERIC)
- (view view1
- (viewType NETLIST)
- (interface
- (port CLKI
- (direction INPUT))
- (port CLKOP
- (direction OUTPUT))
- (port CLKOS
- (direction OUTPUT))
- (port LOCK
- (direction OUTPUT)))
- (property NGD_DRC_MASK (integer 1))
- (contents
- (instance Inst1_IB
- (viewRef view1
- (cellRef IB))
- (property IO_TYPE
- (string "LVDS")))
- (instance scuba_vhi_inst
- (viewRef view1
- (cellRef VHI)))
- (instance scuba_vlo_inst
- (viewRef view1
- (cellRef VLO)))
- (instance PLLInst_0
- (viewRef view1
- (cellRef EHXPLLL))
- (property PLLRST_ENA
- (string "DISABLED"))
- (property INTFB_WAKE
- (string "DISABLED"))
- (property STDBY_ENABLE
- (string "DISABLED"))
- (property DPHASE_SOURCE
- (string "DISABLED"))
- (property CLKOS3_FPHASE
- (string "0"))
- (property CLKOS3_CPHASE
- (string "0"))
- (property CLKOS2_FPHASE
- (string "0"))
- (property CLKOS2_CPHASE
- (string "0"))
- (property CLKOS_FPHASE
- (string "0"))
- (property CLKOS_CPHASE
- (string "0"))
- (property CLKOP_FPHASE
- (string "0"))
- (property CLKOP_CPHASE
- (string "5"))
- (property PLL_LOCK_MODE
- (string "0"))
- (property CLKOS_TRIM_DELAY
- (string "0"))
- (property CLKOS_TRIM_POL
- (string "FALLING"))
- (property CLKOP_TRIM_DELAY
- (string "0"))
- (property CLKOP_TRIM_POL
- (string "FALLING"))
- (property OUTDIVIDER_MUXD
- (string "DIVD"))
- (property CLKOS3_ENABLE
- (string "DISABLED"))
- (property OUTDIVIDER_MUXC
- (string "DIVC"))
- (property CLKOS2_ENABLE
- (string "DISABLED"))
- (property FREQUENCY_PIN_CLKOS
- (string "200.000000"))
- (property OUTDIVIDER_MUXB
- (string "DIVB"))
- (property CLKOS_ENABLE
- (string "ENABLED"))
- (property FREQUENCY_PIN_CLKOP
- (string "100.000000"))
- (property OUTDIVIDER_MUXA
- (string "DIVA"))
- (property CLKOP_ENABLE
- (string "ENABLED"))
- (property FREQUENCY_PIN_CLKI
- (string "200.000000"))
- (property ICP_CURRENT
- (string "9"))
- (property LPF_RESISTOR
- (string "72"))
- (property CLKOS3_DIV
- (string "1"))
- (property CLKOS2_DIV
- (string "1"))
- (property CLKOS_DIV
- (string "1"))
- (property CLKOP_DIV
- (string "6"))
- (property CLKFB_DIV
- (string "1"))
- (property CLKI_DIV
- (string "2"))
- (property FEEDBK_PATH
- (string "CLKOP")))
- (net REFCLK
- (joined
- (portRef REFCLK (instanceRef PLLInst_0))))
- (net buf_CLKI
- (joined
- (portRef O (instanceRef Inst1_IB))
- (portRef CLKI (instanceRef PLLInst_0))))
- (net scuba_vhi
- (joined
- (portRef Z (instanceRef scuba_vhi_inst))))
- (net scuba_vlo
- (joined
- (portRef Z (instanceRef scuba_vlo_inst))
- (portRef ENCLKOS3 (instanceRef PLLInst_0))
- (portRef ENCLKOS2 (instanceRef PLLInst_0))
- (portRef ENCLKOS (instanceRef PLLInst_0))
- (portRef ENCLKOP (instanceRef PLLInst_0))
- (portRef RST (instanceRef PLLInst_0))
- (portRef PLLWAKESYNC (instanceRef PLLInst_0))
- (portRef STDBY (instanceRef PLLInst_0))
- (portRef PHASELOADREG (instanceRef PLLInst_0))
- (portRef PHASESTEP (instanceRef PLLInst_0))
- (portRef PHASEDIR (instanceRef PLLInst_0))
- (portRef PHASESEL1 (instanceRef PLLInst_0))
- (portRef PHASESEL0 (instanceRef PLLInst_0))))
- (net LOCK
- (joined
- (portRef LOCK)
- (portRef LOCK (instanceRef PLLInst_0))))
- (net CLKOS
- (joined
- (portRef CLKOS)
- (portRef CLKOS (instanceRef PLLInst_0))))
- (net CLKOP
- (joined
- (portRef CLKOP)
- (portRef CLKFB (instanceRef PLLInst_0))
- (portRef CLKOP (instanceRef PLLInst_0))))
- (net CLKI
- (joined
- (portRef CLKI)
- (portRef I (instanceRef Inst1_IB))))))))
- (design pll_in200_out100
- (cellRef pll_in200_out100
- (libraryRef ORCLIB)))
-)
+++ /dev/null
-###==== Start Configuration
-
+++ /dev/null
-[Device]
-Family=ecp5um
-PartType=LFE5UM-85F
-PartName=LFE5UM-85F-8MG285C
-SpeedGrade=8
-Package=CSFBGA285
-OperatingCondition=COM
-Status=C
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.7
-ModuleName=pll_in200_out100
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=03/17/2015
-Time=15:42:59
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-CLKI_FREQ=200
-CLKI_DIV=2
-ENABLE_HBW=DISABLED
-REFERENCE=1
-IOBUF=LVDS
-CLKOP_FREQ=100.00
-CLKOP_TOL=0.0
-CLKOP_DIV=6
-CLKOP_ACTUAL_FREQ=100.000000
-CLKOP_MUXA=DISABLED
-CLKOS_Enable=ENABLED
-CLKOS_FREQ=100.00
-CLKOS_TOL=0.0
-CLKOS_DIV=1
-CLKOS_ACTUAL_FREQ=200.000000
-CLKOS_MUXB=ENABLED
-CLKOS2_Enable=DISABLED
-CLKOS2_FREQ=100.00
-CLKOS2_TOL=0.0
-CLKOS2_DIV=1
-CLKOS2_ACTUAL_FREQ=
-CLKOS2_MUXC=DISABLED
-CLKOS3_Enable=DISABLED
-CLKOS3_FREQ=100.00
-CLKOS3_TOL=0.0
-CLKOS3_DIV=1
-CLKOS3_ACTUAL_FREQ=
-CLKOS3_MUXD=DISABLED
-FEEDBK_PATH=CLKOP
-CLKFB_DIV=1
-FRACN_ENABLE=DISABLED
-FRACN_DIV=
-VCO_RATE=600.000
-PLL_BW=8.185
-CLKOP_DPHASE=0
-CLKOP_APHASE=0.00
-CLKOP_TRIM_POL=Rising
-CLKOP_TRIM_DELAY=0
-CLKOS_DPHASE=0
-CLKOS_APHASE=0.00
-CLKOS_TRIM_POL=Rising
-CLKOS_TRIM_DELAY=0
-CLKOS2_DPHASE=0
-CLKOS2_APHASE=0.00
-CLKOS2_TRIM_POL=Rising
-CLKOS2_TRIM_DELAY=0
-CLKOS3_DPHASE=0
-CLKOS3_APHASE=0.00
-CLKOS3_TRIM_POL=Rising
-CLKOS3_TRIM_DELAY=0
-CLKSEL_ENA=DISABLED
-DPHASE_SOURCE=STATIC
-ENABLE_CLKOP=DISABLED
-ENABLE_CLKOS=DISABLED
-ENABLE_CLKOS2=DISABLED
-ENABLE_CLKOS3=DISABLED
-STDBY_ENABLE=DISABLED
-PLLRST_ENA=DISABLED
-PLL_LOCK_MODE=ENABLED
-PLL_LOCK_STK=DISABLED
-PLL_USE_SMI=DISABLED
-
-[Command]
-cmd_line= -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
--- Module Version: 5.7
---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch sa5p00m -type pll -fin 200 -clkibuf LVDS -fclkop 100.00 -fclkop_tol 0.0 -bypass_divs -phase_cntl STATIC -lock -fb_mode 1 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
--- Tue Mar 17 15:43:11 2015
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-library ecp5um;
-use ecp5um.components.all;
-
-entity pll_in200_out100 is
- port (
- CLKI: in std_logic;
- CLKOP: out std_logic;
- CLKOS: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_in200_out100 : entity is true;
-end pll_in200_out100;
-
-architecture Structure of pll_in200_out100 is
-
- -- internal signal declarations
- signal REFCLK: std_logic;
- signal CLKOS_t: std_logic;
- signal CLKOP_t: std_logic;
- signal buf_CLKI: std_logic;
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- attribute IO_TYPE : string;
- attribute FREQUENCY_PIN_CLKOS : string;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute ICP_CURRENT : string;
- attribute LPF_RESISTOR : string;
- attribute IO_TYPE of Inst1_IB : label is "LVDS";
- attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "100.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
- attribute ICP_CURRENT of PLLInst_0 : label is "9";
- attribute LPF_RESISTOR of PLLInst_0 : label is "72";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- Inst1_IB: IB
- port map (I=>CLKI, O=>buf_CLKI);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLL
- generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
- STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
- CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
- CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0,
- CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 5, PLL_LOCK_MODE=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
- OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
- OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
- OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
- OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
- CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 6, CLKFB_DIV=> 1,
- CLKI_DIV=> 2, FEEDBK_PATH=> "CLKOP")
- port map (CLKI=>buf_CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
- PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
- PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
- STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
- ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
- ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
- CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
- REFCLK=>REFCLK, CLKINTFB=>open);
-
- CLKOS <= CLKOS_t;
- CLKOP <= CLKOP_t;
-end Structure;
+++ /dev/null
-[ActiveSupport NGD]
+++ /dev/null
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+++ /dev/null
-MainAppInit 50
+++ /dev/null
-----------------------------------------------------------------------
-Report for cell pll_in200_out100.structure
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 1
- Cell usage:
- cell count Res Usage(%)
- EHXPLLL 1 100.0
- GSR 1 100.0
- IB 1 100.0
- PUR 1 100.0
- VHI 1 100.0
- VLO 1 100.0
-
- TOTAL 6
+++ /dev/null
-(edif pll_in200_out100
- (edifVersion 2 0 0)
- (edifLevel 0)
- (keywordMap (keywordLevel 0))
- (status
- (written
- (timeStamp 2015 3 17 15 43 13)
- (author "Synopsys, Inc.")
- (program "Synplify Pro" (version "J-2014.09-SP2, mapper maprc, Build 2453R"))
- )
- )
- (library ecp5um
- (edifLevel 0)
- (technology (numberDefinition ))
- (cell EHXPLLL (cellType GENERIC)
- (view syn_black_box (viewType NETLIST)
- (interface
- (port CLKI (direction INPUT))
- (port CLKFB (direction INPUT))
- (port PHASESEL1 (direction INPUT))
- (port PHASESEL0 (direction INPUT))
- (port PHASEDIR (direction INPUT))
- (port PHASESTEP (direction INPUT))
- (port PHASELOADREG (direction INPUT))
- (port STDBY (direction INPUT))
- (port PLLWAKESYNC (direction INPUT))
- (port RST (direction INPUT))
- (port ENCLKOP (direction INPUT))
- (port ENCLKOS (direction INPUT))
- (port ENCLKOS2 (direction INPUT))
- (port ENCLKOS3 (direction INPUT))
- (port CLKOP (direction OUTPUT))
- (port CLKOS (direction OUTPUT))
- (port CLKOS2 (direction OUTPUT))
- (port CLKOS3 (direction OUTPUT))
- (port LOCK (direction OUTPUT))
- (port INTLOCK (direction OUTPUT))
- (port REFCLK (direction OUTPUT))
- (port CLKINTFB (direction OUTPUT))
- )
- (property CLKI_DIV (integer 1))
- (property CLKFB_DIV (integer 1))
- (property CLKOP_DIV (integer 8))
- (property CLKOS_DIV (integer 8))
- (property CLKOS2_DIV (integer 8))
- (property CLKOS3_DIV (integer 8))
- (property CLKOP_ENABLE (string "ENABLED"))
- (property CLKOS_ENABLE (string "DISABLED"))
- (property CLKOS2_ENABLE (string "DISABLED"))
- (property CLKOS3_ENABLE (string "DISABLED"))
- (property CLKOP_CPHASE (integer 0))
- (property CLKOS_CPHASE (integer 0))
- (property CLKOS2_CPHASE (integer 0))
- (property CLKOS3_CPHASE (integer 0))
- (property CLKOP_FPHASE (integer 0))
- (property CLKOS_FPHASE (integer 0))
- (property CLKOS2_FPHASE (integer 0))
- (property CLKOS3_FPHASE (integer 0))
- (property FEEDBK_PATH (string "CLKOP"))
- (property CLKOP_TRIM_POL (string "RISING"))
- (property CLKOP_TRIM_DELAY (integer 0))
- (property CLKOS_TRIM_POL (string "RISING"))
- (property CLKOS_TRIM_DELAY (integer 0))
- (property OUTDIVIDER_MUXA (string "DIVA"))
- (property OUTDIVIDER_MUXB (string "DIVB"))
- (property OUTDIVIDER_MUXC (string "DIVC"))
- (property OUTDIVIDER_MUXD (string "DIVD"))
- (property PLL_LOCK_MODE (integer 0))
- (property PLL_LOCK_DELAY (integer 200))
- (property STDBY_ENABLE (string "DISABLED"))
- (property REFIN_RESET (string "DISABLED"))
- (property SYNC_ENABLE (string "DISABLED"))
- (property INT_LOCK_STICKY (string "ENABLED"))
- (property DPHASE_SOURCE (string "DISABLED"))
- (property PLLRST_ENA (string "DISABLED"))
- (property INTFB_WAKE (string "DISABLED"))
- (property orig_inst_of (string "EHXPLLL"))
- )
- )
- )
- (library LUCENT
- (edifLevel 0)
- (technology (numberDefinition ))
- (cell IB (cellType GENERIC)
- (view PRIM (viewType NETLIST)
- (interface
- (port I (direction INPUT))
- (port O (direction OUTPUT))
- )
- )
- )
- (cell GSR (cellType GENERIC)
- (view PRIM (viewType NETLIST)
- (interface
- (port GSR (direction INPUT))
- )
- )
- )
- (cell VHI (cellType GENERIC)
- (view PRIM (viewType NETLIST)
- (interface
- (port Z (direction OUTPUT))
- )
- )
- )
- (cell VLO (cellType GENERIC)
- (view PRIM (viewType NETLIST)
- (interface
- (port Z (direction OUTPUT))
- )
- )
- )
- )
- (library work
- (edifLevel 0)
- (technology (numberDefinition ))
- (cell pll_in200_out100 (cellType GENERIC)
- (view structure (viewType NETLIST)
- (interface
- (port CLKI (direction INPUT))
- (port CLKOP (direction OUTPUT))
- (port CLKOS (direction OUTPUT))
- (port LOCK (direction OUTPUT))
- )
- (contents
- (instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
- (instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
- (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
- )
- (instance Inst1_IB (viewRef PRIM (cellRef IB (libraryRef LUCENT)))
- (property IO_TYPE (string "LVDS"))
- )
- (instance PLLInst_0 (viewRef syn_black_box (cellRef EHXPLLL (libraryRef ecp5um)))
- (property INTFB_WAKE (string "DISABLED"))
- (property PLLRST_ENA (string "DISABLED"))
- (property DPHASE_SOURCE (string "DISABLED"))
- (property STDBY_ENABLE (string "DISABLED"))
- (property PLL_LOCK_MODE (integer 0))
- (property OUTDIVIDER_MUXD (string "DIVD"))
- (property OUTDIVIDER_MUXC (string "DIVC"))
- (property OUTDIVIDER_MUXB (string "DIVB"))
- (property OUTDIVIDER_MUXA (string "DIVA"))
- (property CLKOS_TRIM_DELAY (integer 0))
- (property CLKOS_TRIM_POL (string "FALLING"))
- (property CLKOP_TRIM_DELAY (integer 0))
- (property CLKOP_TRIM_POL (string "FALLING"))
- (property FEEDBK_PATH (string "CLKOP"))
- (property CLKOS3_FPHASE (integer 0))
- (property CLKOS2_FPHASE (integer 0))
- (property CLKOS_FPHASE (integer 0))
- (property CLKOP_FPHASE (integer 0))
- (property CLKOS3_CPHASE (integer 0))
- (property CLKOS2_CPHASE (integer 0))
- (property CLKOS_CPHASE (integer 0))
- (property CLKOP_CPHASE (integer 5))
- (property CLKOS3_ENABLE (string "DISABLED"))
- (property CLKOS2_ENABLE (string "DISABLED"))
- (property CLKOS_ENABLE (string "ENABLED"))
- (property CLKOP_ENABLE (string "ENABLED"))
- (property CLKOS3_DIV (integer 1))
- (property CLKOS2_DIV (integer 1))
- (property CLKOS_DIV (integer 1))
- (property CLKOP_DIV (integer 6))
- (property CLKFB_DIV (integer 1))
- (property CLKI_DIV (integer 2))
- (property LPF_RESISTOR (string "72"))
- (property ICP_CURRENT (string "9"))
- (property FREQUENCY_PIN_CLKI (string "200.000000"))
- (property FREQUENCY_PIN_CLKOP (string "100.000000"))
- (property FREQUENCY_PIN_CLKOS (string "200.000000"))
- )
- (net CLKI (joined
- (portRef CLKI)
- (portRef I (instanceRef Inst1_IB))
- ))
- (net CLKOP (joined
- (portRef CLKOP (instanceRef PLLInst_0))
- (portRef CLKFB (instanceRef PLLInst_0))
- (portRef CLKOP)
- ))
- (net CLKOS (joined
- (portRef CLKOS (instanceRef PLLInst_0))
- (portRef CLKOS)
- ))
- (net LOCK (joined
- (portRef LOCK (instanceRef PLLInst_0))
- (portRef LOCK)
- ))
- (net CLKOS2 (joined
- (portRef CLKOS2 (instanceRef PLLInst_0))
- ))
- (net CLKOS3 (joined
- (portRef CLKOS3 (instanceRef PLLInst_0))
- ))
- (net INTLOCK (joined
- (portRef INTLOCK (instanceRef PLLInst_0))
- ))
- (net CLKINTFB (joined
- (portRef CLKINTFB (instanceRef PLLInst_0))
- ))
- (net buf_CLKI (joined
- (portRef O (instanceRef Inst1_IB))
- (portRef CLKI (instanceRef PLLInst_0))
- ))
- (net REFCLK (joined
- (portRef REFCLK (instanceRef PLLInst_0))
- ))
- (net GND (joined
- (portRef Z (instanceRef GND_0))
- (portRef ENCLKOS3 (instanceRef PLLInst_0))
- (portRef ENCLKOS2 (instanceRef PLLInst_0))
- (portRef ENCLKOS (instanceRef PLLInst_0))
- (portRef ENCLKOP (instanceRef PLLInst_0))
- (portRef RST (instanceRef PLLInst_0))
- (portRef PLLWAKESYNC (instanceRef PLLInst_0))
- (portRef STDBY (instanceRef PLLInst_0))
- (portRef PHASELOADREG (instanceRef PLLInst_0))
- (portRef PHASESTEP (instanceRef PLLInst_0))
- (portRef PHASEDIR (instanceRef PLLInst_0))
- (portRef PHASESEL0 (instanceRef PLLInst_0))
- (portRef PHASESEL1 (instanceRef PLLInst_0))
- ))
- (net VCC (joined
- (portRef Z (instanceRef VCC_0))
- (portRef GSR (instanceRef GSR_INST))
- ))
- )
- (property NGD_DRC_MASK (integer 1))
- (property dont_touch (integer 1))
- (property orig_inst_of (string "pll_in200_out100"))
- )
- )
- )
- (design pll_in200_out100 (cellRef pll_in200_out100 (libraryRef work))
- (property PART (string "lfe5um_25f-6") ))
-)
+++ /dev/null
-<html>
- <head>
- <title>syntmp/pll_in200_out100_srr.htm log file</title>
- </head>
- <frameset cols="20%, 80%">
- <frame src="syntmp/pll_in200_out100_toc.htm" name="tocFrame" />
- <frame src="syntmp/pll_in200_out100_srr.htm" name="srrFrame"/>
-</frameset>
- </html>
+++ /dev/null
-#-- Lattice Semiconductor Corporation Ltd.
-#-- Synplify OEM project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.prj
-#-- Written on Tue Mar 17 15:43:11 2015
-
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM-85F
-set_option -speed_grade 8
-
-#use verilog 2001 standard option
-set_option -vlog_std v2001
-
-#map options
-set_option -frequency 100
-set_option -fanout_limit 50
-set_option -disable_io_insertion true
-set_option -retiming false
-set_option -pipe false
-set_option -pipe false
-set_option -force_gsr false
-
-#simulation options
-set_option -write_verilog true
-set_option -write_vhdl true
-
-#timing analysis options
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#-- add_file options
-add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
-add_file -constraint {"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"}
-
-#-- top module name
-set_option -top_module pll_in200_out100
-
-#-- set result format/file last
-project -result_file "pll_in200_out100.edn"
-
-#-- error message log file
-project -log_file pll_in200_out100.srf
-
-#-- run Synplify with 'arrange VHDL file'
-project -run
+++ /dev/null
-#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
-#install: /opt/synopsys/J-2014.09-SP2
-#OS: Linux
-#Hostname: depc363
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-Running on host :depc363
-Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
-@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
-VHDL syntax check successful!
-@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box
-Post processing for ecp5um.vhi.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box
-Post processing for ecp5um.ib.syn_black_box
-Post processing for work.pll_in200_out100.structure
-@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ...
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:12 2015
-
-###########################################################]
-Pre-mapping Report
-
-Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt
-Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-@S |Clock Summary
-****************
-
-Start Requested Requested Clock Clock
-Clock Frequency Period Type Group
------------------------------------------------------------------
-System 100.0 MHz 10.000 system system_clkgroup
-=================================================================
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:13 2015
-
-###########################################################]
-Map & Optimize Report
-
-Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-------------------------------------------------------------
-
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing EDIF Netlist and constraint files
-J-2014.09-SP2
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-@S |##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Mar 17 15:43:14 2015
-#
-
-
-Top view: pll_in200_out100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000
-==============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000
-===============================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKOP
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 -
-CLKOP Net - - - - 2
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-=================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-
-Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 1
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-IB: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:14 2015
-
-###########################################################]
+++ /dev/null
-#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
-#install: /opt/synopsys/J-2014.09-SP2
-#OS: Linux
-#Hostname: depc363
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-Running on host :depc363
-Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
-@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
-VHDL syntax check successful!
-@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box
-Post processing for ecp5um.vhi.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box
-Post processing for ecp5um.ib.syn_black_box
-Post processing for work.pll_in200_out100.structure
-@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ...
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:12 2015
-
-###########################################################]
-Pre-mapping Report
-
-Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt
-Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-@S |Clock Summary
-****************
-
-Start Requested Requested Clock Clock
-Clock Frequency Period Type Group
------------------------------------------------------------------
-System 100.0 MHz 10.000 system system_clkgroup
-=================================================================
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:13 2015
-
-###########################################################]
-Map & Optimize Report
-
-Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-------------------------------------------------------------
-
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing EDIF Netlist and constraint files
-J-2014.09-SP2
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-@S |##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Mar 17 15:43:14 2015
-#
-
-
-Top view: pll_in200_out100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000
-==============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000
-===============================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKOP
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 -
-CLKOP Net - - - - 2
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-=================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-
-Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 1
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-IB: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:14 2015
-
-###########################################################]
+++ /dev/null
---
--- Written by Synplicity
--- Product Version "J-2014.09-SP2"
--- Program "Synplify Pro", Mapper "maprc, Build 2453R"
--- Tue Mar 17 15:43:14 2015
---
-
---
--- Written by Synplify Pro version Build 2453R
--- Tue Mar 17 15:43:14 2015
---
-
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library synplify;
-use synplify.components.all;
-library pmi;
-use pmi.pmi_components.all;
-library ecp5um;
-use ecp5um.components.all;
-
-entity pll_in200_out100 is
-port(
- CLKI : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- LOCK : out std_logic);
-end pll_in200_out100;
-
-architecture beh of pll_in200_out100 is
- signal CLKOP_0 : std_logic ;
- signal CLKOS2 : std_logic ;
- signal CLKOS3 : std_logic ;
- signal INTLOCK : std_logic ;
- signal CLKINTFB : std_logic ;
- signal BUF_CLKI : std_logic ;
- signal REFCLK : std_logic ;
- signal GND : std_logic ;
- signal VCC : std_logic ;
- component EHXPLLL
- port(
- CLKI : in std_logic;
- CLKFB : in std_logic;
- PHASESEL1 : in std_logic;
- PHASESEL0 : in std_logic;
- PHASEDIR : in std_logic;
- PHASESTEP : in std_logic;
- PHASELOADREG : in std_logic;
- STDBY : in std_logic;
- PLLWAKESYNC : in std_logic;
- RST : in std_logic;
- ENCLKOP : in std_logic;
- ENCLKOS : in std_logic;
- ENCLKOS2 : in std_logic;
- ENCLKOS3 : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- CLKOS2 : out std_logic;
- CLKOS3 : out std_logic;
- LOCK : out std_logic;
- INTLOCK : out std_logic;
- REFCLK : out std_logic;
- CLKINTFB : out std_logic );
- end component;
-begin
-GND_0: VLO port map (
- Z => GND);
-VCC_0: VHI port map (
- Z => VCC);
-PUR_INST: PUR port map (
- PUR => VCC);
-GSR_INST: GSR port map (
- GSR => VCC);
-INST1_IB: IB port map (
- I => CLKI,
- O => BUF_CLKI);
-PLLINST_0: EHXPLLL
- generic map(
- CLKI_DIV => 2,
- CLKFB_DIV => 1,
- CLKOP_DIV => 6,
- CLKOS_DIV => 1,
- CLKOS2_DIV => 1,
- CLKOS3_DIV => 1,
- CLKOP_ENABLE => "ENABLED",
- CLKOS_ENABLE => "ENABLED",
- CLKOS2_ENABLE => "DISABLED",
- CLKOS3_ENABLE => "DISABLED",
- CLKOP_CPHASE => 5,
- CLKOS_CPHASE => 0,
- CLKOS2_CPHASE => 0,
- CLKOS3_CPHASE => 0,
- CLKOP_FPHASE => 0,
- CLKOS_FPHASE => 0,
- CLKOS2_FPHASE => 0,
- CLKOS3_FPHASE => 0,
- FEEDBK_PATH => "CLKOP",
- CLKOP_TRIM_POL => "FALLING",
- CLKOP_TRIM_DELAY => 0,
- CLKOS_TRIM_POL => "FALLING",
- CLKOS_TRIM_DELAY => 0,
- OUTDIVIDER_MUXA => "DIVA",
- OUTDIVIDER_MUXB => "DIVB",
- OUTDIVIDER_MUXC => "DIVC",
- OUTDIVIDER_MUXD => "DIVD",
- PLL_LOCK_MODE => 0,
- STDBY_ENABLE => "DISABLED",
- DPHASE_SOURCE => "DISABLED",
- PLLRST_ENA => "DISABLED",
- INTFB_WAKE => "DISABLED"
- )
- port map (
- CLKI => BUF_CLKI,
- CLKFB => CLKOP_0,
- PHASESEL1 => GND,
- PHASESEL0 => GND,
- PHASEDIR => GND,
- PHASESTEP => GND,
- PHASELOADREG => GND,
- STDBY => GND,
- PLLWAKESYNC => GND,
- RST => GND,
- ENCLKOP => GND,
- ENCLKOS => GND,
- ENCLKOS2 => GND,
- ENCLKOS3 => GND,
- CLKOP => CLKOP_0,
- CLKOS => CLKOS,
- CLKOS2 => CLKOS2,
- CLKOS3 => CLKOS3,
- LOCK => LOCK,
- INTLOCK => INTLOCK,
- REFCLK => REFCLK,
- CLKINTFB => CLKINTFB);
-CLKOP <= CLKOP_0;
-end beh;
-
+++ /dev/null
-//
-// Written by Synplify Pro
-// Product Version "J-2014.09-SP2"
-// Program "Synplify Pro", Mapper "maprc, Build 2453R"
-// Tue Mar 17 15:43:14 2015
-//
-// Source file index table:
-// Object locations will have the form <file>:<line>
-// file 0 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd "
-// file 1 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/snps_haps_pkg.vhd "
-// file 2 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/std1164.vhd "
-// file 3 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/numeric.vhd "
-// file 4 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/umr_capim.vhd "
-// file 5 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/arith.vhd "
-// file 6 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/unsigned.vhd "
-// file 7 "\/opt/synopsys/J-2014.09-SP2/lib/vhd/hyperents.vhd "
-// file 8 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd "
-// file 9 "\/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd "
-// file 10 "\/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc "
-
-`timescale 100 ps/100 ps
-module pll_in200_out100 (
- CLKI,
- CLKOP,
- CLKOS,
- LOCK
-)
-;
-input CLKI ;
-output CLKOP ;
-output CLKOS ;
-output LOCK ;
-wire CLKI ;
-wire CLKOP ;
-wire CLKOS ;
-wire LOCK ;
-wire CLKOS2 ;
-wire CLKOS3 ;
-wire INTLOCK ;
-wire CLKINTFB ;
-wire buf_CLKI ;
-wire REFCLK ;
-wire GND ;
-wire VCC ;
- VLO GND_0 (
- .Z(GND)
-);
- VHI VCC_0 (
- .Z(VCC)
-);
- PUR PUR_INST (
- .PUR(VCC)
-);
- GSR GSR_INST (
- .GSR(VCC)
-);
-// @8:52
- IB Inst1_IB (
- .I(CLKI),
- .O(buf_CLKI)
-);
-// @8:61
- EHXPLLL PLLInst_0 (
- .CLKI(buf_CLKI),
- .CLKFB(CLKOP),
- .PHASESEL1(GND),
- .PHASESEL0(GND),
- .PHASEDIR(GND),
- .PHASESTEP(GND),
- .PHASELOADREG(GND),
- .STDBY(GND),
- .PLLWAKESYNC(GND),
- .RST(GND),
- .ENCLKOP(GND),
- .ENCLKOS(GND),
- .ENCLKOS2(GND),
- .ENCLKOS3(GND),
- .CLKOP(CLKOP),
- .CLKOS(CLKOS),
- .CLKOS2(CLKOS2),
- .CLKOS3(CLKOS3),
- .LOCK(LOCK),
- .INTLOCK(INTLOCK),
- .REFCLK(REFCLK),
- .CLKINTFB(CLKINTFB)
-);
-defparam PLLInst_0.CLKI_DIV = 2;
-defparam PLLInst_0.CLKFB_DIV = 1;
-defparam PLLInst_0.CLKOP_DIV = 6;
-defparam PLLInst_0.CLKOS_DIV = 1;
-defparam PLLInst_0.CLKOS2_DIV = 1;
-defparam PLLInst_0.CLKOS3_DIV = 1;
-defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
-defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
-defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED";
-defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
-defparam PLLInst_0.CLKOP_CPHASE = 5;
-defparam PLLInst_0.CLKOS_CPHASE = 0;
-defparam PLLInst_0.CLKOS2_CPHASE = 0;
-defparam PLLInst_0.CLKOS3_CPHASE = 0;
-defparam PLLInst_0.CLKOP_FPHASE = 0;
-defparam PLLInst_0.CLKOS_FPHASE = 0;
-defparam PLLInst_0.CLKOS2_FPHASE = 0;
-defparam PLLInst_0.CLKOS3_FPHASE = 0;
-defparam PLLInst_0.FEEDBK_PATH = "CLKOP";
-defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
-defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
-defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
-defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
-defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA";
-defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
-defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC";
-defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
-defparam PLLInst_0.PLL_LOCK_MODE = 0;
-defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
-defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
-defparam PLLInst_0.PLLRST_ENA = "DISABLED";
-defparam PLLInst_0.INTFB_WAKE = "DISABLED";
-endmodule /* pll_in200_out100 */
-
+++ /dev/null
-#
-# Logical Preferences generated for Lattice by Synplify maprc, Build 2453R.
-#
-
-# Period Constraints
-
-
-# Output Constraints
-
-# Input Constraints
-
-# Point-to-point Delay Constraints
-
-
-
-# Block Path Constraints
-
-BLOCK ASYNCPATHS;
-
-# End of generated Logical Preferences.
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version J-2014.09-SP2
-#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/run_options.txt
-#-- Written on Tue Mar 17 15:43:11 2015
-
-
-#project files
-add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
-add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
-
-
-
-#implementation: "syn_results"
-impl -add syn_results -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM_25F
-set_option -package MG285C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "pll_in200_out100"
-
-# mapper_options
-set_option -frequency 100
-set_option -write_verilog 1
-set_option -write_vhdl 1
-set_option -srs_instrumentation 1
-
-# Lattice XP
-set_option -maxfan 50
-set_option -disable_io_insertion 1
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -RWCheckOnRam 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./pll_in200_out100.edn"
-
-#set log file
-set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf"
-impl -active "syn_results"
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version J-2014.09-SP2
-#-- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/scratchproject.prs
-
-#project files
-add_file -vhdl -lib work "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd"
-add_file -fpga_constraint "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc"
-
-
-
-#implementation: "syn_results"
-impl -add /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM_25F
-set_option -package MG285C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "pll_in200_out100"
-
-# mapper_options
-set_option -frequency 100
-set_option -write_verilog 1
-set_option -write_vhdl 1
-set_option -srs_instrumentation 1
-
-# Lattice XP
-set_option -maxfan 50
-set_option -disable_io_insertion 1
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -RWCheckOnRam 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.edn"
-
-#set log file
-set_option log_file "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srf"
-impl -active "syn_results"
+++ /dev/null
-./synlog/pll_in200_out100_fpga_mapper.srr,map.srr,Map Log
+++ /dev/null
-Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-Running on host :depc363
-Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
-@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
-VHDL syntax check successful!
-@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box
-Post processing for ecp5um.vhi.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box
-Post processing for ecp5um.ib.syn_black_box
-Post processing for work.pll_in200_out100.structure
-@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ...
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
+++ /dev/null
-./synlog/pll_in200_out100_compiler.srr,pll_in200_out100_compiler.srr,Compile Log
+++ /dev/null
-Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-------------------------------------------------------------
-
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing EDIF Netlist and constraint files
-J-2014.09-SP2
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-@S |##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Mar 17 15:43:14 2015
-#
-
-
-Top view: pll_in200_out100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000
-==============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000
-===============================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKOP
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 -
-CLKOP Net - - - - 2
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-=================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-
-Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 1
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-IB: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:14 2015
-
-###########################################################]
+++ /dev/null
-
-
-@S |##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Mar 17 15:43:14 2015
-#
-
-
-Top view: pll_in200_out100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 0.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz 100.0 MHz 10.000 10.000 0.000 system system_clkgroup
-===============================================================================================================
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------
-System System | 0.000 0.000 | No paths - | No paths - | No paths -
-========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 0.000
-=============================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKOP 0.000 0.000
-==============================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Propagation time: 0.000
- + Clock delay at starting point: 0.000 (ideal)
--0.000
- - Requested Period: 0.000
- - Hold time: 0.000
- - Clock delay at ending point: 0.000 (ideal)
-0.000
- = Slack (critical) : 0.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKOP
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 -
-CLKOP Net - - - - 2
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-=================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
+++ /dev/null
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-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:12 2015
-
-###########################################################]
+++ /dev/null
-Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-@L: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt
-Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-@S |Clock Summary
-****************
-
-Start Requested Requested Clock Clock
-Clock Frequency Period Type Group
------------------------------------------------------------------
-System 100.0 MHz 10.000 system system_clkgroup
-=================================================================
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:13 2015
-
-###########################################################]
+++ /dev/null
-./synlog/pll_in200_out100_premap.srr,pre_map.srr,Pre_Map Log
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
-@N:"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Top entity is set to pll_in200_out100.
-@N: CD630 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":12:7:12:22|Synthesizing work.pll_in200_out100.structure
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":2081:10:2081:16|Synthesizing ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":830:10:830:12|Synthesizing ecp5um.vlo.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":823:10:823:12|Synthesizing ecp5um.vhi.syn_black_box
-@N: CD630 :"/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd":998:10:998:11|Synthesizing ecp5um.ib.syn_black_box
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
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-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
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- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL168 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":55:4:55:17|Pruning instance scuba_vhi_inst -- not in use ...
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>0</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>1</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>0</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
-@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
-@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>0 / 0</data>
-<report_link name="more">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
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-<data>Completed</data>
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-<job_info>
-<info name="Notes">
-<data>11</data>
-<report_link name="more">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>1</data>
-<report_link name="more">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:01s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:01s</data>
-</info>
-<info name="Peak Memory">
-<data>143MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1426603394</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
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-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>NA</data>
-<data>10.000</data>
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-</report_table>
+++ /dev/null
-@W: MT246 :"/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd":61:4:61:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/pll_in200_out100_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
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-<data>Completed</data>
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-<job_info>
-<info name="Notes">
-<data>2</data>
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-<info name="Warnings">
-<data>0</data>
-<report_link name="more">
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-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_premap_errors.txt</data>
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-<data>0h:00m:00s</data>
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-<data>0h:00m:00s</data>
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-<info name="Peak Memory">
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-</info>
-<info name="Date & Time">
-<data type="timestamp">1426603393</data>
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-</job_info>
-</job_run_status>
+++ /dev/null
-@P: Worst Slack : 10.000
-@P: System - Estimated Frequency : NA
-@P: System - Requested Frequency : 100.0 MHz
-@P: System - Estimated Period : 0.000
-@P: System - Requested Period : 10.000
-@P: System - Slack : 10.000
-@P: Worst Slack(min analysis) : 0.000
-@P: System - Estimated Frequency(min analysis) : 100.0 MHz
-@P: System - Requested Frequency(min analysis) : 100.0 MHz
-@P: System - Estimated Period(min analysis) : 10.000
-@P: System - Requested Period(min analysis) : 10.000
-@P: System - Slack(min analysis) : 0.000
-@P: Total Area : 0.0
-@P: CPU Time : 0h:00m:01s
+++ /dev/null
-<html><body><samp><pre>
-<!@TC:1426603391>
-#Build: Synplify Pro J-2014.09-SP2, Build 1283R, Nov 20 2014
-#install: /opt/synopsys/J-2014.09-SP2
-#OS: Linux
-#Hostname: depc363
-
-#Implementation: syn_results
-
-<a name=compilerReport1>Synopsys HDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
-@N: : <!@TM:1426603391> | Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-Running on host :depc363
-<a name=compilerReport2>Synopsys VHDL Compiler, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
-@N: : <!@TM:1426603391> | Running in 64-bit mode
-Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1426603391> | Setting time resolution to ns
-@N: : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:12:7:12:23:@N::@XP_MSG">pll_in200_out100.vhd(12)</a><!@TM:1426603391> | Top entity is set to pll_in200_out100.
-VHDL syntax check successful!
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:12:7:12:23:@N:CD630:@XP_MSG">pll_in200_out100.vhd(12)</a><!@TM:1426603391> | Synthesizing work.pll_in200_out100.structure
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:2081:10:2081:17:@N:CD630:@XP_MSG">ecp5um.vhd(2081)</a><!@TM:1426603391> | Synthesizing ecp5um.ehxplll.syn_black_box
-Post processing for ecp5um.ehxplll.syn_black_box
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:830:10:830:13:@N:CD630:@XP_MSG">ecp5um.vhd(830)</a><!@TM:1426603391> | Synthesizing ecp5um.vlo.syn_black_box
-Post processing for ecp5um.vlo.syn_black_box
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:823:10:823:13:@N:CD630:@XP_MSG">ecp5um.vhd(823)</a><!@TM:1426603391> | Synthesizing ecp5um.vhi.syn_black_box
-Post processing for ecp5um.vhi.syn_black_box
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/opt/synopsys/J-2014.09-SP2/lib/lucent/ecp5um.vhd:998:10:998:12:@N:CD630:@XP_MSG">ecp5um.vhd(998)</a><!@TM:1426603391> | Synthesizing ecp5um.ib.syn_black_box
-Post processing for ecp5um.ib.syn_black_box
-Post processing for work.pll_in200_out100.structure
-<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:55:4:55:18:@W:CL168:@XP_MSG">pll_in200_out100.vhd(55)</a><!@TM:1426603391> | Pruning instance scuba_vhi_inst -- not in use ... </font>
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-<a name=compilerReport3>Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
-@N: : <!@TM:1426603391> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:11 2015
-
-###########################################################]
-<a name=compilerReport4>Synopsys Netlist Linker, version comp201409sp2rc, Build 069R, built Nov 20 2014</a>
-@N: : <!@TM:1426603392> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:12 2015
-
-###########################################################]
-Pre-mapping Report
-
-<a name=mapperReport5>Synopsys Lattice Technology Pre-mapping, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55</a>
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Reading constraint file: /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-Linked File: <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt:@XP_FILE">pll_in200_out100_scck.rpt</a>
-Printing clock summary report in "/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100_scck.rpt" file
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426603393> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1426603393> | Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_in200_out100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-<a name=mapperReport6>@S |Clock Summary</a>
-****************
-
-Start Requested Requested Clock Clock
-Clock Frequency Period Type Group
------------------------------------------------------------------
-System 100.0 MHz 10.000 system system_clkgroup
-=================================================================
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 140MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:13 2015
-
-###########################################################]
-Map & Optimize Report
-
-<a name=mapperReport7>Synopsys Lattice Technology Mapper, Version maprc, Build 2453R, Built Nov 20 2014 09:28:55</a>
-Copyright (C) 1994-2014, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-Product Version J-2014.09-SP2
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426603394> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1426603394> | Clock conversion enabled
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-------------------------------------------------------------
-
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1426603394> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)
-
-
-
-<a name=clockReport8>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing Analyst data base /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synwork/pll_in200_out100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-Writing EDIF Netlist and constraint files
-J-2014.09-SP2
-@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1426603394> | Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.vhd:61:4:61:13:@W:MT246:@XP_MSG">pll_in200_out100.vhd(61)</a><!@TM:1426603394> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
-
-
-<a name=timingReport9>@S |##### START OF TIMING REPORT #####[</a>
-# Timing Report written on Tue Mar 17 15:43:14 2015
-#
-
-
-Top view: pll_in200_out100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/pll_in200_out100.fdc
-
-@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1426603394> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
-
-@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1426603394> | Clock constraints cover only FF-to-FF paths associated with the clock.
-
-
-
-<a name=performanceSummary10>Performance Summary </a>
-*******************
-
-
-Worst slack in design: 10.000
-
-@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1426603394> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-@N:<a href="@N:MT582:@XP_HELP">MT582</a> : <!@TM:1426603394> | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
-
-
-
-
-
-<a name=clockRelationships11>Clock Relationships</a>
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-<a name=interfaceInfo12>Interface Information </a>
-*********************
-
-No IO constraint found
-
-
-
-====================================
-<a name=clockReport13>Detailed Report for Clock: System</a>
-====================================
-
-
-
-<a name=startingSlack14>Starting Points with Worst Slack</a>
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKOP CLKOP 0.000 10.000
-==============================================================================
-
-
-<a name=endingSlack15>Ending Points with Worst Slack</a>
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKOP 10.000 10.000
-===============================================================================
-
-
-
-<a name=worstPaths16>Worst Path Information</a>
-<a href="/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srr:srsf/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/pll_in200_out100.srs:fp:16238:16484:@XP_NAMES_GATE">View Worst Path in Analyst</a>
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKOP
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKOP Out 0.000 0.000 -
-CLKOP Net - - - - 2
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-=================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-
-Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)
-
----------------------------------------
-<a name=resourceUsage17>Resource Usage Report</a>
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 1
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-IB: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Mar 17 15:43:14 2015
-
-###########################################################]
-
-</pre></samp></body></html>
+++ /dev/null
- <html>
- <head>
- <script type="text/javascript" src="file:///opt/synopsys/J-2014.09-SP2/lib/report/reportlog_tree.js"></script>
- <link rel="stylesheet" type="text/css" href="file:///opt/synopsys/J-2014.09-SP2/lib/report/reportlog_tree.css" />
- </head>
-
- <body style="background-color:#e0e0ff;">
- <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
- <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
- <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">pll_in200_out100 (syn_results)</b>
- <ul rel="open" style="font-size:small;">
-
-<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
-<ul rel="open">
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>
-<ul rel="open" >
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>
-<ul rel="open" >
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>
-<ul rel="open" >
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a> </li>
-<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>
-<ul >
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#clockReport13" target="srrFrame" title="">Clock: System</a>
-<ul >
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/pll_in200_out100_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
-<li><a href="file:///home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/stdout.log" target="srrFrame" title="">Session Log (15:43 17-Mar)</a>
-<ul ></ul></li> </ul>
- </li>
- </ul>
-
- <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
-
- </body>
- </html>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>
-<!--
- Synopsys, Inc.
- Version J-2014.09-SP2
- Project file /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/syntmp/run_option.xml
- Written on Tue Mar 17 15:43:11 2015
-
-
--->
-<project_attribute_list name="Project Settings">
- <option name="project_name" display_name="Project Name">pll_in200_out100</option>
- <option name="impl_name" display_name="Implementation Name">syn_results</option>
- <option name="top_module" display_name="Top Module">pll_in200_out100</option>
- <option name="pipe" display_name="Pipelining">0</option>
- <option name="retiming" display_name="Retiming">0</option>
- <option name="resource_sharing" display_name="Resource Sharing">1</option>
- <option name="maxfan" display_name="Fanout Guide">50</option>
- <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
- <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
- <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
-</project_attribute_list>
-
+++ /dev/null
-<html>
- <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
- <title>Project Status Summary Page</title>
- <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
- </head>
-
- <body style="background-color:#f0f0ff;">
-
-<table style="border:none;" width="100%" ><tr> <td class="outline">
-<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
- <tr> <td class="optionTitle" align="left"> Project Name</td> <td> pll_in200_out100</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> </tr>
- </thead>
- <tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> pll_in200_out100</td> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
-<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> </tr>
-<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
-
-</tbody>
- </table><br> <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
- <thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
- <tbody>
- <tr>
- <th align="left" width="17%">Job Name</th>
- <th align="left">Status</th>
- <td class="lnote" align="center" title="Notes"></td>
- <td class="lwarn" align="center" title="Warnings"></td>
- <td class="lerror" align="center" title="Errors"></td>
- <th align="left">CPU Time</th>
- <th align="left">Real Time</th>
- <th align="left">Memory</th>
- <th align="left">Date/Time</th>
- </tr>
- <tr>
- <td class="optionTitle"> (compiler)</td><td>Complete</td>
- <td>10</td>
- <td>1</td>
-<td>0</td>
-<td>-</td>
-<td>00m:00s</td>
-<td>-</td>
-<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (premap)</td><td>Complete</td>
- <td>2</td>
-<td>0</td>
-<td>0</td>
-<td>0m:00s</td>
-<td>0m:00s</td>
-<td>140MB</td>
-<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
- <td>11</td>
- <td>1</td>
-<td>0</td>
-<td>0m:01s</td>
-<td>0m:01s</td>
-<td>143MB</td>
-<td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td>
-</tr>
-
-<tr>
- <td class="optionTitle">Multi-srs Generator</td>
- <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">17.03.2015</font><br/><font size="-2">15:43</font></td> </tbody>
- </table>
- <br>
- <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
- <thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
- </tfoot>
- <tbody> <tr>
-<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
-<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>1</td>
-</tr>
-<tr>
-<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
-(v_ram)</td> <td>0</td>
-<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
-(dsp_used)</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
-(total_luts)</td> <td>0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
- <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
- <thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr>
- </tfoot>
-<tbody>
- <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
-<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">10.000</td></tr>
-</tbody>
- </table>
-<br>
- <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
- <thead class="tablehead"><tr><th colspan="4">Optimizations Summary</th></tr></thead>
- <tbody> <tr>
-<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
-<br>
-</td></tr></table></body>
- </html>
\ No newline at end of file
+++ /dev/null
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-# Configuration files used
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+++ /dev/null
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+++ /dev/null
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jspc29 / trbnet.git / commitdiff
