+++ /dev/null
- -- ***************************************************************************
- -- *
- -- MAPS Addon to TRB communication *
- -----------------------------------------------------------------------------*
- -- Version 5.0 *
- -----------------------------------------------------------------------------*
- -- *
- -- The addon should communicate over the LVDS lines with the TRB2 FPGA *
- -- The lines are not LVDS, but TTL - LVCMOS25 *
- -- *
- -- *
- -- R1 - R4 32 bit internal registers *
- -- reg1 - reg4 16 bit internal registers *
- -- ra - rd 1 bit internal registers *
- -- ------------------------------------------------------------------ *
- -- *
- -- *
- -- *
- -- IN/OUT ports use 19 bits each (med_IC) *
- -- *
- -- 0 .. 15 16 17 18 *
- -- DATA RDY CTRL CLK *
- -- *
- -- *
- -- *
- -- xxxxxxxxxxxxxxxxxxxxxx specific xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx*
- -- *
- -- use a reset handler *
- -- *
- -- ***************************************************************************
-
-
-
- LIBRARY ieee;
- use ieee.std_logic_1164.all;
- USE IEEE.numeric_std.ALL;
-
- --USE IEEE.std_logic_UNSIGNED.ALL;
-
- Library UNISIM;
- use UNISIM.vcomponents.all;
-
- library work;
- use work.trb_net_std.all;
- use work.mvd_net.all;
- use work.trb_net_components.all;
- use work.monitor_config.all;
-
-
- entity jcb_trb is
- generic(
- external_trigger : std_logic := '0'
- );
- port(
-
- VIRT_CLK : in std_logic;
- VIRT_CLKb : in std_logic;
-
- RESET_VIRT : in std_logic;
-
- ADO_LV : out std_logic_vector(57 downto 0);
-
- ONEWIRE : inout std_logic;
-
- TLK_CLK : in std_logic;
- TLK_ENABLE : out std_logic;
- TLK_LCKREFN : out std_logic;
- TLK_LOOPEN : out std_logic;
- TLK_PRBSEN : out std_logic;
- TLK_RXD : in std_logic_vector(15 downto 0);
- TLK_RX_CLK : in std_logic;
- TLK_RX_DV : in std_logic;
- TLK_RX_ER : in std_logic;
- TLK_TXD : out std_logic_vector(15 downto 0);
- TLK_TX_EN : out std_logic;
- TLK_TX_ER : out std_logic;
- SFP_LOS : in std_logic;
- SFP_TX_DIS : out std_logic;
-
- DGOOD : out std_logic;
- DINT : out std_logic;
- DBAD : out std_logic;
- DWAIT : out std_logic;
-
- --unused
- FS_PB : out std_logic_vector(17 downto 0);
- FS_PC : inout std_logic_vector(17 downto 0);
- ETRAX_IRQ : out std_logic;
- ADO_TTL : in std_logic_vector(46 downto 0)
-
- -- JTAG1_TMS_OUT : out std_logic;
- -- JTAG1_TCK_OUT : out std_logic;
- -- JTAG1_TDI_OUT : out std_logic;
- -- JTAG1_TDO_IN : in std_logic;
- -- JTAG2_TMS_OUT : out std_logic;
- -- JTAG2_TCK_OUT : out std_logic;
- -- JTAG2_TDI_OUT : out std_logic;
- -- JTAG2_TDO_IN : in std_logic;
- --
- --
- -- JTAG3_TMS_OUT : out std_logic;
- -- JTAG3_TCK_OUT : out std_logic;
- -- JTAG3_TDI_OUT : out std_logic;
- -- JTAG3_TDO_IN : in std_logic;
-
- -- event_trigger : in std_logic;
-
- -- MAPS
- -- MAPS_CLK_out : out std_logic;
- -- MAPS_start_out : out std_logic;
- -- MAPS_reset_out : out std_logic
- );
- end entity;
-
-
-
-
-
-
-
-
-
- architecture basic of jcb_trb is
-
- -- JTAG inputs/outputs
- signal JTAG1_TMS_OUT : std_logic;
- signal JTAG1_TCK_OUT : std_logic;
- signal JTAG1_TDI_OUT : std_logic;
- signal JTAG1_TDO_IN : std_logic;
- signal JTAG2_TMS_OUT : std_logic;
- signal JTAG2_TCK_OUT : std_logic;
- signal JTAG2_TDI_OUT : std_logic;
- signal JTAG2_TDO_IN : std_logic;
-
- signal JTAG3_TMS_OUT : std_logic;
- signal JTAG3_TCK_OUT : std_logic;
- signal JTAG3_TDI_OUT : std_logic;
- signal JTAG3_TDO_IN : std_logic;
-
- signal event_trigger : std_logic;
- -- MAPS outputs
-signal MAPS_CLK1_out : std_logic;
-signal MAPS_CLK2_out : std_logic;
-signal MAPS_CLK3_out : std_logic;
-signal MAPS_CLK1_out_int : std_logic; -- internal signal for ODDR
-signal MAPS_CLK1_out_int2 : std_logic; -- internal signal for ODDR
-signal MAPS_CLK2_out_int : std_logic; -- internal signal for ODDR
-signal MAPS_CLK2_out_int2 : std_logic; -- internal signal for ODDR
-signal MAPS_CLK3_out_int : std_logic; -- internal signal for ODDR
-signal MAPS_CLK3_out_int2 : std_logic; -- internal signal for ODDR
-signal MAPS_start1_out : std_logic;
-signal MAPS_start2_out : std_logic;
-signal MAPS_start3_out : std_logic;
-signal MAPS_reset1_out : std_logic;
-signal MAPS_reset2_out : std_logic;
-signal MAPS_reset3_out : std_logic;
-
-
-
-
- -- the ENDPOINT signals
- signal ep_MED_DATAREADY_OUT : std_logic;
- signal ep_MED_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal ep_MED_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0);
- signal ep_MED_READ_IN : std_logic;
- signal ep_MED_DATAREADY_IN : std_logic;
- signal ep_MED_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal ep_MED_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
- signal ep_MED_READ_OUT : std_logic;
- signal ep_MED_STAT_OP_IN : std_logic_vector(15 downto 0);
- signal ep_MED_CTRL_OP_OUT : std_logic_vector(15 downto 0);
- signal ep_TRG_TIMING_TRG_RECEIVED_IN : std_logic;
- signal ep_LVL1_TRG_DATA_VALID_OUT : std_logic; --trigger type, number, code, information are valid
- signal ep_LVL1_VALID_TIMING_TRG_OUT : std_logic; --valid timing trigger has been received
- signal ep_LVL1_VALID_NOTIMING_TRG_OUT : std_logic; --valid trigger without timing trigger has been received
- signal ep_LVL1_INVALID_TRG_OUT : std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
- signal ep_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
- signal ep_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
- signal ep_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
- signal ep_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
- signal ep_LVL1_INT_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
- signal ep_FEE_TRG_RELEASE_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
- signal ep_FEE_TRG_STATUSBITS_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER*32-1 downto 0);
- signal ep_FEE_DATA_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER*32-1 downto 0);
- signal ep_FEE_DATA_WRITE_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
- signal ep_FEE_DATA_FINISHED_IN : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
- signal ep_FEE_DATA_ALMOST_FULL_OUT : std_logic_vector(c_DATA_INTERFACE_NUMBER-1 downto 0);
- signal ep_REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- signal ep_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal ep_REGIO_COMMON_STAT_STROBE_OUT : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal ep_REGIO_COMMON_CTRL_STROBE_OUT : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal ep_REGIO_STAT_REG_IN : std_logic_vector(2**(c_REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
- signal ep_REGIO_CTRL_REG_OUT : std_logic_vector(2**(c_REGIO_NUM_CTRL_REGS)*32-1 downto 0);
- signal ep_REGIO_STAT_STROBE_OUT : std_logic_vector(2**(c_REGIO_NUM_STAT_REGS)-1 downto 0);
- signal ep_REGIO_CTRL_STROBE_OUT : std_logic_vector(2**(c_REGIO_NUM_CTRL_REGS)-1 downto 0);
- signal ep_BUS_ADDR_OUT : std_logic_vector(16-1 downto 0);
- signal ep_BUS_DATA_OUT : std_logic_vector(32-1 downto 0);
- signal ep_BUS_READ_ENABLE_OUT : std_logic;
- signal ep_BUS_WRITE_ENABLE_OUT : std_logic;
- signal ep_BUS_TIMEOUT_OUT : std_logic;
- signal ep_BUS_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
- signal ep_BUS_DATAREADY_IN : std_logic := '0';
- signal ep_BUS_WRITE_ACK_IN : std_logic := '0';
- signal ep_BUS_NO_MORE_DATA_IN : std_logic := '0';
- signal ep_BUS_UNKNOWN_ADDR_IN : std_logic := '0';
- signal ep_ONEWIRE_INOUT : std_logic; --temperature sensor
- signal ep_ONEWIRE_MONITOR_IN : std_logic := '0';
- signal ep_ONEWIRE_MONITOR_OUT : std_logic;
- signal ep_REGIO_VAR_ENDPOINT_ID : std_logic_vector (15 downto 0) := (others => '0');
- signal ep_TIME_GLOBAL_OUT : std_logic_vector (31 downto 0); --global time, microseconds
- signal ep_TIME_LOCAL_OUT : std_logic_vector ( 7 downto 0); --local time running with chip frequency
- signal ep_TIME_SINCE_LAST_TRG_OUT : std_logic_vector (31 downto 0); --local time, resetted with each trigger
- signal ep_TIME_TICKS_OUT : std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
- signal ep_STAT_DEBUG_IPU : std_logic_vector (31 downto 0);
- signal ep_STAT_DEBUG_1 : std_logic_vector (31 downto 0);
- signal ep_STAT_DEBUG_2 : std_logic_vector (31 downto 0);
- signal ep_STAT_DEBUG_DATA_HANDLER_OUT : std_logic_vector (31 downto 0);
- signal ep_STAT_DEBUG_IPU_HANDLER_OUT : std_logic_vector (31 downto 0);
- signal ep_CTRL_MPLEX : std_logic_vector (31 downto 0) := (others => '0');
- signal ep_IOBUF_CTRL_GEN : std_logic_vector (4*32-1 downto 0) := (others => '0');
- signal ep_STAT_ONEWIRE : std_logic_vector (31 downto 0);
- signal ep_STAT_ADDR_DEBUG : std_logic_vector (15 downto 0);
- signal ep_DEBUG_LVL1_HANDLER_OUT : std_logic_vector (15 downto 0);
-
-
- -- the med IC communicator signals
- signal ic_MED_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal ic_MED_PACKET_NUM_IN : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal ic_MED_DATAREADY_IN : std_logic := '0';
- signal ic_MED_READ_OUT : std_logic := '0';
- signal ic_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal ic_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal ic_MED_DATAREADY_OUT : std_logic := '0';
- signal ic_MED_READ_IN : std_logic := '0';
- signal ic_DATA_OUT : std_logic_vector(15 downto 0) := (others => '0');
- signal ic_DATA_VALID_OUT : std_logic := '0';
- signal ic_DATA_CTRL_OUT : std_logic := '0';
- signal ic_DATA_CLK_OUT : std_logic := '0';
- signal ic_DATA_IN : std_logic_vector(15 downto 0) := (others => '0');
- signal ic_DATA_VALID_IN : std_logic := '0';
- signal ic_DATA_CTRL_IN : std_logic := '0';
- signal ic_DATA_CLK_IN : std_logic := '0';
- signal ic_STAT_OP : std_logic_vector(15 downto 0) := (others => '0');
- signal ic_CTRL_OP : std_logic_vector(15 downto 0) := (others => '0');
- signal ic_STAT_DEBUG : std_logic_vector(63 downto 0) := (others => '0');
-
-
- --MU
- signal mu_REGIO_READ_ENABLE_IN, next_mu_REGIO_READ_ENABLE_IN : std_logic := '0';
- signal mu_REGIO_WRITE_ENABLE_IN : std_logic := '0';
- signal mu_REGIO_ADDR_IN, next_mu_REGIO_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0');
- signal mu_REGIO_DATA_IN : std_logic_vector(31 downto 0);
- signal mu_REGIO_DATA_OUT : std_logic_vector(31 downto 0) := x"0000_0000";
- signal mu_REGIO_DATAREADY_OUT : std_logic := '0';
- signal mu_REGIO_NO_MORE_DATA_OUT : std_logic := '0';
- signal mu_REGIO_WRITE_ACK_OUT : std_logic := '0';
- signal mu_REGIO_UNKNOWN_ADDR_OUT : std_logic := '0';
- signal mu_REGIO_TIMEOUT_IN : std_logic := '0';
- signal mu_FIFO_DATA_IN, next_mu_FIFO_DATA_IN : std_logic_vector( (FIFO_BUS*FIFO_NUM)-1 downto 0 ) := (others => '0');
- signal mu_REG_DATA_IN, next_mu_REG_DATA_IN : std_logic_vector( (REG_BUS*REG_NUM)-1 downto 0 ) := (others => '0');
- signal mu_HW_TRIGGER_IN, next_mu_HW_TRIGGER_IN : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
- signal mu_GLOBAL_TIME_IN : std_logic_vector(31 downto 0) := (others => '0');
- signal mu_LOCAL_TIME_IN : std_logic_vector(7 downto 0) := (others => '0');
- signal mu_TRIGGER_TIME_IN : std_logic_vector(31 downto 0) := (others => '0');
- signal mu_EVENT_NUMBER_IN : std_logic_vector(7 downto 0) := (others => '0');
-
-
-
-
- -- Main signals
- signal CLK : std_logic := '0';
- signal RESET : std_logic := '1';
--- signal soft_reset, next_soft_reset : std_logic := '0';
-
-
-
-
- --attribute syn_keep : boolean;
- --attribute syn_keep of next_testsignal : signal is true;
-
--- COM_SETTINGS signals: for settings in this entity
-signal com_settings_addr_in : std_logic_vector(7 downto 0);
-signal com_settings_data_in : std_logic_vector(31 downto 0);
-signal com_settings_read_enable_in : std_logic;
-signal com_settings_write_enable_in : std_logic;
-signal com_settings_data_out : std_logic_vector(31 downto 0);
-signal com_settings_dataready_out : std_logic;
-signal com_settings_write_ack_out : std_logic;
-signal com_settings_no_more_data_out : std_logic;
-signal com_settings_unknown_addr_out : std_logic;
-signal signals_invert : std_logic_vector(13 downto 0);
-signal signals_invert2 : std_logic_vector(13 downto 0);
-signal signals_invert3 : std_logic_vector(13 downto 0);
-signal waitbeforestart : std_logic_vector(31 downto 0);
-signal beforestartcounter, beforestartcounter_next : std_logic_vector(31 downto 0);
-constant beforestartcounter_zero : std_logic_vector(31 downto 0) := (others => '0');
-signal beforestartcounter_finished, beforestartcounter_finished_next : std_logic;
-signal beforestartcounter_finished_last, beforestartcounter_finished_last_next : std_logic;
-
-signal fet_counter_limit : std_logic_vector(31 downto 0);
-signal jcounter_initvalue : std_logic_vector(28 downto 0); --29 bit
-signal trbnet_fet : std_logic;
--- JTAG_CMD_M26C connection signals
-signal jtag_cmd_m26c_addr_in : std_logic_vector(8 downto 0);
-signal jtag_cmd_m26c_data_in : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_read_enable_in : std_logic;
-signal jtag_cmd_m26c_write_enable_in : std_logic;
-signal jtag_cmd_m26c_data_out : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_dataready_out : std_logic;
-signal jtag_cmd_m26c_write_ack_out : std_logic;
-signal jtag_cmd_m26c_no_more_data_out : std_logic;
-signal jtag_cmd_m26c_unknown_addr_out : std_logic;
-signal jtag_tck : std_logic;
-signal jtag_tms : std_logic;
-signal jtag_tdi : std_logic;
-signal jtag_tdo_evtlinv : std_logic;
--- second JTAG entity
-signal jtag_cmd_m26c_addr_in2 : std_logic_vector(8 downto 0);
-signal jtag_cmd_m26c_data_in2 : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_read_enable_in2 : std_logic;
-signal jtag_cmd_m26c_write_enable_in2 : std_logic;
-signal jtag_cmd_m26c_data_out2 : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_dataready_out2 : std_logic;
-signal jtag_cmd_m26c_write_ack_out2 : std_logic;
-signal jtag_cmd_m26c_no_more_data_out2 : std_logic;
-signal jtag_cmd_m26c_unknown_addr_out2 : std_logic;
-signal jtag_tck2 : std_logic;
-signal jtag_tms2 : std_logic;
-signal jtag_tdi2 : std_logic;
-signal jtag_tdo_evtlinv2 : std_logic;
--- third JTAG entity
-signal jtag_cmd_m26c_addr_in3 : std_logic_vector(8 downto 0);
-signal jtag_cmd_m26c_data_in3 : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_read_enable_in3 : std_logic;
-signal jtag_cmd_m26c_write_enable_in3 : std_logic;
-signal jtag_cmd_m26c_data_out3 : std_logic_vector(31 downto 0);
-signal jtag_cmd_m26c_dataready_out3 : std_logic;
-signal jtag_cmd_m26c_write_ack_out3 : std_logic;
-signal jtag_cmd_m26c_no_more_data_out3 : std_logic;
-signal jtag_cmd_m26c_unknown_addr_out3 : std_logic;
-signal jtag_tck3 : std_logic;
-signal jtag_tms3 : std_logic;
-signal jtag_tdi3 : std_logic;
-signal jtag_tdo_evtlinv3 : std_logic;
-
-
--- JTAG stuff
-signal jcounter, jcounter_next : std_logic_vector(28 downto 0); --29 bit
-signal off_spill, off_spill_next : std_logic;
-signal fake_event_trigger, fake_event_trigger_next : std_logic;
-signal fet_counter, fet_counter_next : std_logic_vector (31 downto 0); -- 32 bit
-signal my_status : std_logic_vector(8 downto 0);
-signal idle_out : std_logic;
-signal idle_out2 : std_logic;
-signal idle_out3 : std_logic;
-
-signal prog_jtag_finished : std_logic;
-
-signal prog_jtag_finished2 : std_logic;
-
-signal prog_jtag_finished3 : std_logic;
-
--- spill trigger rising edge detection
-signal event_trigger_ff, event_trigger_ff_next : std_logic;
-signal event_trigger_ff_last, event_trigger_ff_last_next : std_logic;
-signal spillbreak_trigger : std_logic;
--- spill trigger rising edge detection (MAPS_CLK)
-signal event_trigger_ff_MAPS_CLK, event_trigger_ff_MAPS_CLK_next : std_logic;
-signal event_trigger_ff_last_MAPS_CLK, event_trigger_ff_last_MAPS_CLK_next : std_logic;
-signal spillbreak_trigger_MAPS_CLK : std_logic;
--- JTAG finished edge detection
-signal prog_jtag_finished_ff_MAPS_CLK, prog_jtag_finished_ff_MAPS_CLK_next : std_logic;
-signal prog_jtag_finished_ff_last_MAPS_CLK, prog_jtag_finished_ff_last_MAPS_CLK_next : std_logic;
-signal prog_jtag_finished_pulse_MAPS_CLK, prog_jtag_finished_pulse_MAPS_CLK_next : std_logic;
--- MAPS outputs (reset, start)
-signal MAPS_CLK : std_logic;
-signal MAPS_reset, MAPS_reset_next : std_logic;
-signal MAPS_reset_count, MAPS_reset_count_next : std_logic_vector(6 downto 0);
-signal MAPS_start, MAPS_start_next : std_logic;
-signal MAPS_start_count, MAPS_start_count_next : std_logic_vector(6 downto 0);
-
- -- TrbNet Reset Handler
- signal reset_CLEAR_IN : std_logic := '0'; -- reset input (high active, async)
- signal reset_CLEAR_N_IN : std_logic := '0'; -- reset input (low active, async)
- signal reset_CLK_IN : std_logic := '0'; -- raw master clock, NOT from PLL/DLL!
- signal reset_SYSCLK_IN : std_logic := '0'; -- PLL/DLL remastered clock
- signal reset_PLL_LOCKED_IN : std_logic := '0'; -- master PLL lock signal (async)
- signal reset_RESET_IN : std_logic := '0'; -- general reset signal (SYSCLK)
- signal reset_TRB_RESET_IN : std_logic := '0'; -- TRBnet reset signal (SYSCLK)
- signal reset_CLEAR_OUT : std_logic := '0'; -- async reset out, USE WITH CARE!
- signal reset_RESET_OUT : std_logic := '0'; -- synchronous reset out (SYSCLK)
- signal reset_DEBUG_OUT : std_logic_vector(15 downto 0) := x"0000";
-
-
-component jtag_cmd_m26c is
- port(
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- JTAG_TMS_OUT : out std_logic;
- JTAG_TCK_OUT : out std_logic;
- JTAG_TDI_OUT : out std_logic;
- JTAG_TDO_IN : in std_logic;
-
- BUS_DATA_IN : in std_logic_vector(31 downto 0);
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);
- BUS_ADDR_IN : in std_logic_vector(8 downto 0);
- BUS_READ_IN : in std_logic;
- BUS_WRITE_IN : in std_logic;
-
- BUS_DATAREADY_OUT : out std_logic;
- BUS_NO_MORE_DATA_OUT : out std_logic;
- BUS_WRITE_ACK_OUT : out std_logic;
- BUS_UNKNOWN_ADDR_OUT : out std_logic;
-
- OFF_SPILL_IN : in std_logic;
- MY_STATUS_OUT : out std_logic_vector(8 downto 0);
- --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
- --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
- IDLE_OUT : out std_logic;
- PROG_JTAG_FINISHED_OUT:out std_logic
- --BUS_TIMEOUT_IN : in std_logic;
- );
-end component;
-
- COMPONENT dcm3
- PORT(
- CLKIN_IN : IN std_logic;
- RST_IN : IN std_logic;
- CLKFX_OUT : OUT std_logic;
- CLK0_OUT : OUT std_logic;
- LOCKED_OUT : OUT std_logic
- );
- END COMPONENT;
-
-
-
-begin
-ETRAX_IRQ <= '1';
-
---inputs/outputs
-MAPS_reset_OBUFDS1 : OBUFDS
-port map (
- I => MAPS_reset1_out,
- O => ADO_LV(2),
- OB=> ADO_LV(3)
-);
-MAPS_start_OBUFDS1 : OBUFDS
-port map (
- I => MAPS_start1_out,
- O => ADO_LV(4),
- OB=> ADO_LV(5)
-);
-MAPS_CLK_OBUFDS1 : OBUFDS
-port map (
- I => MAPS_CLK1_out,
- O => ADO_LV(6),
- OB=> ADO_LV(7)
-);
-
-jtag1_tck_OBUFDS : OBUFDS
-port map (
- I => JTAG1_TCK_OUT,
- O => ADO_LV(8),
- OB=> ADO_LV(9)
-);
-jtag1_tdi_OBUFDS : OBUFDS
-port map (
- I => JTAG1_TDI_OUT,
- O => ADO_LV(10),
- OB=> ADO_LV(11)
-);
-jtag1_tms_OBUFDS : OBUFDS
-port map (
- I => JTAG1_TMS_OUT,
- O => ADO_LV(12),
- OB=> ADO_LV(13)
-);
-
-
-MAPS_reset_OBUFDS2 : OBUFDS
-port map (
- I => MAPS_reset2_out,
- O => ADO_LV(18),
- OB=> ADO_LV(19)
-);
-MAPS_start_OBUFDS2 : OBUFDS
-port map (
- I => MAPS_start2_out,
- O => ADO_LV(20),
- OB=> ADO_LV(21)
-);
-MAPS_CLK_OBUFDS2 : OBUFDS
-port map (
- I => MAPS_CLK2_out,
- O => ADO_LV(22),
- OB=> ADO_LV(23)
-);
-
-jtag2_tms_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TMS_OUT,
- O => ADO_LV(24),
- OB=> ADO_LV(25)
-);
-jtag2_tck_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TCK_OUT,
- O => ADO_LV(26),
- OB=> ADO_LV(27)
-);
-jtag2_tdi_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TDI_OUT,
- O => ADO_LV(28),
- OB=> ADO_LV(29)
-);
-
-MAPS_reset_OBUFDS3 : OBUFDS
-port map (
- I => MAPS_reset3_out,
- O => ADO_LV(34),
- OB=> ADO_LV(35)
-);
-MAPS_start_OBUFDS3 : OBUFDS
-port map (
- I => MAPS_start3_out,
- O => ADO_LV(36),
- OB=> ADO_LV(37)
-);
-MAPS_CLK_OBUFDS3 : OBUFDS
-port map (
- I => MAPS_CLK3_out,
- O => ADO_LV(38),
- OB=> ADO_LV(39)
-);
-
-jtag3_tms_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TMS_OUT,
- O => ADO_LV(40),
- OB=> ADO_LV(41)
-);
-jtag3_tck_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TCK_OUT,
- O => ADO_LV(42),
- OB=> ADO_LV(43)
-);
-jtag3_tdi_OBUFDS : OBUFDS
-port map (
- I => JTAG2_TDI_OUT,
- O => ADO_LV(44),
- OB=> ADO_LV(45)
-);
-
---ADO_LV(1 downto 0) <= (others => '0');
---ADO_LV(17 downto 14) <= (others => '0');
---ADO_LV(33 downto 30) <= (others => '0');
---ADO_LV(57 downto 46) <= (others => '0');
-
-unused1 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(0),
- OB=> ADO_LV(1)
-);
-
-unused2 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(14),
- OB=> ADO_LV(15)
-);
-unused3 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(16),
- OB=> ADO_LV(17)
-);
-unused4 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(30),
- OB=> ADO_LV(31)
-);
-unused5 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(32),
- OB=> ADO_LV(33)
-);
-unused6 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(46),
- OB=> ADO_LV(47)
-);
-unused7 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(48),
- OB=> ADO_LV(49)
-);
-unused8 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(50),
- OB=> ADO_LV(51)
-);
-unused9 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(52),
- OB=> ADO_LV(53)
-);
-unused10 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(54),
- OB=> ADO_LV(55)
-);
-unused11 : OBUFDS
-port map (
- I => '0',
- O => ADO_LV(56),
- OB=> ADO_LV(57)
-);
-
-
-
-JTAG1_TDO_IN <= ADO_TTL(16);
-JTAG2_TDO_IN <= ADO_TTL(17);
-JTAG3_TDO_IN <= ADO_TTL(18);
-
-event_trigger <= ADO_TTL(19);
-
-
-
- ---------------------------------------------------------------------
- -- CLK generator
- ---------------------------------------------------------------------
- the_IBUFGDS : IBUFGDS
- generic map (
- DIFF_TERM => TRUE,
- IOSTANDARD => "LVDS_25"
- )
- port map (
- O => CLK,
- I => VIRT_CLK,
- IB => VIRT_CLKb
- );
-
-
-
-
-
-
--- ---------------------------------------------------------------------
--- -- FIFO
--- ---------------------------------------------------------------------
--- the_xilinx_BRAM_FIFO_16x1024_1: xilinx_BRAM_FIFO_16x1024
--- port map(
--- clk => CLK,
--- din => fifo_din1,
--- rd_en => fifo_rd_en1,
--- rst => RESET,
--- wr_en => fifo_wr_en1,
--- data_count => fifo_data_count1,
--- dout => fifo_dout1,
--- empty => fifo_empty1,
--- full => fifo_full1,
--- valid => fifo_valid1
--- );
---
---
--- ---------------------------------------------------------------------
--- -- FIFO
--- ---------------------------------------------------------------------
--- the_xilinx_BRAM_FIFO_16x1024_2: xilinx_BRAM_FIFO_16x1024
--- port map(
--- clk => CLK,
--- din => fifo_din2,
--- rd_en => fifo_rd_en2,
--- rst => RESET,
--- wr_en => fifo_wr_en2,
--- data_count => fifo_data_count2,
--- dout => fifo_dout2,
--- empty => fifo_empty2,
--- full => fifo_full2,
--- valid => fifo_valid2
--- );
---
-
--- ---------------------------------------------------------------------
--- -- RESET Handler
--- ---------------------------------------------------------------------
--- the_reset_handler: reset_handler_b
--- generic map(
--- RESET_DELAY => x"000f"
--- )
--- port map(
--- CLK => CLK,
--- RESET_IN => soft_reset,
--- TRB_RESET_IN => not RESET_VIRT,
--- EXTERNAL_RESET_IN => '0',
--- RESET_COUNTER_IN => x"00000000",
--- RESET_OUT => RESET
--- );
--- -- next_soft_reset <= ic_STAT_OP(13);
--- -- next_ttl_obuf(16) <= soft_reset;
- ----------------------------------------------------------------------------------------------------------------------------------------
- -- Reset Handler
- ----------------------------------------------------------------------------------------------------------------------------------------
- the_trb_net_reset_handler: trb_net_reset_handler
- generic map(
- RESET_DELAY => x"000f"
- )
- port map(
- CLEAR_IN => reset_CLEAR_IN, -- reset input (high active, async)
- CLEAR_N_IN => reset_CLEAR_N_IN, -- reset input (low active, async)
- CLK_IN => reset_CLK_IN, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => reset_SYSCLK_IN, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => reset_PLL_LOCKED_IN,-- master PLL lock signal (async)
- RESET_IN => reset_RESET_IN, -- general reset signal (SYSCLK)
- TRB_RESET_IN => reset_TRB_RESET_IN, -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => reset_CLEAR_OUT, -- async reset out, USE WITH CARE!
- RESET_OUT => RESET, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => reset_DEBUG_OUT
- );
- reset_CLK_IN <= CLK;
- reset_SYSCLK_IN <= CLK;
- reset_CLEAR_IN <= '0';
- reset_CLEAR_N_IN <= '1';
- reset_PLL_LOCKED_IN <= '1';
- reset_RESET_IN <= ep_MED_STAT_OP_IN(13);
-
-
- the_med_tlk: trb_net16_med_tlk
- port map(
- RESET => RESET, -- which reset should be used?
- CLK => CLK,
- TLK_CLK => TLK_CLK,
- TLK_ENABLE => TLK_ENABLE,
- TLK_LCKREFN => TLK_LCKREFN,
- TLK_LOOPEN => TLK_LOOPEN,
- TLK_PRBSEN => TLK_PRBSEN,
- TLK_RXD => TLK_RXD,
- TLK_RX_CLK => TLK_RX_CLK,
- TLK_RX_DV =>TLK_RX_DV,
- TLK_RX_ER => TLK_RX_ER,
- TLK_TXD => TLK_TXD,
- TLK_TX_EN => TLK_TX_EN,
- TLK_TX_ER => TLK_TX_ER,
- SFP_LOS => SFP_LOS,
- SFP_TX_DIS => SFP_TX_DIS,
- MED_DATAREADY_IN => ep_MED_DATAREADY_OUT,
- MED_READ_IN => ep_MED_READ_OUT,
- MED_DATA_IN => ep_MED_DATA_OUT,
- MED_PACKET_NUM_IN => ep_MED_PACKET_NUM_OUT,
- MED_DATAREADY_OUT => ep_MED_DATAREADY_IN,
- MED_READ_OUT => ep_MED_READ_IN,
- MED_DATA_OUT => ep_MED_DATA_IN,
- MED_PACKET_NUM_OUT=> ep_MED_PACKET_NUM_IN,
- STAT => open,
- STAT_MONITOR => open,
- STAT_OP => ep_MED_STAT_OP_IN,
- CTRL_OP => ep_MED_CTRL_OP_OUT
- --connect STAT(0) to LED
- );
-
-
-
--- the_reg_sync : reg_sync
--- port map(
---
--- CLK => CLK,
--- RESET => '0',
---
--- CLK_SLOW => sync_clk_in,
--- CLK_OUT => sync_ddr_out,
---
--- DATA_IN_SLOW => sync_data_in2,
--- VALID_IN_SLOW => sync_valid_in2,
--- PACKET_NUM_IN_SLOW => sync_packet_num_in2,
--- READ_IN_SLOW => sync_read_in2,
---
--- DATA_IN_FAST => sync_data_in1,
--- VALID_IN_FAST => sync_valid_in1,
--- PACKET_NUM_IN_FAST => sync_packet_num_in1,
--- READ_IN_FAST => sync_read_in1,
---
--- DATA_OUT_SLOW => sync_data_out2,
--- VALID_OUT_SLOW => sync_valid_out2,
--- PACKET_NUM_OUT_SLOW => sync_packet_num_out2,
--- READ_OUT_SLOW => sync_read_out2,
---
--- DATA_OUT_FAST => sync_data_out1,
--- VALID_OUT_FAST => sync_valid_out1,
--- PACKET_NUM_OUT_FAST => sync_packet_num_out1,
--- READ_OUT_FAST => sync_read_out1
---
--- );
--- ep_MED_READ_IN <= sync_read_out2;
--- ep_MED_DATA_IN <= sync_data_out2;
--- ep_MED_DATAREADY_IN <= sync_valid_out2;
--- ep_MED_PACKET_NUM_IN <= sync_packet_num_out2;
---
--- sync_data_in1 <= ep_MED_DATA_OUT;
--- sync_valid_in1 <= ep_MED_DATAREADY_OUT;
--- sync_packet_num_in1 <= ep_MED_PACKET_NUM_OUT;
--- sync_read_in1 <= ep_MED_READ_OUT;
----- sync_data_in1 <= ep_testdata;
----- sync_valid_in1 <= ep_testvalid;
----- sync_packet_num_in1 <= ep_testpacket;
----- sync_read_in1 <= ep_testread;
----- sync_data_in1 <= testsignal(15 downto 0);
----- sync_valid_in1 <= testsignal(16);
----- sync_packet_num_in1 <= testsignal(19 downto 17);
----- sync_read_in1 <= testsignal(20);
-
-
-
- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- -- The Endpoint
- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
- the_ENDPOINT: trb_net16_endpoint_hades_full_handler
- generic map(
- IBUF_DEPTH => (6,6,6,6),
- FIFO_TO_INT_DEPTH => (6,6,6,6),
- FIFO_TO_APL_DEPTH => (6,6,6,6),
- APL_WRITE_ALL_WORDS => (c_NO,c_NO,c_NO,c_NO),
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"FF",
- REGIO_NUM_STAT_REGS => c_REGIO_NUM_STAT_REGS,
- REGIO_NUM_CTRL_REGS => c_REGIO_NUM_CTRL_REGS,
- REGIO_INIT_CTRL_REGS => (others => '0'),
- REGIO_INIT_ADDRESS => x"F013",
- REGIO_INIT_BOARD_INFO => x"1234_5678",
- REGIO_INIT_ENDPOINT_ID => x"1234",
- REGIO_COMPILE_TIME => x"00000000",
- REGIO_COMPILE_VERSION => x"0005",
- REGIO_HARDWARE_VERSION => x"12345678",
- REGIO_USE_1WIRE_INTERFACE => c_YES,
- REGIO_USE_VAR_ENDPOINT_ID => c_NO,
- CLOCK_FREQUENCY => 100,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => c_DATA_INTERFACE_NUMBER,
- DATA_BUFFER_DEPTH => 9,
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**8,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**8
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => '1',
-
- -- Media direction port
- MED_DATAREADY_OUT => ep_MED_DATAREADY_OUT,
- MED_DATA_OUT => ep_MED_DATA_OUT,
- MED_PACKET_NUM_OUT => ep_MED_PACKET_NUM_OUT,
- MED_READ_IN => ep_MED_READ_IN,
- MED_DATAREADY_IN => ep_MED_DATAREADY_IN,
- MED_DATA_IN => ep_MED_DATA_IN,
- MED_PACKET_NUM_IN => ep_MED_PACKET_NUM_IN,
- MED_READ_OUT => ep_MED_READ_OUT,
- MED_STAT_OP_IN => ep_MED_STAT_OP_IN,
- MED_CTRL_OP_OUT => ep_MED_CTRL_OP_OUT,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => ep_TRG_TIMING_TRG_RECEIVED_IN,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => ep_LVL1_TRG_DATA_VALID_OUT, --trigger type, number, code, information are valid
- LVL1_VALID_TIMING_TRG_OUT => ep_LVL1_VALID_TIMING_TRG_OUT, --valid timing trigger has been received
- LVL1_VALID_NOTIMING_TRG_OUT => ep_LVL1_VALID_NOTIMING_TRG_OUT, --valid trigger without timing trigger has been received
- LVL1_INVALID_TRG_OUT => ep_LVL1_INVALID_TRG_OUT, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
- LVL1_TRG_TYPE_OUT => ep_LVL1_TRG_TYPE_OUT,
- LVL1_TRG_NUMBER_OUT => ep_LVL1_TRG_NUMBER_OUT,
- LVL1_TRG_CODE_OUT => ep_LVL1_TRG_CODE_OUT,
- LVL1_TRG_INFORMATION_OUT => ep_LVL1_TRG_INFORMATION_OUT,
- LVL1_INT_TRG_NUMBER_OUT => ep_LVL1_INT_TRG_NUMBER_OUT, --internally generated trigger number, for informational uses only
-
- --Response from FEE
- FEE_TRG_RELEASE_IN => ep_FEE_TRG_RELEASE_IN,
- FEE_TRG_STATUSBITS_IN => ep_FEE_TRG_STATUSBITS_IN,
- FEE_DATA_IN => ep_FEE_DATA_IN,
- FEE_DATA_WRITE_IN => ep_FEE_DATA_WRITE_IN,
- FEE_DATA_FINISHED_IN => ep_FEE_DATA_FINISHED_IN,
- FEE_DATA_ALMOST_FULL_OUT => ep_FEE_DATA_ALMOST_FULL_OUT,
-
- --Slow Control Port
- --common registers
- REGIO_COMMON_STAT_REG_IN => ep_REGIO_COMMON_STAT_REG_IN,
- REGIO_COMMON_CTRL_REG_OUT => ep_REGIO_COMMON_CTRL_REG_OUT,
- REGIO_COMMON_STAT_STROBE_OUT => ep_REGIO_COMMON_STAT_STROBE_OUT,
- REGIO_COMMON_CTRL_STROBE_OUT => ep_REGIO_COMMON_CTRL_STROBE_OUT,
- --user defined registers
- REGIO_STAT_REG_IN => ep_REGIO_STAT_REG_IN,
- REGIO_CTRL_REG_OUT => ep_REGIO_CTRL_REG_OUT,
- REGIO_STAT_STROBE_OUT => ep_REGIO_STAT_STROBE_OUT,
- REGIO_CTRL_STROBE_OUT => ep_REGIO_CTRL_STROBE_OUT,
- --internal data port
- BUS_ADDR_OUT => ep_BUS_ADDR_OUT,
- BUS_DATA_OUT => ep_BUS_DATA_OUT,
- BUS_READ_ENABLE_OUT => ep_BUS_READ_ENABLE_OUT,
- BUS_WRITE_ENABLE_OUT => ep_BUS_WRITE_ENABLE_OUT,
- BUS_TIMEOUT_OUT => ep_BUS_TIMEOUT_OUT,
- BUS_DATA_IN => ep_BUS_DATA_IN,
- BUS_DATAREADY_IN => ep_BUS_DATAREADY_IN,
- BUS_WRITE_ACK_IN => ep_BUS_WRITE_ACK_IN,
- BUS_NO_MORE_DATA_IN => ep_BUS_NO_MORE_DATA_IN,
- BUS_UNKNOWN_ADDR_IN => ep_BUS_UNKNOWN_ADDR_IN,
- --Onewire
- ONEWIRE_INOUT => ONEWIRE, --temperature sensor
- ONEWIRE_MONITOR_IN => ep_ONEWIRE_MONITOR_IN,
- ONEWIRE_MONITOR_OUT => ep_ONEWIRE_MONITOR_OUT,
- --Config endpoint id, if not statically assigned
- REGIO_VAR_ENDPOINT_ID => ep_REGIO_VAR_ENDPOINT_ID,
-
- --Timing registers
- TIME_GLOBAL_OUT => ep_TIME_GLOBAL_OUT, --global time, microseconds
- TIME_LOCAL_OUT => ep_TIME_LOCAL_OUT, --local time running with chip frequency
- TIME_SINCE_LAST_TRG_OUT => ep_TIME_SINCE_LAST_TRG_OUT, --local time, resetted with each trigger
- TIME_TICKS_OUT => ep_TIME_TICKS_OUT, --bit 1 ms-tick, 0 us-tick
-
- --Debugging & Status information
- STAT_DEBUG_IPU => ep_STAT_DEBUG_IPU,
- STAT_DEBUG_1 => ep_STAT_DEBUG_1,
- STAT_DEBUG_2 => ep_STAT_DEBUG_2,
- STAT_DEBUG_DATA_HANDLER_OUT => ep_STAT_DEBUG_DATA_HANDLER_OUT,
- STAT_DEBUG_IPU_HANDLER_OUT => ep_STAT_DEBUG_IPU_HANDLER_OUT,
- CTRL_MPLEX => ep_CTRL_MPLEX,
- IOBUF_CTRL_GEN => ep_IOBUF_CTRL_GEN,
- STAT_ONEWIRE => ep_STAT_ONEWIRE,
- STAT_ADDR_DEBUG => ep_STAT_ADDR_DEBUG,
- DEBUG_LVL1_HANDLER_OUT => ep_DEBUG_LVL1_HANDLER_OUT
- );
-
-
-
-the_bus_handler : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 5,
- PORT_ADDRESSES => (0 => x"b000", 1 => x"8000", 2 => x"c000", 3 => x"d000", 4 => x"e000", others => (others => '0')),
- PORT_ADDR_MASK => (0 => 9, 1 => 10, 2 => 8, 3 => 9, 4 => 9, others => 0)
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- DAT_ADDR_IN => ep_BUS_ADDR_OUT,
- DAT_DATA_IN => ep_BUS_DATA_OUT, -- data from TRB endpoint
- DAT_DATA_OUT => ep_BUS_DATA_IN, -- data to TRB endpoint
- DAT_READ_ENABLE_IN => ep_BUS_READ_ENABLE_OUT, -- read pulse
- DAT_WRITE_ENABLE_IN => ep_BUS_WRITE_ENABLE_OUT, -- write pulse
- DAT_TIMEOUT_IN => ep_BUS_TIMEOUT_OUT, -- access timed out
- DAT_DATAREADY_OUT => ep_BUS_DATAREADY_IN, -- your data, master, as requested
- DAT_WRITE_ACK_OUT => ep_BUS_WRITE_ACK_IN, -- data accepted
- DAT_NO_MORE_DATA_OUT => ep_BUS_NO_MORE_DATA_IN, -- don't disturb me now
- DAT_UNKNOWN_ADDR_OUT => ep_BUS_UNKNOWN_ADDR_IN, -- noone here to answer your request
-
- --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => jtag_cmd_m26c_addr_in,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+9 downto 1*16) => open,
- BUS_ADDR_OUT(1*16+15 downto 1*16+10) => open,
- BUS_ADDR_OUT(2*16+7 downto 2*16) => com_settings_addr_in,
- BUS_ADDR_OUT(2*16+15 downto 2*16+8) => open,
- BUS_ADDR_OUT(3*16+8 downto 3*16) => jtag_cmd_m26c_addr_in2,
- BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
- BUS_ADDR_OUT(4*16+8 downto 4*16) => jtag_cmd_m26c_addr_in3,
- BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
- --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
- BUS_DATA_OUT(0*32+31 downto 0*32) => jtag_cmd_m26c_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => open,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+31 downto 2*32) => com_settings_data_in,
- BUS_DATA_OUT(3*32+31 downto 3*32) => jtag_cmd_m26c_data_in2,
- BUS_DATA_OUT(4*32+31 downto 4*32) => jtag_cmd_m26c_data_in3,
- BUS_READ_ENABLE_OUT(0) => jtag_cmd_m26c_read_enable_in,
- BUS_READ_ENABLE_OUT(1) => open,
- BUS_READ_ENABLE_OUT(2) => com_settings_read_enable_in,
- BUS_READ_ENABLE_OUT(3) => jtag_cmd_m26c_read_enable_in2,
- BUS_READ_ENABLE_OUT(4) => jtag_cmd_m26c_read_enable_in3,
- BUS_WRITE_ENABLE_OUT(0) => jtag_cmd_m26c_write_enable_in,
- BUS_WRITE_ENABLE_OUT(1) => open,
- BUS_WRITE_ENABLE_OUT(2) => com_settings_write_enable_in,
- BUS_WRITE_ENABLE_OUT(3) => jtag_cmd_m26c_write_enable_in2,
- BUS_WRITE_ENABLE_OUT(4) => jtag_cmd_m26c_write_enable_in3,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_TIMEOUT_OUT(4) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => jtag_cmd_m26c_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32) => (others => '0'),
- BUS_DATA_IN(2*32+31 downto 2*32) => com_settings_data_out,
- BUS_DATA_IN(3*32+31 downto 3*32) => jtag_cmd_m26c_data_out2,
- BUS_DATA_IN(4*32+31 downto 4*32) => jtag_cmd_m26c_data_out3,
- BUS_DATAREADY_IN(0) => jtag_cmd_m26c_dataready_out,
- BUS_DATAREADY_IN(1) => '0',
- BUS_DATAREADY_IN(2) => com_settings_dataready_out,
- BUS_DATAREADY_IN(3) => jtag_cmd_m26c_dataready_out2,
- BUS_DATAREADY_IN(4) => jtag_cmd_m26c_dataready_out3,
- BUS_WRITE_ACK_IN(0) => jtag_cmd_m26c_write_ack_out,
- BUS_WRITE_ACK_IN(1) => '0',
- BUS_WRITE_ACK_IN(2) => com_settings_write_ack_out,
- BUS_WRITE_ACK_IN(3) => jtag_cmd_m26c_write_ack_out2,
- BUS_WRITE_ACK_IN(4) => jtag_cmd_m26c_write_ack_out3,
- BUS_NO_MORE_DATA_IN(0) => jtag_cmd_m26c_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => com_settings_no_more_data_out,
- BUS_NO_MORE_DATA_IN(3) => jtag_cmd_m26c_no_more_data_out2,
- BUS_NO_MORE_DATA_IN(4) => jtag_cmd_m26c_no_more_data_out3,
- BUS_UNKNOWN_ADDR_IN(0) => jtag_cmd_m26c_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => com_settings_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(3) => jtag_cmd_m26c_unknown_addr_out2,
- BUS_UNKNOWN_ADDR_IN(4) => jtag_cmd_m26c_unknown_addr_out3,
-
-
-
-
-
- STAT_DEBUG => open
- );
-
-
-the_jtag3_cmd_m26c : jtag_cmd_m26c
- port map(
- CLK_IN => CLK,
- RESET_IN => RESET,
-
- JTAG_TMS_OUT => jtag_tms3,
- JTAG_TCK_OUT => jtag_tck3,
- JTAG_TDI_OUT => jtag_tdi3,
- JTAG_TDO_IN => jtag_tdo_evtlinv3,
-
- BUS_DATA_IN => jtag_cmd_m26c_data_in3,
- BUS_DATA_OUT => jtag_cmd_m26c_data_out3,
- BUS_ADDR_IN => jtag_cmd_m26c_addr_in3(8 downto 0),
- BUS_READ_IN => jtag_cmd_m26c_read_enable_in3,
- BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in3,
-
- BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out3,
- BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out3,
- BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out3,
- BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out3,
-
- OFF_SPILL_IN => off_spill,
- MY_STATUS_OUT => open,
- IDLE_OUT => idle_out3,
- --BUS_TIMEOUT_IN : in std_logic;
- PROG_JTAG_FINISHED_OUT => prog_jtag_finished3
- );
-the_jtag2_cmd_m26c : jtag_cmd_m26c
- port map(
- CLK_IN => CLK,
- RESET_IN => RESET,
-
- JTAG_TMS_OUT => jtag_tms2,
- JTAG_TCK_OUT => jtag_tck2,
- JTAG_TDI_OUT => jtag_tdi2,
- JTAG_TDO_IN => jtag_tdo_evtlinv2,
-
- BUS_DATA_IN => jtag_cmd_m26c_data_in2,
- BUS_DATA_OUT => jtag_cmd_m26c_data_out2,
- BUS_ADDR_IN => jtag_cmd_m26c_addr_in2(8 downto 0),
- BUS_READ_IN => jtag_cmd_m26c_read_enable_in2,
- BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in2,
-
- BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out2,
- BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out2,
- BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out2,
- BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out2,
-
- OFF_SPILL_IN => off_spill,
- MY_STATUS_OUT => open,
- IDLE_OUT => idle_out2,
- --BUS_TIMEOUT_IN : in std_logic;
- PROG_JTAG_FINISHED_OUT => prog_jtag_finished2
- );
-
-the_jtag_cmd_m26c : jtag_cmd_m26c
- port map(
- CLK_IN => CLK,
- RESET_IN => RESET,
-
- JTAG_TMS_OUT => jtag_tms,
- JTAG_TCK_OUT => jtag_tck,
- JTAG_TDI_OUT => jtag_tdi,
- JTAG_TDO_IN => jtag_tdo_evtlinv,
-
- BUS_DATA_IN => jtag_cmd_m26c_data_in,
- BUS_DATA_OUT => jtag_cmd_m26c_data_out,
- BUS_ADDR_IN => jtag_cmd_m26c_addr_in(8 downto 0),
- BUS_READ_IN => jtag_cmd_m26c_read_enable_in,
- BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in,
-
- BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out,
- BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out,
- BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out,
-
- OFF_SPILL_IN => off_spill,
- MY_STATUS_OUT => my_status,
- IDLE_OUT => idle_out,
- --BUS_TIMEOUT_IN : in std_logic;
- PROG_JTAG_FINISHED_OUT => prog_jtag_finished
- );
-
---JTAG_TDO_TEST_OUT <= JTAG_TDO_IN;
-
-SEQ_COUNTER : process(CLK, RESET)
-begin
- if(rising_edge(CLK)) then
- if(RESET='1') then
- jcounter <= (others => '0');
- off_spill <= '0';
- else
- jcounter <= jcounter_next;
- off_spill <= off_spill_next;
- end if;
- end if;
-end process;
-
-COMB_COUNTER : process(jcounter, off_spill, spillbreak_trigger, jcounter_initvalue)
-begin
- jcounter_next <= std_logic_vector(unsigned(jcounter) - 1);
- off_spill_next <= off_spill;
- if(spillbreak_trigger = '1') then
- off_spill_next <= '1';
- jcounter_next <= jcounter_initvalue;
- elsif(to_integer(unsigned(jcounter)) = 0) then
- off_spill_next <= '0';
- end if;
-end process;
-
-
-
--- the_IODELAY : IODELAY
--- generic map (
--- DELAY_SRC => "I", -- Specify which input port to be used
--- -- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
--- HIGH_PERFORMANCE_MODE => TRUE, -- TRUE specifies lower jitter
--- -- at expense of more power
--- IDELAY_TYPE => "DEFAULT", -- "DEFAULT", "FIXED" or "VARIABLE"
--- IDELAY_VALUE => 0, -- 0 to 63 tap values
--- ODELAY_VALUE => 0, -- 0 to 63 tap values
--- REFCLK_FREQUENCY => 200.0, -- Frequency used for IDELAYCTRL
--- -- 175.0 to 225.0
--- SIGNAL_PATTERN => "DATA") -- Input signal type, "CLOCK" or "DATA"
--- port map (
--- DATAOUT => DATAOUT, -- 1-bit delayed data output
--- C => C, -- 1-bit clock input
--- CE => CE, -- 1-bit clock enable input
--- DATAIN => DATAIN, -- 1-bit internal data input
--- IDATAIN => IDATAIN, -- 1-bit input data input (connect to port)
--- INC => INC, -- 1-bit increment/decrement input
--- ODATAIN => ODATAIN, -- 1-bit output data input
--- RST => RST, -- 1-bit active high, synch reset input
--- T => T -- 1-bit 3-state control input
--- );
-
-
-
---*************************************************************************************************************************
--- The LOGIC **************************************************************************************************************
---*************************************************************************************************************************
-
-
-
- -- LEDs
- DGOOD <= not ep_MED_STAT_OP_IN(9);
- DINT <= not (ep_MED_STAT_OP_IN(10) or ep_MED_STAT_OP_IN(11));
- DBAD <= not '0';
- DWAIT <= not '0';
---
-
-
-
-
--- MAPS CLK output
- Inst_dcm3: dcm3 PORT MAP(
- CLKIN_IN => CLK,
- RST_IN => '0',
- CLKFX_OUT => MAPS_CLK,
- CLK0_OUT => open,
- LOCKED_OUT => open
- );
-
---TEST_out <= jtag_tck;
---TEST_out <= prog_jtag_finished;
---TEST_out <= '0';
-JTAG1_TCK_OUT <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
-JTAG1_TMS_OUT <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
-JTAG1_TDI_OUT <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
-JTAG2_TCK_OUT <= (jtag_tck2 xor signals_invert2(6)) when signals_invert2(7) = '1' else signals_invert2(6);
-JTAG2_TMS_OUT <= (jtag_tms2 xor signals_invert2(4)) when signals_invert2(5) = '1' else signals_invert2(4);
-JTAG2_TDI_OUT <= (jtag_tdi2 xor signals_invert2(2)) when signals_invert2(3) = '1' else signals_invert2(2);
-JTAG3_TCK_OUT <= (jtag_tck3 xor signals_invert3(6)) when signals_invert3(7) = '1' else signals_invert3(6);
-JTAG3_TMS_OUT <= (jtag_tms3 xor signals_invert3(4)) when signals_invert3(5) = '1' else signals_invert3(4);
-JTAG3_TDI_OUT <= (jtag_tdi3 xor signals_invert3(2)) when signals_invert3(3) = '1' else signals_invert3(2);
--- x1_saddr(3) <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
--- x1_saddr(2) <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
--- x1_saddr(1) <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
--- x1_saddr(0) <= JTAG_TDO_IN;
-
-jtag_tdo_evtlinv <= (JTAG1_TDO_IN xor signals_invert(0)) when signals_invert(1) = '1' else signals_invert(0);
-jtag_tdo_evtlinv2 <= (JTAG2_TDO_IN xor signals_invert2(0)) when signals_invert2(1) = '1' else signals_invert2(0);
-jtag_tdo_evtlinv3 <= (JTAG3_TDO_IN xor signals_invert3(0)) when signals_invert3(1) = '1' else signals_invert3(0);
-
-MAPS_CLK1_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
-MAPS_CLK1_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
-MAPS_CLK2_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
-MAPS_CLK2_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
-MAPS_CLK3_out_int <= signals_invert(12) when signals_invert(13) = '1' else signals_invert(12);
-MAPS_CLK3_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
-
- ODDR_MAPS_CLK1_out : ODDR
- generic map(
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
- port map (
- Q => MAPS_CLK1_out, -- 1-bit DDR output
- C => MAPS_CLK, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => MAPS_CLK1_out_int, -- 1-bit data input (positive edge) -- inverted output
- D2 => MAPS_CLK1_out_int2, -- 1-bit data input (negative edge) -- inverted output
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
- ODDR_MAPS_CLK2_out : ODDR
- generic map(
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
- port map (
- Q => MAPS_CLK2_out, -- 1-bit DDR output
- C => MAPS_CLK, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => MAPS_CLK2_out_int, -- 1-bit data input (positive edge) -- inverted output
- D2 => MAPS_CLK2_out_int2, -- 1-bit data input (negative edge) -- inverted output
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
- ODDR_MAPS_CLK3_out : ODDR
- generic map(
- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
- INIT => '0', -- Initial value for Q port ('1' or '0')
- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
- port map (
- Q => MAPS_CLK3_out, -- 1-bit DDR output
- C => MAPS_CLK, -- 1-bit clock input
- CE => '1', -- 1-bit clock enable input
- D1 => MAPS_CLK3_out_int, -- 1-bit data input (positive edge) -- inverted output
- D2 => MAPS_CLK3_out_int2, -- 1-bit data input (negative edge) -- inverted output
- R => '0', -- 1-bit reset input
- S => '0' -- 1-bit set input
- );
-
-
--- MAPS_start_out
--- ODDR_MAPS_start_out : ODDR
--- generic map(
--- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
--- INIT => '0', -- Initial value for Q port ('1' or '0')
--- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
--- port map (
--- Q => MAPS_start_out, -- 1-bit DDR output
--- C => MAPS_CLK, -- 1-bit clock input
--- CE => '1', -- 1-bit clock enable input
--- D1 => not MAPS_start, -- 1-bit data input (positive edge) -- inverted output
--- D2 => not MAPS_start, -- 1-bit data input (negative edge) -- inverted output
--- R => '0', -- 1-bit reset input
--- S => '0' -- 1-bit set input
--- );
-MAPS_start1_out <= (MAPS_start xor signals_invert(8)) when signals_invert(9) = '1' else signals_invert(8); -- activated/deactivated and inverted/non-inverted
-MAPS_start2_out <= (MAPS_start xor signals_invert2(8)) when signals_invert2(9) = '1' else signals_invert2(8); -- activated/deactivated and inverted/non-inverted
-MAPS_start3_out <= (MAPS_start xor signals_invert3(8)) when signals_invert3(9) = '1' else signals_invert3(8); -- activated/deactivated and inverted/non-inverted
-
-
- -- MAPS_reset_out
--- ODDR_MAPS_reset_out : ODDR
--- generic map(
--- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
--- INIT => '0', -- Initial value for Q port ('1' or '0')
--- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
--- port map (
--- Q => MAPS_reset_out, -- 1-bit DDR output
--- C => MAPS_CLK, -- 1-bit clock input
--- CE => '1', -- 1-bit clock enable input
--- D1 => not MAPS_reset, -- 1-bit data input (positive edge) -- inverted output
--- D2 => not MAPS_reset, -- 1-bit data input (negative edge) -- inverted output
--- R => '0', -- 1-bit reset input
--- S => '0' -- 1-bit set input
--- );
---MAPS_reset_out <= not MAPS_reset;
-MAPS_reset1_out <= (MAPS_reset xor signals_invert(10)) when signals_invert(11) = '1' else signals_invert(10);
-MAPS_reset2_out <= (MAPS_reset xor signals_invert2(10)) when signals_invert2(11) = '1' else signals_invert2(10);
-MAPS_reset3_out <= (MAPS_reset xor signals_invert3(10)) when signals_invert3(11) = '1' else signals_invert3(10);
-
-COMB_MAPS_START : process(prog_jtag_finished_pulse_MAPS_CLK, MAPS_start, MAPS_start_count, beforestartcounter, beforestartcounter_finished, beforestartcounter_finished_last, waitbeforestart)
-begin
- MAPS_start_count_next <= std_logic_vector(unsigned(MAPS_start_count) - 1);
- if(beforestartcounter /= beforestartcounter_zero) then
- beforestartcounter_next <= std_logic_vector(unsigned(beforestartcounter) - 1);
- end if;
- MAPS_start_next <= MAPS_start;
- if(MAPS_start = '1') then
- if(to_integer(unsigned(MAPS_start_count)) = 0) then
- MAPS_start_next <= '0';
- end if;
- end if;
- if(prog_jtag_finished_pulse_MAPS_CLK = '1') then
- beforestartcounter_next <= waitbeforestart;
- end if;
- if(beforestartcounter_finished = '1' and beforestartcounter_finished_last='0') then
- MAPS_start_next <= '1';
- MAPS_start_count_next <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0)
- end if;
-end process;
-
-beforestartcounter_finished_next <= '1' when beforestartcounter = beforestartcounter_zero else '0';
-beforestartcounter_finished_last_next <= beforestartcounter_finished;
-
-SEQ_MAPS_START : process(MAPS_CLK, RESET)
-begin
- if(rising_edge(MAPS_CLK)) then
- if(RESET='1') then
- MAPS_start <= '0';
- MAPS_start_count <= (others => '0');
- beforestartcounter <= (others => '0');
- beforestartcounter_finished <= '1';
- beforestartcounter_finished_last <= '1';
- else
- MAPS_start <= MAPS_start_next;
- MAPS_start_count <= MAPS_start_count_next;
- beforestartcounter <= beforestartcounter_next;
- beforestartcounter_finished <= beforestartcounter_finished_next;
- beforestartcounter_finished_last <= beforestartcounter_finished_last_next;
- end if;
- end if;
-end process;
-
-
-
-COMB_MAPS_RESET : process(spillbreak_trigger_MAPS_CLK, MAPS_reset, MAPS_reset_count)
-begin
- MAPS_reset_count_next <= std_logic_vector(unsigned(MAPS_reset_count) - 1);
- MAPS_reset_next <= MAPS_reset;
- if(MAPS_reset = '1') then
- if(to_integer(unsigned(MAPS_reset_count)) = 0) then
- MAPS_reset_next <= '0';
- end if;
- end if;
- if(spillbreak_trigger_MAPS_CLK = '1') then
- MAPS_reset_next <= '1';
- MAPS_reset_count_next <= "1100100"; -- 3 clock cycles reset (on for 2,1,0)
- end if;
-end process;
-
--- reset signal
-SEQ_MAPS_RESET : process(MAPS_CLK, RESET)
-begin
- if(rising_edge(MAPS_CLK)) then
- if(RESET='1') then
- MAPS_reset <= '0';
- MAPS_reset_count <= (others => '0');
- else
- MAPS_reset <= MAPS_reset_next;
- MAPS_reset_count <= MAPS_reset_count_next;
- end if;
- end if;
-end process;
-
-
--- spill trigger (MAPS_CLK)
-spillbreak_trigger_MAPS_CLK <= '1' when (event_trigger_ff_MAPS_CLK = '1' and event_trigger_ff_last_MAPS_CLK = '0') else '0';
-event_trigger_ff_MAPS_CLK_next <= event_trigger when external_trigger = '1' else
- fake_event_trigger;
-event_trigger_ff_last_MAPS_CLK_next <= event_trigger_ff_MAPS_CLK;
-SEQ_SPILLTRIGGER_MAPS_CLK : process(MAPS_CLK, RESET)
-begin
- if(rising_edge(MAPS_CLK)) then
- if(RESET='1') then
- event_trigger_ff_last_MAPS_CLK <= '0';
- event_trigger_ff_MAPS_CLK <= '0';
- else
- event_trigger_ff_MAPS_CLK <= event_trigger_ff_MAPS_CLK_next;
- event_trigger_ff_last_MAPS_CLK <= event_trigger_ff_last_MAPS_CLK_next;
- end if;
- end if;
-end process;
-
-
--- spill trigger
-spillbreak_trigger <= '1' when (event_trigger_ff = '1' and event_trigger_ff_last = '0') else '0';
-event_trigger_ff_next <= event_trigger when external_trigger = '1' else
- fake_event_trigger;
-event_trigger_ff_last_next <= event_trigger_ff;
-SEQ_SPILLTRIGGER : process(CLK, RESET)
-begin
- if(rising_edge(CLK)) then
- if(RESET='1') then
- event_trigger_ff_last <= '0';
- event_trigger_ff <= '0';
- else
- event_trigger_ff <= event_trigger_ff_next;
- event_trigger_ff_last <= event_trigger_ff_last_next;
- end if;
- end if;
-end process;
-
-
--- spill trigger (MAPS_CLK)
-prog_jtag_finished_pulse_MAPS_CLK <= '1' when (prog_jtag_finished_ff_MAPS_CLK = '1' and prog_jtag_finished_ff_last_MAPS_CLK = '0') else '0';
-prog_jtag_finished_ff_MAPS_CLK_next <= prog_jtag_finished and prog_jtag_finished2 and prog_jtag_finished3;
-prog_jtag_finished_ff_last_MAPS_CLK_next <= prog_jtag_finished_ff_MAPS_CLK;
-SEQ_PROG_JTAG_FINISHED_MAPS_CLK : process(MAPS_CLK, RESET)
-begin
- if(rising_edge(MAPS_CLK)) then
- if(RESET='1') then
- prog_jtag_finished_ff_MAPS_CLK <= '0';
- prog_jtag_finished_ff_last_MAPS_CLK <= '0';
- else
- prog_jtag_finished_ff_MAPS_CLK <= prog_jtag_finished_ff_MAPS_CLK_next;
- prog_jtag_finished_ff_last_MAPS_CLK <= prog_jtag_finished_ff_last_MAPS_CLK_next;
- end if;
- end if;
-end process;
-
-fet_counter_next <= (others => '0') when trbnet_fet = '1' else std_logic_vector(unsigned(fet_counter) +1) and fet_counter_limit;
-fake_event_trigger_next <= '1' when (fet_counter = x"00000000" or fet_counter = x"00000001") else
- '0';
-
-fet_c_sync: process(CLK, RESET)
-begin
- if(rising_edge(CLK)) then
- if(RESET='1') then
- fet_counter <= (others => '0');
- fake_event_trigger <= '0';
- else
- fet_counter <= fet_counter_next;
- fake_event_trigger <= fake_event_trigger_next;
- end if;
- end if;
-end process;
-
-com_settings_all : process
-begin
- wait until (CLK'event and CLK='1');
- com_settings_write_ack_out <= '0';
- com_settings_dataready_out <= '0';
- trbnet_fet <= '0';
- if(com_settings_write_enable_in = '1') then
- if(com_settings_addr_in = x"01") then
- fet_counter_limit <= com_settings_data_in;
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"02") then
- jcounter_initvalue <= com_settings_data_in(28 downto 0);
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"03") then
- trbnet_fet <= '1';
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"06") then
- signals_invert <= com_settings_data_in(13 downto 0); -- 13-12: MAPS_CLK, 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"07") then
- waitbeforestart <= com_settings_data_in(31 downto 0);
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"08") then
- signals_invert2 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
- com_settings_write_ack_out <= '1';
- elsif(com_settings_addr_in = x"09") then
- signals_invert3 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
- com_settings_write_ack_out <= '1';
- end if;
- elsif(com_settings_read_enable_in = '1') then
- if(com_settings_addr_in = x"01") then
- com_settings_data_out <= fet_counter_limit;
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"02") then
- com_settings_data_out(28 downto 0) <= jcounter_initvalue;
- com_settings_data_out(31 downto 29) <= (others => '0');
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"04") then
- com_settings_data_out <= fet_counter;
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"05") then
- com_settings_data_out(28 downto 0) <= jcounter;
- com_settings_data_out(31 downto 29) <= (others => '0');
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"06") then
- com_settings_data_out(13 downto 0) <= signals_invert;
- com_settings_data_out(31 downto 14) <= (others => '0');
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"07") then
- com_settings_data_out <= waitbeforestart;
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"08") then
- com_settings_data_out(13 downto 0) <= signals_invert2;
- com_settings_data_out(31 downto 14) <= (others => '0');
- com_settings_dataready_out <= '1';
- elsif(com_settings_addr_in = x"09") then
- com_settings_data_out(13 downto 0) <= signals_invert3;
- com_settings_data_out(31 downto 14) <= (others => '0');
- com_settings_dataready_out <= '1';
- end if;
- end if;
- if(RESET = '1') then
- fet_counter_limit <= x"7FFFFFFF";
- jcounter_initvalue <= (others => '1');
- trbnet_fet <= '0';
- end if;
-end process;
-
-
-
-
-
-end architecture basic;
--- /dev/null
+-- The JCB and CCU in one
+
+
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.monitor_config.all;
+use work.version.all;
+use work.jtag_constants.all;
+
+entity main_board is
+ generic(
+ external_trigger : std_logic := '0'
+ );
+ port(
+
+ VIRT_CLK : in std_logic;
+ VIRT_CLKb : in std_logic;
+
+ RESET_VIRT : in std_logic;
+
+ ADO_LV_OUT : out std_logic_vector(61 downto 0);
+
+ ADO_JTTL_OUT : out std_logic_vector(15 downto 0); -- TTL Connector (20 pin)
+ ADO_TTL1_IN : in std_logic_vector(7 downto 0); -- JDIFF1
+ ADO_TTL2_IN : in std_logic_vector(7 downto 0); -- JDIFF2
+ ADO_TTL1_OUT : out std_logic_vector(3 downto 0); -- JTCM1
+ ADO_TTL2_OUT : out std_logic_vector(3 downto 0); -- JTCM2
+ ADO_TTL : in std_logic_vector(6 downto 0); -- internal
+
+ ONEWIRE : inout std_logic;
+
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector(15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector(15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DBAD : out std_logic;
+ DWAIT : out std_logic;
+
+ --unused
+ FS_PB : out std_logic_vector(17 downto 0);
+ FS_PC : inout std_logic_vector(17 downto 0);
+ ETRAX_IRQ : out std_logic
+
+ );
+end entity;
+
+
+
+
+
+
+
+
+
+ architecture basic of main_board is
+
+ signal SPILL_BREAK : std_logic;
+ signal static_spill_reg : std_logic;
+ signal pulsed_spill_reg : std_logic;
+
+ -- JTAG inputs/outputs
+ signal JTAG1_TMS_OUT : std_logic;
+ signal JTAG1_TCK_OUT : std_logic;
+ signal JTAG1_TDI_OUT : std_logic;
+ signal JTAG1_TDO_IN : std_logic;
+ signal JTAG2_TMS_OUT : std_logic;
+ signal JTAG2_TCK_OUT : std_logic;
+ signal JTAG2_TDI_OUT : std_logic;
+ signal JTAG2_TDO_IN : std_logic;
+
+ signal JTAG3_TMS_OUT : std_logic;
+ signal JTAG3_TCK_OUT : std_logic;
+ signal JTAG3_TDI_OUT : std_logic;
+ signal JTAG3_TDO_IN : std_logic;
+
+ -- MAPS outputs
+ signal MAPS_CLK1_out : std_logic;
+ signal MAPS_CLK2_out : std_logic;
+ signal MAPS_CLK3_out : std_logic;
+ signal MAPS_CLK1_out_int : std_logic; -- internal signal for ODDR
+ signal MAPS_CLK1_out_int2 : std_logic; -- internal signal for ODDR
+ signal MAPS_CLK2_out_int : std_logic; -- internal signal for ODDR
+ signal MAPS_CLK2_out_int2 : std_logic; -- internal signal for ODDR
+ signal MAPS_CLK3_out_int : std_logic; -- internal signal for ODDR
+ signal MAPS_CLK3_out_int2 : std_logic; -- internal signal for ODDR
+ signal MAPS_start1_out : std_logic;
+ signal MAPS_start2_out : std_logic;
+ signal MAPS_start3_out : std_logic;
+ signal MAPS_reset1_out : std_logic;
+ signal MAPS_reset2_out : std_logic;
+ signal MAPS_reset3_out : std_logic;
+
+
+
+
+ -- Main signals
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '1';
+ signal trg_config : std_logic_vector(31 downto 0) := (others => '0');
+ signal ipu_config : std_logic_vector(31 downto 0) := (others => '0');
+ signal main_config : std_logic_vector(31 downto 0) := (others => '0');
+ signal counter : std_logic_vector(31 downto 0) := x"0000_0000";
+-- signal soft_reset, next_soft_reset : std_logic := '0';
+
+
+
+
+ --attribute syn_keep : boolean;
+ --attribute syn_keep of next_testsignal : signal is true;
+
+ -- COM_SETTINGS signals: for settings in this entity
+ signal com_settings_addr_in : std_logic_vector(7 downto 0);
+ signal com_settings_data_in : std_logic_vector(31 downto 0);
+ signal com_settings_read_enable_in : std_logic;
+ signal com_settings_write_enable_in : std_logic;
+ signal com_settings_write_enable_in_last : std_logic;
+ signal com_settings_data_out : std_logic_vector(31 downto 0);
+ signal com_settings_dataready_out : std_logic;
+ signal com_settings_write_ack_out : std_logic;
+ signal com_settings_no_more_data_out : std_logic;
+ signal com_settings_unknown_addr_out : std_logic;
+ signal signals_invert : std_logic_vector(13 downto 0);
+ signal signals_invert2 : std_logic_vector(13 downto 0);
+ signal signals_invert3 : std_logic_vector(13 downto 0);
+ signal waitbeforestart : unsigned(27 downto 0);
+-- signal beforestartcounter, beforestartcounter_next : std_logic_vector(31 downto 0);
+-- constant beforestartcounter_zero : std_logic_vector(31 downto 0) := (others => '0');
+-- signal beforestartcounter_finished, beforestartcounter_finished_next : std_logic;
+-- signal beforestartcounter_finished_last, beforestartcounter_finished_last_next : std_logic;
+
+
+ --signal trigger_allchains_reset_pulse_MAPS_CLK : std_logic;
+ signal trigger_allchains_start_pulse_MAPS_CLK : std_logic;
+ signal trigger_start_pulse_MAPS_CLK : std_logic_vector(2 downto 0);
+ signal trigger_reset_pulse_MAPS_CLK : std_logic_vector(2 downto 0);
+ signal trigger2_reset_pulse_MAPS_CLK : std_logic_vector(2 downto 0);
+ signal trigger_jtag_run_MAPS_CLK : std_logic_vector(2 downto 0);
+ signal trigger_jtag_run2_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK : std_logic;
+signal trbnet_trigger_initialization_sequence_sync1_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_initialization_sequence_sync2_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_reset_pulse_sync1_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_reset_pulse_sync2_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_start_pulse_sync1_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_start_pulse_sync2_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK : std_logic_vector(2 downto 0);
+
+signal trbnet_trigger_allchains_initialization_sequence_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_reset_pulse_MAPS_CLK : std_logic;
+signal trbnet_trigger_allchains_start_pulse_MAPS_CLK : std_logic;
+signal trbnet_trigger_initialization_sequence_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_reset_pulse_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_start_pulse_MAPS_CLK : std_logic_vector(2 downto 0);
+signal trbnet_trigger_jtag_run_noreset_MAPS_CLK: std_logic_vector(2 downto 0);
+signal trbnet_trigger_allchains_initialization_sequence : std_logic;
+signal trbnet_trigger_allchains_reset_pulse : std_logic;
+signal trbnet_trigger_allchains_start_pulse : std_logic;
+signal trbnet_trigger_initialization_sequence : std_logic_vector(2 downto 0);
+signal trbnet_trigger_reset_pulse : std_logic_vector(2 downto 0);
+signal trbnet_trigger_start_pulse : std_logic_vector(2 downto 0);
+signal trbnet_trigger_jtag_run_noreset: std_logic_vector(2 downto 0);
+signal trbnet_trigger_jtag_write_once : std_logic_vector(2 downto 0);
+signal run_jtag : std_logic_vector(2 downto 0);
+signal run_jtag_MAPS_CLK : std_logic_vector(2 downto 0);
+
+
+
+type INIT_SEQ_TYPE is (isIDLE, isRUN_JTAG_WAIT1, isRUN_JTAG_WAIT2, isRUN_JTAG_WAIT3,
+isRUN_JTAG_WAIT4, isRUN_JTAG_WAIT5, isRUN_JTAG_WAIT6, isRUN_JTAG_WAIT7, isRUN_JTAG, isWAITBEFORESTART );
+--type ISA1 is array (0 to 2) of INIT_SEQ_TYPE;
+signal init_seq_MAPS_CLK_0 : INIT_SEQ_TYPE;
+signal init_seq_MAPS_CLK_1 : INIT_SEQ_TYPE;
+signal init_seq_MAPS_CLK_2 : INIT_SEQ_TYPE;
+signal init_seq_allchains_MAPS_CLK : INIT_SEQ_TYPE;
+
+
+signal resetbeforeinit : std_logic_vector(2 downto 0);
+signal resetafterfirstwrite : std_logic_vector(2 downto 0);
+signal request_reset : std_logic_vector(2 downto 0);
+signal request_reset_MAPS_CLK : std_logic_vector(2 downto 0);
+signal idle_out_MAPS_CLK : std_logic_vector(2 downto 0);
+type UA1 is array (0 to 2) of unsigned(27 downto 0);
+signal waitbeforestart_counter : UA1;
+constant waitbeforestart_counter_zero : unsigned := "0000000000000000000000000000";
+signal waitbeforestart_counter_allchains : unsigned(27 downto 0);
+
+--type UA3 is array (0 to 2) of unsigned(11 downto 0);
+--signal run_window_counter : UA3;
+
+--constant run_window_counter_zero : unsigned(11 downto 0) := "000000000000";
+signal prog_jtag_finished_MAPS_CLK : std_logic_vector(2 downto 0);
+type UA2 is array (0 to 2) of unsigned(6 downto 0);
+signal MAPS_reset_count : UA2;
+signal MAPS_start_count : UA2;
+
+signal MAPS_reset : std_logic_vector(2 downto 0);
+signal MAPS_start : std_logic_vector(2 downto 0);
+
+
+ -- JTAG_CMD_M26C connection signals
+ signal jtag_cmd_m26c_addr_in : std_logic_vector(8 downto 0);
+ signal jtag_cmd_m26c_data_in : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_read_enable_in : std_logic;
+ signal jtag_cmd_m26c_write_enable_in : std_logic;
+ signal jtag_cmd_m26c_data_out : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_dataready_out : std_logic;
+ signal jtag_cmd_m26c_write_ack_out : std_logic;
+ signal jtag_cmd_m26c_no_more_data_out : std_logic;
+ signal jtag_cmd_m26c_unknown_addr_out : std_logic;
+ signal jtag_tck : std_logic;
+ signal jtag_tms : std_logic;
+ signal jtag_tdi : std_logic;
+ signal jtag_tdo_evtlinv : std_logic;
+ -- second JTAG entity
+ signal jtag_cmd_m26c_addr_in2 : std_logic_vector(8 downto 0);
+ signal jtag_cmd_m26c_data_in2 : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_read_enable_in2 : std_logic;
+ signal jtag_cmd_m26c_write_enable_in2 : std_logic;
+ signal jtag_cmd_m26c_data_out2 : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_dataready_out2 : std_logic;
+ signal jtag_cmd_m26c_write_ack_out2 : std_logic;
+ signal jtag_cmd_m26c_no_more_data_out2 : std_logic;
+ signal jtag_cmd_m26c_unknown_addr_out2 : std_logic;
+ signal jtag_tck2 : std_logic;
+ signal jtag_tms2 : std_logic;
+ signal jtag_tdi2 : std_logic;
+ signal jtag_tdo_evtlinv2 : std_logic;
+ -- third JTAG entity
+ signal jtag_cmd_m26c_addr_in3 : std_logic_vector(8 downto 0);
+ signal jtag_cmd_m26c_data_in3 : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_read_enable_in3 : std_logic;
+ signal jtag_cmd_m26c_write_enable_in3 : std_logic;
+ signal jtag_cmd_m26c_data_out3 : std_logic_vector(31 downto 0);
+ signal jtag_cmd_m26c_dataready_out3 : std_logic;
+ signal jtag_cmd_m26c_write_ack_out3 : std_logic;
+ signal jtag_cmd_m26c_no_more_data_out3 : std_logic;
+ signal jtag_cmd_m26c_unknown_addr_out3 : std_logic;
+ signal jtag_tck3 : std_logic;
+ signal jtag_tms3 : std_logic;
+ signal jtag_tdi3 : std_logic;
+ signal jtag_tdo_evtlinv3 : std_logic;
+
+
+
+
+ -- JTAG stuff
+ signal my_status : std_logic_vector(8 downto 0);
+ signal idle_out : std_logic;
+ signal idle_out2 : std_logic;
+ signal idle_out3 : std_logic;
+
+ signal prog_jtag_finished : std_logic;
+
+ signal prog_jtag_finished2 : std_logic;
+
+ signal prog_jtag_finished3 : std_logic;
+
+ signal MAPS_CLK : std_logic;
+
+ -- TrbNet Reset Handler
+ signal reset_CLEAR_IN : std_logic := '0'; -- reset input (high active, async)
+ signal reset_CLEAR_N_IN : std_logic := '0'; -- reset input (low active, async)
+ signal reset_CLK_IN : std_logic := '0'; -- raw master clock, NOT from PLL/DLL!
+ signal reset_SYSCLK_IN : std_logic := '0'; -- PLL/DLL remastered clock
+ signal reset_PLL_LOCKED_IN : std_logic := '0'; -- master PLL lock signal (async)
+ signal reset_RESET_IN : std_logic := '0'; -- general reset signal (SYSCLK)
+ signal reset_TRB_RESET_IN : std_logic := '0'; -- TRBnet reset signal (SYSCLK)
+ signal reset_CLEAR_OUT : std_logic := '0'; -- async reset out, USE WITH CARE!
+ signal reset_RESET_OUT : std_logic := '0'; -- synchronous reset out (SYSCLK)
+ signal reset_DEBUG_OUT : std_logic_vector(15 downto 0) := x"0000";
+
+ -- the med TLK communicator signals
+ signal tlk_STAT : std_logic_vector(63 downto 0);
+ signal tlk_STAT_MONITOR : std_logic_vector(100 downto 0);
+ signal tmp: std_logic;
+ signal tlk_MED_DATA_IN : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal tlk_MED_PACKET_NUM_IN : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal tlk_MED_DATAREADY_IN : std_logic := '0';
+ signal tlk_MED_READ_OUT : std_logic := '0';
+ signal tlk_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal tlk_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal tlk_MED_DATAREADY_OUT : std_logic := '0';
+ signal tlk_MED_READ_IN : std_logic := '0';
+ signal tlk_STAT_OP : std_logic_vector(15 downto 0) := (others => '0');
+ signal tlk_CTRL_OP : std_logic_vector(15 downto 0) := (others => '0');
+ signal tlk_STAT_DEBUG : std_logic_vector(63 downto 0) := (others => '0');
+
+
+ -- BORIS:
+ -- HADES CTS (aka Arbiter)
+ signal a_MED_DATAREADY_OUT : std_logic := '0';
+ signal a_MED_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal a_MED_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal a_MED_READ_IN : std_logic := '0';
+ signal a_MED_DATAREADY_IN : std_logic := '0';
+ signal a_MED_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal a_MED_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal a_MED_READ_OUT : std_logic := '0';
+ signal a_MED_STAT_OP_IN : std_logic_vector(15 downto 0) := (others => '0');
+ signal a_MED_CTRL_OP_OUT : std_logic_vector(15 downto 0) := (others => '0');
+ signal a_TRG_SEND_IN : std_logic := '0';
+ signal a_TRG_TYPE_IN : std_logic_vector (3 downto 0) := (others => '0');
+ signal a_TRG_NUMBER_IN : std_logic_vector (15 downto 0) := (others => '0');
+ signal a_TRG_INFORMATION_IN : std_logic_vector (23 downto 0) := (others => '0');
+ signal a_TRG_RND_CODE_IN : std_logic_vector (7 downto 0) := (others => '0');
+ signal a_TRG_STATUS_BITS_OUT : std_logic_vector (31 downto 0) := (others => '0');
+ signal a_TRG_BUSY_OUT : std_logic := '0';
+ signal a_IPU_SEND_IN : std_logic := '0';
+ signal a_IPU_TYPE_IN : std_logic_vector (3 downto 0) := (others => '0');
+ signal a_IPU_NUMBER_IN : std_logic_vector (15 downto 0) := (others => '0');
+ signal a_IPU_INFORMATION_IN : std_logic_vector (7 downto 0) := (others => '0');
+ signal a_IPU_RND_CODE_IN : std_logic_vector (7 downto 0) := (others => '0');
+ signal a_IPU_DATA_OUT : std_logic_vector (31 downto 0) := (others => '0');
+ signal a_IPU_DATAREADY_OUT : std_logic := '0';
+ signal a_IPU_READ_IN : std_logic := '0';
+ signal a_IPU_STATUS_BITS_OUT : std_logic_vector (31 downto 0) := (others => '0');
+ signal a_IPU_BUSY_OUT : std_logic := '0';
+ signal a_REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal a_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0) := (others => '0');
+ signal a_REGIO_REGISTERS_IN : std_logic_vector(32*2**(5)-1 downto 0) := (others => '0');
+ signal a_REGIO_REGISTERS_OUT : std_logic_vector(32*2**(3)-1 downto 0) := (others => '0');
+ signal a_COMMON_STAT_REG_STROBE : std_logic_vector(std_COMSTATREG-1 downto 0) := (others => '0');
+ signal a_COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0) := (others => '0');
+ signal a_STAT_REG_STROBE : std_logic_vector(2**(5)-1 downto 0) := (others => '0');
+ signal a_CTRL_REG_STROBE : std_logic_vector(2**(3)-1 downto 0) := (others => '0');
+ signal a_REGIO_ADDR_OUT : std_logic_vector(16-1 downto 0) := (others => '0');
+ signal a_REGIO_READ_ENABLE_OUT : std_logic := '0';
+ signal a_REGIO_WRITE_ENABLE_OUT : std_logic := '0';
+ signal a_REGIO_DATA_OUT : std_logic_vector(32-1 downto 0) := (others => '0');
+ signal a_REGIO_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
+ signal a_REGIO_DATAREADY_IN : std_logic := '0';
+ signal a_REGIO_NO_MORE_DATA_IN : std_logic := '0';
+ signal a_REGIO_WRITE_ACK_IN : std_logic := '0';
+ signal a_REGIO_UNKNOWN_ADDR_IN : std_logic := '0';
+ signal a_REGIO_TIMEOUT_OUT : std_logic := '0';
+ signal a_REGIO_ONEWIRE_INOUT : std_logic := '0';
+ signal a_REGIO_ONEWIRE_MONITOR_OUT : std_logic := '0';
+ signal a_REGIO_ONEWIRE_MONITOR_IN : std_logic := '0';
+ signal a_REGIO_VAR_ENDPOINT_ID : std_logic_vector(15 downto 0) := (others => '0');
+ signal a_TRIGGER_MONITOR_IN : std_logic := '0'; --strobe when timing trigger received
+ signal a_GLOBAL_TIME_OUT : std_logic_vector(31 downto 0) := (others => '0'); --global time, microseconds
+ signal a_LOCAL_TIME_OUT : std_logic_vector(7 downto 0) := (others => '0'); --local time running with chip frequency
+ signal a_TIME_SINCE_LAST_TRG_OUT : std_logic_vector(31 downto 0) := (others => '0'); --local time, resetted with each trigger
+ signal a_TIMER_TICKS_OUT : std_logic_vector(1 downto 0) := (others => '0'); --bit 1 ms-tick, 0 us-tick
+ signal a_STAT_DEBUG_1 : std_logic_vector(31 downto 0) := (others => '0');
+ signal a_STAT_DEBUG_2 : std_logic_vector(31 downto 0) := (others => '0');
+
+ -- Monitor
+ signal m_ADDR_IN : std_logic_vector(9 downto 0) := (others => '0'); -- ADDR> bit 9,8 for selection, bits 7 - 0 for the cell address
+ signal m_READ_IN : std_logic := '0'; -- READ a cell
+ signal m_WRITE_IN : std_logic := '0'; -- WRITE CFG (FIFO control register)
+ signal m_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); -- CFG data
+ signal m_DATA_OUT : std_logic_vector(EXT_BUS-1 downto 0) := (others => '0'); -- Monitoring cell contents
+ signal m_VALID_OUT : std_logic := '0'; -- Valid signal
+ signal m_STATUS_OUT : std_logic_vector(7 downto 0) := "00000000"; -- Bits: 0-Unknown_Address, 1-EMPTY, 2-ACK, 5-Wrong_Address_Scope
+ signal m_FIFO_DATA_IN : std_logic_vector( (FIFO_BUS*FIFO_NUM)-1 downto 0 ) := (others => '0'); -- combined FIFO data
+ signal m_FIFO_WRITE_IN : std_logic_vector( FIFO_NUM-1 downto 0 ) := (others => '0'); -- combined FIFO valid
+ signal m_REG_DATA_IN : std_logic_vector( (REG_BUS*REG_NUM)-1 downto 0 ) := (others => '0'); -- combined RED data
+ signal m_TIMER0_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal m_TIMER1_IN : std_logic_vector( 7 downto 0) := (others => '0');
+ signal m_TIMER2_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal m_RB_TRIGGER_IN : std_logic := '0';
+ signal m_EXTERNAL_STAMP_IN : std_logic_vector(7 downto 0) := (others => '0'); -- additional data marker (in addition to timestamp)
+ signal m_DEBUG_OUT : std_logic_vector(31 downto 0) := (others => '0'); -- Status, tests, etc
+ signal dummy_BUS_ADDR_OUT : std_logic_vector(5 downto 0) := (others => '0'); --
+ signal dummy_BUS_DATA_OUT : std_logic_vector(23 downto 0) := (others => '0'); -- dummies for the regio bus handler
+ signal dummy_BUS_TIMEOUT_OUT : std_logic := '0'; --
+ signal monitor_writes : std_logic_vector(FIFO_NUM-1 downto 0) := (others => '0');
+
+ -- Sync Logic
+ signal sync_START_IN : std_logic; -- Start signal, can be 'high' all time, only 0-1 edge sets the start
+ signal sync_COUNTDOWN_IN : std_logic_vector(15 downto 0);
+ signal sync_RESTART_IN : std_logic; -- Must be high only in one clock cycle to set start
+ signal sync_SYNC_OUT : std_logic;
+ signal sync_SYNC_SENT_OUT : std_logic;
+ signal sync_START_SENT_OUT : std_logic;
+ signal sync_DEBUG_OUT : std_logic_vector(31 downto 0);
+
+ -- Frame Request
+ signal freq_START_IN : std_logic;
+ signal freq_AFL_IN : std_logic;
+ signal freq_SEND_OUT : std_logic;
+ signal freq_INFO_OUT : std_logic_vector(23 downto 0);
+ signal freq_RAND_OUT : std_logic_vector(7 downto 0);
+ signal freq_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal freq_NUM_OUT : std_logic_vector(15 downto 0);
+ signal freq_RAND_FIFO_WRITE_OUT : std_logic;
+ signal freq_RAND_FIFO_DATA_OUT : std_logic_vector(7 downto 0);
+ signal freq_DEBUG_OUT: std_logic_vector(15 downto 0);
+
+ -- Readout Request
+ signal readout_START_IN : std_logic;
+ signal readout_SEND_OUT : std_logic;
+ signal readout_INFO_OUT : std_logic_vector(7 downto 0);
+ signal readout_RAND_OUT : std_logic_vector(7 downto 0);
+ signal readout_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal readout_NUM_OUT : std_logic_vector(15 downto 0);
+ signal readout_RAND_FIFO_READ_OUT : std_logic;
+ signal readout_RAND_FIFO_DATA_IN : std_logic_vector(7 downto 0);
+ signal readout_RAND_FIFO_VALID_IN : std_logic;
+ signal readout_DEBUG_OUT: std_logic_vector(15 downto 0);
+
+ -- Arbiter Controller
+ signal actrl_SYNC_SENT_IN : std_logic;
+ signal actrl_START_SENT_IN : std_logic;
+ signal actrl_FR_START_OUT : std_logic;
+ signal actrl_AFL_OUT : std_logic;
+ signal actrl_R_START_OUT : std_logic;
+ signal actrl_DEBUG_OUT : std_logic_vector(15 downto 0);
+
+ -- Rand FIFO
+ signal rand_fifo_din : std_logic_VECTOR(15 downto 0);
+ signal rand_fifo_rd_en : std_logic;
+ signal rand_fifo_rst : std_logic;
+ signal rand_fifo_wr_en : std_logic;
+ signal rand_fifo_data_count: std_logic_VECTOR(9 downto 0);
+ signal rand_fifo_dout : std_logic_VECTOR(15 downto 0);
+ signal rand_fifo_empty : std_logic;
+ signal rand_fifo_full : std_logic;
+ signal rand_fifo_valid : std_logic;
+
+ signal stack0, max0, min0 : std_logic_vector(15 downto 0);
+ signal stack1, max1, min1 : std_logic_vector(15 downto 0);
+ signal stack2, max2, min2 : std_logic_vector(15 downto 0);
+ signal stack3, max3, min3 : std_logic_vector(15 downto 0);
+
+ --Statistics
+ signal trigger_per_sec : std_logic_vector(15 downto 0);
+ signal readout_per_sec : std_logic_vector(15 downto 0);
+ signal sync_per_sec : std_logic_vector(15 downto 0);
+ signal trigrelease_per_sec_2 : std_logic_vector(15 downto 0);
+ signal frcompl_per_sec_0: std_logic_vector(15 downto 0);
+ signal frcompl_per_sec_1: std_logic_vector(15 downto 0);
+ signal frcompl_per_sec_2: std_logic_vector(15 downto 0);
+ signal reset_per_sec_0: std_logic_vector(15 downto 0);
+ signal reset_per_sec_1: std_logic_vector(15 downto 0);
+ signal reset_per_sec_2: std_logic_vector(15 downto 0);
+ signal pulse_readout: std_logic;
+ signal pulse_trigger: std_logic;
+ signal pulse_sync: std_logic;
+ signal statistics_vector: std_logic_vector(511 downto 0);
+
+ signal jtag3cmd_READ_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag3cmd_WRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag3cmd_DATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag3cmd_SAMPLING_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag3cmd_RUN_COUNTER_OUT : std_logic_vector(31 downto 0);
+ signal jtag3cmd_STARTED_OUT : std_logic;
+ signal jtag3cmd_LAST_RUN_SUCCESSFUL_OUT : std_logic;
+ signal jtag3cmd_LAST_DATA_CHANGED_OUT : std_logic;
+ signal jtag3cmd_LAST_WRITE_ERRORS_OUT : std_logic;
+ signal jtag3cmd_LAST_READ_ERRORS_OUT : std_logic;
+ signal jtag3cmd_CRC_ERROR_OUT : std_logic;
+
+ signal jtag2cmd_READ_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag2cmd_WRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag2cmd_DATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag2cmd_SAMPLING_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag2cmd_RUN_COUNTER_OUT : std_logic_vector(31 downto 0);
+ signal jtag2cmd_STARTED_OUT : std_logic;
+ signal jtag2cmd_LAST_RUN_SUCCESSFUL_OUT : std_logic;
+ signal jtag2cmd_LAST_DATA_CHANGED_OUT : std_logic;
+ signal jtag2cmd_LAST_WRITE_ERRORS_OUT : std_logic;
+ signal jtag2cmd_LAST_READ_ERRORS_OUT : std_logic;
+ signal jtag2cmd_CRC_ERROR_OUT : std_logic;
+
+ signal jtag1cmd_READ_ID_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag1cmd_WRITE_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag1cmd_DATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag1cmd_SAMPLING_ERRORS_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ signal jtag1cmd_RUN_COUNTER_OUT : std_logic_vector(31 downto 0);
+ signal jtag1cmd_STARTED_OUT : std_logic;
+ signal jtag1cmd_LAST_RUN_SUCCESSFUL_OUT : std_logic;
+ signal jtag1cmd_LAST_DATA_CHANGED_OUT : std_logic;
+ signal jtag1cmd_LAST_WRITE_ERRORS_OUT : std_logic;
+ signal jtag1cmd_LAST_READ_ERRORS_OUT : std_logic;
+ signal jtag1cmd_CRC_ERROR_OUT : std_logic;
+
+ signal dcm4_CLK0_OUT : std_logic;
+
+ component arbiter_sync is
+ generic(
+ FRAMETIME : integer := 11520
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ START_IN : in std_logic; -- Start signal, can be 'high' all time, only 0-1 edge sets the start
+ RESTART_IN : in std_logic; -- Must be high only in one clock cycle to set start
+
+ SYNC_OUT : out std_logic;
+ SYNC_SENT_OUT : out std_logic;
+ START_SENT_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+ component jtag_cmd_m26c is
+ generic(
+ MAX_NUMCHIPS : integer := 7; -- maximum number of chips in this chain controllers chain (because number of chips can be 0, best chose 2^n-1 as maximum to save logic. if memory should be used completely, choose 2^n.)
+ MAX_NUMCHIPS_PLUS_ONE_LD : integer := 3; -- LD of value plus one, rounded up, or ld rounded down + 1, because the next binary digit needs one bit more (i.e, 2 needs second bit)
+ MAX_NUMCHIPS_LD : integer := 3; -- LD of value, rounded up
+ MAX_REGISTERS : integer := 14; -- number of registers per chip. Because of ram3 layout, values of 2^n-2 should be chosen.
+ MAX_REGISTERS_LD : integer := 4; -- LD of value, rounded up.
+ MAX_REGISTERS_PLUS_ONE_LD : integer := 4; -- LD of (value plus one)
+ MAX_REGISTERS_PLUS_TWO_LD : integer := 4; -- LD of (value plus two)
+ MAX_REGLEN_LD : integer := 12; -- LD of naximum register length.
+ MAX_REGLEN_PLUS_ONE_LD : integer := 12; -- LD of (register length+1)
+
+ WRITE_ERROR_THRESHOLD : integer := 3; -- if at least WRITE_ERROR_THRESHOLD bits are different from written value, count as WRITE_ERROR/DATA_CHANGED.
+
+ READ_ERROR_THRESHOLD : integer := 4; -- if at least READ_ERROR_THRESHOLD bits are different from 32 bit ID, set
+
+ JTAG_M26_IRLEN : integer := 5; -- length of the instruction register of the connected chips
+ JTAG_M26_IRLEN_LD : integer := 3; -- ld of value, rounded up
+ JTAG_M26_IR_ID_CODE : std_logic_vector(4 downto 0) := "01110"; -- Code selecting DEV_ID register of Mimosa26
+ JTAG_M26_DEV_ID : std_logic_vector(31 downto 0) := x"4D323601"; -- Mimosa26 DEV_ID, which the sensor should send.
+
+ RAM_JTAG_REGISTERS_DEPTH : integer := 11; -- will be split up into MAX_NUMCHIPS_LD bits for chip address, rest is for addressing words in that chip block. word size is 32 bit.
+-- GLOBAL_JTAG_COUNTER_BITS : integer := 10; --
+ JTAG_CHAIN_BROKEN_COUNTER_BITS : integer := 10; -- counter width
+ JTAG_TDO_EXPECTED_MAXDELAY : integer := 3; -- set range to 0..value for delay of expected TDO value
+ JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := 2; -- ceil of ld( value plus one)
+ RESET_WAIT_DURATION : unsigned := "10000000" -- 128 clock cycles at 100 mhz
+);
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ JTAG_TMS_OUT : out std_logic;
+ JTAG_TCK_OUT : out std_logic;
+ JTAG_TDI_OUT : out std_logic;
+ JTAG_TDO_IN : in std_logic;
+
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_ADDR_IN : in std_logic_vector(8 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+
+ BUS_DATAREADY_OUT : out std_logic;
+ BUS_NO_MORE_DATA_OUT : out std_logic;
+ BUS_WRITE_ACK_OUT : out std_logic;
+ BUS_UNKNOWN_ADDR_OUT : out std_logic;
+
+ --OFF_SPILL_IN : in std_logic;
+ RUN_REQUEST_IN : in std_logic;
+ WRITE_ONCE_REQUEST_IN : in std_logic;
+ MY_STATUS_OUT : out std_logic_vector(8 downto 0);
+ --MON_FIFO_DATA_OUT : out std_logic_vector((FIFO_BUS*FIFO_NUM)-1 downto 0);
+ --MON_FIFO_WRITE_OUT : out std_logic_vector(FIFO_NUM-1 downto 0);
+ REQUEST_RESET_OUT : out std_logic;
+ IDLE_OUT : out std_logic;
+ PROG_JTAG_FINISHED_OUT:out std_logic;
+ READ_ID_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ WRITE_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ DATA_CHANGED_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ SAMPLING_ERRORS_COUNT_OUT : out std_logic_vector(COUNTER_WIDTHS-1 downto 0);
+ RUN_COUNTER_OUT : out std_logic_vector(31 downto 0);
+
+ STARTED_OUT : out std_logic;
+ LAST_RUN_SUCCESSFUL_OUT : out std_logic;
+ LAST_DATA_CHANGED_OUT : out std_logic;
+ LAST_WRITE_ERRORS_OUT : out std_logic;
+ LAST_READ_ERRORS_OUT : out std_logic;
+ CRC_ERROR_OUT : out std_logic
+
+ --BUS_TIMEOUT_IN : in std_logic;
+ );
+ end component;
+
+ COMPONENT dcm3
+ PORT(
+ CLKIN_IN : IN std_logic;
+ RST_IN : IN std_logic;
+ CLKFX_OUT : OUT std_logic;
+ CLK0_OUT : OUT std_logic;
+ LOCKED_OUT : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ component virtex4_fifo_16x1024 IS
+ port (
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(15 downto 0);
+ rd_en: IN std_logic;
+ rst: IN std_logic;
+ wr_en: IN std_logic;
+ data_count: OUT std_logic_VECTOR(9 downto 0);
+ dout: OUT std_logic_VECTOR(15 downto 0);
+ empty: OUT std_logic;
+ full: OUT std_logic;
+ valid: OUT std_logic);
+ END component;
+
+ component trb_net16_endpoint_hades_cts is
+ generic(
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ IBUF_DEPTH : channel_config_t := (1,6,6,6);
+ FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6);
+ FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6);
+ INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+
+ --LVL1 trigger
+ TRG_SEND_IN : in std_logic;
+ TRG_TYPE_IN : in std_logic_vector (3 downto 0);
+ TRG_NUMBER_IN : in std_logic_vector (15 downto 0);
+ TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);
+ TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);
+ TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ TRG_BUSY_OUT : out std_logic;
+
+ --IPU Channel
+ IPU_SEND_IN : in std_logic;
+ IPU_TYPE_IN : in std_logic_vector (3 downto 0);
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);
+ -- Receiver port
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ IPU_READ_IN : in std_logic;
+ IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ IPU_BUSY_OUT : out std_logic;
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+ REGIO_ONEWIRE_INOUT : inout std_logic;
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
+ TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick
+ STAT_DEBUG_1 : out std_logic_vector(31 downto 0);
+ STAT_DEBUG_2 : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component arbiter_frame_request is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ START_IN : in std_logic;
+ AFL_IN : in std_logic;
+
+ SEND_OUT : out std_logic;
+ INFO_OUT : out std_logic_vector(23 downto 0);
+ RAND_OUT : out std_logic_vector(7 downto 0);
+ TYPE_OUT : out std_logic_vector(3 downto 0);
+ NUM_OUT : out std_logic_vector(15 downto 0);
+
+ RAND_FIFO_WRITE_OUT : out std_logic;
+ RAND_FIFO_DATA_OUT : out std_logic_vector(7 downto 0);
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component arbiter_readout_request is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ START_IN : in std_logic;
+
+ -- IPU/Readout ports
+ SEND_OUT : out std_logic;
+ INFO_OUT : out std_logic_vector(7 downto 0);
+ RAND_OUT : out std_logic_vector(7 downto 0);
+ TYPE_OUT : out std_logic_vector(3 downto 0);
+ NUM_OUT : out std_logic_vector(15 downto 0);
+
+ -- Random FIFO ports
+ RAND_FIFO_READ_OUT : out std_logic;
+ RAND_FIFO_DATA_IN : in std_logic_vector(7 downto 0);
+ RAND_FIFO_VALID_IN : in std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+
+ );
+ end component;
+
+
+ component arbiter_controller is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- SYNC ports
+ SYNC_SENT_IN : in std_logic;
+ START_SENT_IN : in std_logic;
+
+ -- Frame Request Ports
+ FR_START_OUT : out std_logic;
+ AFL_OUT : out std_logic;
+ TRG_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ TRG_BUSY_IN : in std_logic;
+ FRAMERATE_IN : in std_logic_vector(15 downto 0);
+
+ -- Readout Request Ports
+ R_START_OUT : out std_logic;
+ IPU_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ IPU_BUSY_IN : in std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component statistics_per_sec_advanced is
+ generic(
+ NUMBER_OF_SECONDS : integer range 1 to 32;
+ SIGNAL_NUMBER : integer range 1 to 32
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- INPUTs
+ SIGNAL_IN : in std_logic_vector(31 downto 0);
+
+ -- Outputs
+ STATISTICS_OUT : out std_logic_vector(32*16-1 downto 0);
+ DATAREADY_OUT : out std_logic
+
+ );
+ end component;
+
+
+
+component dcm4 is
+PORT (
+ CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLKIN_IBUFG_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic
+ );
+ end component;
+
+
+
+
+begin
+
+
+
+
+ --inputs/outputs
+ MAPS_reset_OBUFDS1 : OBUFDS
+ port map (
+ I => MAPS_reset1_out,
+ O => ADO_LV_OUT(2),
+ OB=> ADO_LV_OUT(3)
+ );
+ MAPS_start_OBUFDS1 : OBUFDS
+ port map (
+ I => MAPS_start1_out,
+ O => ADO_LV_OUT(4),
+ OB=> ADO_LV_OUT(5)
+ );
+ MAPS_CLK_OBUFDS1 : OBUFDS
+ port map (
+ I => MAPS_CLK1_out,
+ O => ADO_LV_OUT(6),
+ OB=> ADO_LV_OUT(7)
+ );
+
+ jtag1_tck_OBUFDS : OBUFDS
+ port map (
+ I => JTAG1_TCK_OUT,
+ O => ADO_LV_OUT(8),
+ OB=> ADO_LV_OUT(9)
+ );
+ jtag1_tdi_OBUFDS : OBUFDS
+ port map (
+ I => JTAG1_TDI_OUT,
+ O => ADO_LV_OUT(10),
+ OB=> ADO_LV_OUT(11)
+ );
+ jtag1_tms_OBUFDS : OBUFDS
+ port map (
+ I => JTAG1_TMS_OUT,
+ O => ADO_LV_OUT(12),
+ OB=> ADO_LV_OUT(13)
+ );
+
+
+ MAPS_reset_OBUFDS2 : OBUFDS
+ port map (
+ I => MAPS_reset2_out,
+ O => ADO_LV_OUT(18),
+ OB=> ADO_LV_OUT(19)
+ );
+ MAPS_start_OBUFDS2 : OBUFDS
+ port map (
+ I => MAPS_start2_out,
+ O => ADO_LV_OUT(20),
+ OB=> ADO_LV_OUT(21)
+ );
+ MAPS_CLK_OBUFDS2 : OBUFDS
+ port map (
+ I => MAPS_CLK2_out,
+ O => ADO_LV_OUT(22),
+ OB=> ADO_LV_OUT(23)
+ );
+
+ jtag2_tck_OBUFDS : OBUFDS
+ port map (
+ I => JTAG2_TCK_OUT,
+ O => ADO_LV_OUT(24),
+ OB=> ADO_LV_OUT(25)
+ );
+ jtag2_tdi_OBUFDS : OBUFDS
+ port map (
+ I => JTAG2_TDI_OUT,
+ O => ADO_LV_OUT(26),
+ OB=> ADO_LV_OUT(27)
+ );
+ jtag2_tms_OBUFDS : OBUFDS
+ port map (
+ I => JTAG2_TMS_OUT,
+ O => ADO_LV_OUT(28),
+ OB=> ADO_LV_OUT(29)
+ );
+
+ MAPS_reset_OBUFDS3 : OBUFDS
+ port map (
+ I => MAPS_reset3_out,
+ O => ADO_LV_OUT(34),
+ OB=> ADO_LV_OUT(35)
+ );
+ MAPS_start_OBUFDS3 : OBUFDS
+ port map (
+ I => MAPS_start3_out,
+ O => ADO_LV_OUT(36),
+ OB=> ADO_LV_OUT(37)
+ );
+ MAPS_CLK_OBUFDS3 : OBUFDS
+ port map (
+ I => MAPS_CLK3_out,
+ O => ADO_LV_OUT(38),
+ OB=> ADO_LV_OUT(39)
+ );
+
+ jtag3_tck_OBUFDS : OBUFDS
+ port map (
+ I => JTAG3_TCK_OUT,
+ O => ADO_LV_OUT(40),
+ OB=> ADO_LV_OUT(41)
+ );
+ jtag3_tdi_OBUFDS : OBUFDS
+ port map (
+ I => JTAG3_TDI_OUT,
+ O => ADO_LV_OUT(42),
+ OB=> ADO_LV_OUT(43)
+ );
+ jtag3_tms_OBUFDS : OBUFDS
+ port map (
+ I => JTAG3_TMS_OUT,
+ O => ADO_LV_OUT(44),
+ OB=> ADO_LV_OUT(45)
+ );
+
+ --ADO_LV_OUT(1 downto 0) <= (others => '0');
+ --ADO_LV_OUT(17 downto 14) <= (others => '0');
+ --ADO_LV_OUT(33 downto 30) <= (others => '0');
+ --ADO_LV_OUT(57 downto 46) <= (others => '0');
+
+ unused1 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(0),
+ OB=> ADO_LV_OUT(1)
+ );
+
+ unused2 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(14),
+ OB=> ADO_LV_OUT(15)
+ );
+ unused3 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(16),
+ OB=> ADO_LV_OUT(17)
+ );
+ unused4 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(30),
+ OB=> ADO_LV_OUT(31)
+ );
+ unused5 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(32),
+ OB=> ADO_LV_OUT(33)
+ );
+ unused6 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(46),
+ OB=> ADO_LV_OUT(47)
+ );
+ unused7 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(48),
+ OB=> ADO_LV_OUT(49)
+ );
+ unused8 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(50),
+ OB=> ADO_LV_OUT(51)
+ );
+ unused9 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(52),
+ OB=> ADO_LV_OUT(53)
+ );
+ unused10 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(54),
+ OB=> ADO_LV_OUT(55)
+ );
+ unused11 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(56),
+ OB=> ADO_LV_OUT(57)
+ );
+ unused12 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(58),
+ OB=> ADO_LV_OUT(59)
+ );
+ unused13 : OBUFDS
+ port map (
+ I => '0',
+ O => ADO_LV_OUT(60),
+ OB=> ADO_LV_OUT(61)
+ );
+
+
+ JTAG1_TDO_IN <= ADO_TTL1_IN(0);
+ JTAG2_TDO_IN <= ADO_TTL1_IN(1);
+ JTAG3_TDO_IN <= ADO_TTL1_IN(2);
+
+
+
+
+ ---------------------------------------------------------------------
+ -- CLK generator
+ ---------------------------------------------------------------------
+ the_IBUFGDS : IBUFGDS
+ generic map (
+ DIFF_TERM => TRUE,
+ IOSTANDARD => "LVDS_25"
+ )
+ port map (
+ O => CLK,
+ I => VIRT_CLK,
+ IB => VIRT_CLKb
+ );
+
+
+ ----------------------------------------------------------------------------------------------------------------------------------------
+ -- Reset Handler
+ ----------------------------------------------------------------------------------------------------------------------------------------
+ the_trb_net_reset_handler: trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"000f"
+ )
+ port map(
+ CLEAR_IN => reset_CLEAR_IN, -- reset input (high active, async)
+ CLEAR_N_IN => reset_CLEAR_N_IN, -- reset input (low active, async)
+ CLK_IN => reset_CLK_IN, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => reset_SYSCLK_IN, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => reset_PLL_LOCKED_IN,-- master PLL lock signal (async)
+ RESET_IN => reset_RESET_IN, -- general reset signal (SYSCLK)
+ TRB_RESET_IN => reset_TRB_RESET_IN, -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => reset_CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => RESET, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => reset_DEBUG_OUT
+ );
+ reset_CLK_IN <= CLK;
+ reset_SYSCLK_IN <= CLK;
+ reset_CLEAR_IN <= '0';
+ reset_CLEAR_N_IN <= '1';
+ reset_PLL_LOCKED_IN <= '1';
+ reset_RESET_IN <= a_MED_STAT_OP_IN(13);
+
+
+ ---------------------------------------------------------------------
+ -- The TRBNET TLK interface
+ ---------------------------------------------------------------------
+ the_trb_net16_med_tlk : trb_net16_med_tlk
+ port map(
+ RESET => RESET,
+ CLK => CLK,
+ TLK_CLK => TLK_CLK,
+ TLK_ENABLE => TLK_ENABLE,
+ TLK_LCKREFN => TLK_LCKREFN,
+ TLK_LOOPEN => TLK_LOOPEN,
+ TLK_PRBSEN => TLK_PRBSEN,
+ TLK_RXD => TLK_RXD,
+ TLK_RX_CLK => dcm4_CLK0_OUT,
+ TLK_RX_DV => TLK_RX_DV,
+ TLK_RX_ER => TLK_RX_ER,
+ TLK_TXD => TLK_TXD,
+ TLK_TX_EN => TLK_TX_EN,
+ TLK_TX_ER => TLK_TX_ER,
+ SFP_LOS => SFP_LOS,
+ SFP_TX_DIS => SFP_TX_DIS,
+ MED_DATAREADY_IN => tlk_MED_DATAREADY_IN,
+ MED_READ_IN => tlk_MED_READ_IN,
+ MED_DATA_IN => tlk_MED_DATA_IN,
+ MED_PACKET_NUM_IN => tlk_MED_PACKET_NUM_IN,
+ MED_DATAREADY_OUT => tlk_MED_DATAREADY_OUT,
+ MED_READ_OUT => tlk_MED_READ_OUT,
+ MED_DATA_OUT => tlk_MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => tlk_MED_PACKET_NUM_OUT,
+ STAT => tlk_STAT,
+ STAT_MONITOR => tlk_STAT_MONITOR,
+ STAT_OP => tlk_STAT_OP,
+ CTRL_OP => tlk_CTRL_OP
+ );
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Arbiter CTS
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_trb_net16_endpoint_hades_cts : trb_net16_endpoint_hades_cts
+ generic map(
+ USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+ IBUF_DEPTH => (6,6,6,6),
+ FIFO_TO_INT_DEPTH => (6,6,6,6),
+ FIFO_TO_APL_DEPTH => (6,6,6,6),
+ INIT_CAN_SEND_DATA => (c_YES,c_YES,c_NO,c_NO),
+ REPLY_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_YES),
+ REPLY_CAN_RECEIVE_DATA => (c_YES,c_YES,c_NO,c_NO),
+ USE_CHECKSUM => (c_NO,c_YES,c_YES,c_YES),
+ APL_WRITE_ALL_WORDS => (c_NO,c_NO,c_NO,c_NO),
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_NUM_STAT_REGS => 5, --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS => 3, --log2 of number of ctrl registers
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS => (others => '0'),
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS => x"00FF",
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK => (others => '1'),
+ REGIO_USE_DAT_PORT => c_YES, --internal data port
+ REGIO_INIT_ADDRESS => x"f013",
+ REGIO_INIT_UNIQUE_ID => x"0000_0000_0000_0000",
+ REGIO_INIT_BOARD_INFO => x"0000_0000",
+ REGIO_INIT_ENDPOINT_ID => x"1234",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+ REGIO_COMPILE_VERSION => x"0001",
+ REGIO_HARDWARE_VERSION => x"50000000",
+ REGIO_USE_1WIRE_INTERFACE=> c_YES, --c_YES,c_NO,c_MONITOR
+ REGIO_USE_VAR_ENDPOINT_ID=> c_NO,
+ CLOCK_FREQUENCY => 100
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MED_DATAREADY_OUT => a_MED_DATAREADY_OUT,
+ MED_DATA_OUT => a_MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => a_MED_PACKET_NUM_OUT,
+ MED_READ_IN => a_MED_READ_IN,
+
+ MED_DATAREADY_IN => a_MED_DATAREADY_IN,
+ MED_DATA_IN => a_MED_DATA_IN,
+ MED_PACKET_NUM_IN => a_MED_PACKET_NUM_IN,
+ MED_READ_OUT => a_MED_READ_OUT,
+
+ MED_STAT_OP_IN => a_MED_STAT_OP_IN,
+ MED_CTRL_OP_OUT => a_MED_CTRL_OP_OUT,
+
+ --LVL1 trigger
+ TRG_SEND_IN => a_TRG_SEND_IN,
+ TRG_TYPE_IN => a_TRG_TYPE_IN,
+ TRG_NUMBER_IN => a_TRG_NUMBER_IN,
+ TRG_INFORMATION_IN => a_TRG_INFORMATION_IN,
+ TRG_RND_CODE_IN => a_TRG_RND_CODE_IN,
+ TRG_STATUS_BITS_OUT => a_TRG_STATUS_BITS_OUT,
+ TRG_BUSY_OUT => a_TRG_BUSY_OUT,
+
+ --IPU Channel
+ IPU_SEND_IN => a_IPU_SEND_IN,
+ IPU_TYPE_IN => a_IPU_TYPE_IN,
+ IPU_NUMBER_IN => a_IPU_NUMBER_IN,
+ IPU_INFORMATION_IN => a_IPU_INFORMATION_IN,
+ IPU_RND_CODE_IN => a_IPU_RND_CODE_IN,
+ -- Receiver port
+ IPU_DATA_OUT => a_IPU_DATA_OUT,
+ IPU_DATAREADY_OUT => a_IPU_DATAREADY_OUT,
+ IPU_READ_IN => a_IPU_READ_IN,
+ IPU_STATUS_BITS_OUT => a_IPU_STATUS_BITS_OUT,
+ IPU_BUSY_OUT => a_IPU_BUSY_OUT,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => a_REGIO_COMMON_STAT_REG_IN,
+ REGIO_COMMON_CTRL_REG_OUT => a_REGIO_COMMON_CTRL_REG_OUT,
+ REGIO_REGISTERS_IN => a_REGIO_REGISTERS_IN,
+ REGIO_REGISTERS_OUT => a_REGIO_REGISTERS_OUT,
+ COMMON_STAT_REG_STROBE => a_COMMON_STAT_REG_STROBE,
+ COMMON_CTRL_REG_STROBE => a_COMMON_CTRL_REG_STROBE,
+ STAT_REG_STROBE => a_STAT_REG_STROBE,
+ CTRL_REG_STROBE => a_CTRL_REG_STROBE,
+
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => a_REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => a_REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => a_REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => a_REGIO_DATA_OUT,
+ REGIO_DATA_IN => a_REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => a_REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => a_REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => a_REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => a_REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => a_REGIO_TIMEOUT_OUT,
+
+ REGIO_ONEWIRE_INOUT => ONEWIRE,
+ REGIO_ONEWIRE_MONITOR_OUT => a_REGIO_ONEWIRE_MONITOR_OUT,
+ REGIO_ONEWIRE_MONITOR_IN => a_REGIO_ONEWIRE_MONITOR_IN,
+ REGIO_VAR_ENDPOINT_ID => a_REGIO_VAR_ENDPOINT_ID,
+ TRIGGER_MONITOR_IN => a_TRIGGER_MONITOR_IN,
+ GLOBAL_TIME_OUT => a_GLOBAL_TIME_OUT,
+ LOCAL_TIME_OUT => a_LOCAL_TIME_OUT,
+ TIME_SINCE_LAST_TRG_OUT => a_TIME_SINCE_LAST_TRG_OUT,
+ TIMER_TICKS_OUT => a_TIMER_TICKS_OUT,
+ STAT_DEBUG_1 => a_STAT_DEBUG_1,
+ STAT_DEBUG_2 => a_STAT_DEBUG_2
+ );
+ a_MED_READ_IN <= tlk_MED_READ_OUT;
+ a_MED_DATAREADY_IN <= tlk_MED_DATAREADY_OUT;
+ a_MED_DATA_IN <= tlk_MED_DATA_OUT;
+ a_MED_PACKET_NUM_IN <= tlk_MED_PACKET_NUM_OUT;
+ a_MED_STAT_OP_IN <= tlk_STAT_OP;
+ tlk_MED_DATAREADY_IN <= a_MED_DATAREADY_OUT;
+ tlk_MED_DATA_IN <= a_MED_DATA_OUT;
+ tlk_MED_PACKET_NUM_IN <= a_MED_PACKET_NUM_OUT;
+ tlk_MED_READ_IN <= a_MED_READ_OUT;
+ tlk_CTRL_OP <= a_MED_CTRL_OP_OUT;
+ a_TRG_SEND_IN <= freq_SEND_OUT;
+ a_TRG_TYPE_IN <= freq_TYPE_OUT;
+ a_TRG_NUMBER_IN <= freq_NUM_OUT;
+ a_TRG_INFORMATION_IN <= freq_INFO_OUT;
+ a_TRG_RND_CODE_IN <= freq_RAND_OUT;
+ a_IPU_SEND_IN <= readout_SEND_OUT;
+ a_IPU_TYPE_IN <= readout_TYPE_OUT;
+ a_IPU_NUMBER_IN <= readout_NUM_OUT;
+ a_IPU_INFORMATION_IN <= readout_INFO_OUT;
+ a_IPU_RND_CODE_IN <= readout_RAND_OUT;
+ a_IPU_READ_IN <= '1';
+
+ main_config <= a_REGIO_REGISTERS_OUT(31 downto 0);
+ trg_config <= a_REGIO_REGISTERS_OUT(63 downto 32);
+ ipu_config <= a_REGIO_REGISTERS_OUT(95 downto 64);
+
+ a_REGIO_REGISTERS_IN(31 downto 0) <= counter;
+ a_REGIO_REGISTERS_IN(63 downto 32) <= x"0000_000" & "000" & main_config(0);
+ a_REGIO_REGISTERS_IN(95 downto 64) <= jtag3cmd_WRITE_ERRORS_COUNT_OUT & jtag3cmd_READ_ID_ERRORS_COUNT_OUT;
+ a_REGIO_REGISTERS_IN(127 downto 96) <= jtag3cmd_SAMPLING_ERRORS_COUNT_OUT & jtag3cmd_DATA_CHANGED_COUNT_OUT;
+ a_REGIO_REGISTERS_IN(159 downto 128) <= jtag3cmd_RUN_COUNTER_OUT;
+ a_REGIO_REGISTERS_IN(191 downto 160) <= "000" & '0' & "000" & '0' & "000" & jtag3cmd_CRC_ERROR_OUT & "000" & jtag3cmd_LAST_READ_ERRORS_OUT & "000" & jtag3cmd_LAST_WRITE_ERRORS_OUT & "000" & jtag3cmd_LAST_DATA_CHANGED_OUT & "000" & jtag3cmd_LAST_RUN_SUCCESSFUL_OUT & "000" & jtag3cmd_STARTED_OUT;
+ a_REGIO_REGISTERS_IN(223 downto 192) <= jtag2cmd_WRITE_ERRORS_COUNT_OUT & jtag2cmd_READ_ID_ERRORS_COUNT_OUT;
+ a_REGIO_REGISTERS_IN(255 downto 224) <= jtag2cmd_SAMPLING_ERRORS_COUNT_OUT & jtag2cmd_DATA_CHANGED_COUNT_OUT;
+
+ a_REGIO_REGISTERS_IN(256+31 downto 256) <= jtag2cmd_RUN_COUNTER_OUT;
+ a_REGIO_REGISTERS_IN(256+63 downto 256+32) <= "000" & '0' & "000" & '0' & "000" & jtag2cmd_CRC_ERROR_OUT & "000" & jtag2cmd_LAST_READ_ERRORS_OUT & "000" & jtag2cmd_LAST_WRITE_ERRORS_OUT & "000" & jtag2cmd_LAST_DATA_CHANGED_OUT & "000" & jtag2cmd_LAST_RUN_SUCCESSFUL_OUT & "000" & jtag2cmd_STARTED_OUT;
+ a_REGIO_REGISTERS_IN(256+95 downto 256+64) <= jtag1cmd_WRITE_ERRORS_COUNT_OUT & jtag1cmd_READ_ID_ERRORS_COUNT_OUT;
+ a_REGIO_REGISTERS_IN(256+127 downto 256+96) <= jtag1cmd_SAMPLING_ERRORS_COUNT_OUT & jtag1cmd_DATA_CHANGED_COUNT_OUT;
+ a_REGIO_REGISTERS_IN(256+159 downto 256+128) <= jtag1cmd_RUN_COUNTER_OUT;
+ a_REGIO_REGISTERS_IN(256+191 downto 256+160) <= "000" & '0' & "000" & '0' & "000" & jtag1cmd_CRC_ERROR_OUT & "000" & jtag1cmd_LAST_READ_ERRORS_OUT & "000" & jtag1cmd_LAST_WRITE_ERRORS_OUT & "000" & jtag1cmd_LAST_DATA_CHANGED_OUT & "000" & jtag1cmd_LAST_RUN_SUCCESSFUL_OUT & "000" & jtag1cmd_STARTED_OUT;
+ a_REGIO_REGISTERS_IN(256+223 downto 256+192) <= x"0000_000" & "000" & static_spill_reg;
+ a_REGIO_REGISTERS_IN(256+255 downto 256+224) <= x"0000_000" & "000" & pulsed_spill_reg;
+
+ a_REGIO_REGISTERS_IN(512+31 downto 512) <= x"0000" & statistics_vector(16*1-1 downto 16*0);
+ a_REGIO_REGISTERS_IN(512+63 downto 512+32) <= x"0000" & statistics_vector(16*2-1 downto 16*1);
+ a_REGIO_REGISTERS_IN(512+95 downto 512+64) <= x"0000" & statistics_vector(16*3-1 downto 16*2);
+ a_REGIO_REGISTERS_IN(512+127 downto 512+96) <= x"0000" & statistics_vector(16*4-1 downto 16*3);
+ a_REGIO_REGISTERS_IN(512+159 downto 512+128) <= x"0000" & statistics_vector(16*5-1 downto 16*4);
+ a_REGIO_REGISTERS_IN(512+191 downto 512+160) <= x"0000" & statistics_vector(16*6-1 downto 16*5);
+ a_REGIO_REGISTERS_IN(512+223 downto 512+192) <= x"0000" & statistics_vector(16*7-1 downto 16*6);
+ a_REGIO_REGISTERS_IN(512+255 downto 512+224) <= x"0000" & statistics_vector(16*8-1 downto 16*7);
+
+ a_REGIO_REGISTERS_IN(512+256+31 downto 512+256) <= x"0000" & statistics_vector(16*9-1 downto 16*8);
+ a_REGIO_REGISTERS_IN(512+256+63 downto 512+256+32) <= x"0000" & x"0000";
+ a_REGIO_REGISTERS_IN(512+256+95 downto 512+256+64) <= x"0000" & x"0000";
+ a_REGIO_REGISTERS_IN(512+256+127 downto 512+256+96) <= x"0000" & x"0000";
+ a_REGIO_REGISTERS_IN(512+256+159 downto 512+256+128) <= x"0000" & x"0000";
+ a_REGIO_REGISTERS_IN(512+256+191 downto 512+256+160) <= x"0000" & x"0000";
+ a_REGIO_REGISTERS_IN(512+256+223 downto 512+256+192) <= x"0000_0000";
+ a_REGIO_REGISTERS_IN(512+256+255 downto 512+256+224) <= x"0000_0000";
+
+
+ the_statistics_per_sec:statistics_per_sec_advanced
+ generic map(
+ NUMBER_OF_SECONDS => 1,
+ SIGNAL_NUMBER => 9
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ -- INPUTs
+ SIGNAL_IN(0) => not MAPS_reset1_out,
+ SIGNAL_IN(1) => MAPS_start1_out,
+ SIGNAL_IN(2) => not MAPS_reset2_out,
+ SIGNAL_IN(3) => MAPS_start2_out,
+ SIGNAL_IN(4) => not MAPS_reset3_out,
+ SIGNAL_IN(5) => MAPS_start3_out,
+ SIGNAL_IN(6) => freq_SEND_OUT,
+ SIGNAL_IN(7) => readout_SEND_OUT,
+ SIGNAL_IN(8) => actrl_AFL_OUT,
+ SIGNAL_IN(31 downto 9) => "00000000000000000000000",
+
+ -- Outputs
+ STATISTICS_OUT => statistics_vector,
+
+ DATAREADY_OUT => open
+ );
+
+
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Rand FIFO
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_rand_fifo_virtex4_fifo_16x1024: virtex4_fifo_16x1024
+ port map(
+ clk => CLK,
+ din(15 downto 8) => x"00",
+ din(7 downto 0) => freq_RAND_FIFO_DATA_OUT,
+ rd_en => readout_RAND_FIFO_READ_OUT,
+ rst => RESET,
+ wr_en => freq_RAND_FIFO_WRITE_OUT,
+ data_count => rand_fifo_data_count,
+ dout => rand_fifo_dout,
+ empty => rand_fifo_empty,
+ full => rand_fifo_full,
+ valid => rand_fifo_valid
+ );
+
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The SYNC Module
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_arbiter_sync: arbiter_sync
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ START_IN => main_config(0),
+ RESTART_IN => sync_RESTART_IN,
+
+ SYNC_OUT => sync_SYNC_OUT,
+ SYNC_SENT_OUT => sync_SYNC_SENT_OUT,
+ START_SENT_OUT => sync_START_SENT_OUT,
+
+ DEBUG_OUT => sync_DEBUG_OUT
+ );
+
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Frame Request Module
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_arbiter_frame_request: arbiter_frame_request
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ START_IN => freq_START_IN,
+ AFL_IN => freq_AFL_IN,
+
+ SEND_OUT => freq_SEND_OUT,
+ INFO_OUT => freq_INFO_OUT,
+ RAND_OUT => freq_RAND_OUT,
+ TYPE_OUT => freq_TYPE_OUT,
+ NUM_OUT => freq_NUM_OUT,
+
+ RAND_FIFO_WRITE_OUT => freq_RAND_FIFO_WRITE_OUT,
+ RAND_FIFO_DATA_OUT => freq_RAND_FIFO_DATA_OUT,
+
+ DEBUG_OUT => freq_DEBUG_OUT
+ );
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Readout Request Module
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_arbiter_readout_request: arbiter_readout_request
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ START_IN => readout_START_IN,
+
+ -- IPU/ Readout (R) ports
+ SEND_OUT => readout_SEND_OUT,
+ INFO_OUT => readout_INFO_OUT,
+ RAND_OUT => readout_RAND_OUT,
+ TYPE_OUT => readout_TYPE_OUT,
+ NUM_OUT => readout_NUM_OUT,
+
+ RAND_FIFO_READ_OUT => readout_RAND_FIFO_READ_OUT,
+ RAND_FIFO_DATA_IN => rand_fifo_dout(7 downto 0),
+ RAND_FIFO_VALID_IN => rand_fifo_valid,
+
+ DEBUG_OUT => readout_DEBUG_OUT
+ );
+
+
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ -- The Aribter Controller
+ -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+ the_arbiter_controller: arbiter_controller
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ -- SYNC ports
+ SYNC_SENT_IN => sync_SYNC_SENT_OUT,
+ START_SENT_IN => sync_START_SENT_OUT,
+
+ -- Frame Request Ports
+ FR_START_OUT => actrl_FR_START_OUT,
+ AFL_OUT => actrl_AFL_OUT,
+ TRG_STATUS_BITS_IN => a_TRG_STATUS_BITS_OUT,
+ TRG_BUSY_IN => a_TRG_BUSY_OUT,
+ FRAMERATE_IN => trg_config(15 downto 0),
+
+ -- Readout Request Ports
+ R_START_OUT => actrl_R_START_OUT,
+ IPU_STATUS_BITS_IN => a_IPU_STATUS_BITS_OUT,
+ IPU_BUSY_IN => a_IPU_BUSY_OUT,
+
+ DEBUG_OUT => actrl_DEBUG_OUT
+ );
+ freq_START_IN <= actrl_FR_START_OUT;
+ freq_AFL_IN <= actrl_AFL_OUT;
+ readout_START_IN <= actrl_R_START_OUT;
+
+
+ the_bus_handler : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"b000", 1 => x"8000", 2 => x"c000", 3 => x"d000", 4 => x"e000", others => (others => '0')),
+ PORT_ADDR_MASK => (0 => 9, 1 => 10, 2 => 8, 3 => 9, 4 => 9, others => 0)
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ DAT_ADDR_IN => a_REGIO_ADDR_OUT,
+ DAT_DATA_IN => a_REGIO_DATA_OUT, -- data from TRB endpoint
+ DAT_DATA_OUT => a_REGIO_DATA_IN, -- data to TRB endpoint
+ DAT_READ_ENABLE_IN => a_REGIO_READ_ENABLE_OUT, -- read pulse
+ DAT_WRITE_ENABLE_IN => a_REGIO_WRITE_ENABLE_OUT, -- write pulse
+ DAT_TIMEOUT_IN => a_REGIO_TIMEOUT_OUT, -- access timed out
+ DAT_DATAREADY_OUT => a_REGIO_DATAREADY_IN, -- your data, master, as requested
+ DAT_WRITE_ACK_OUT => a_REGIO_WRITE_ACK_IN, -- data accepted
+ DAT_NO_MORE_DATA_OUT => a_REGIO_NO_MORE_DATA_IN, -- don't disturb me now
+ DAT_UNKNOWN_ADDR_OUT => a_REGIO_UNKNOWN_ADDR_IN, -- noone here to answer your request
+
+
+ --BUS_ADDR_OUT(0*16+15 downto 0*16+8) => open,
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => jtag_cmd_m26c_addr_in,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_ADDR_OUT(1*16+9 downto 1*16) => open,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+10) => open,
+ BUS_ADDR_OUT(2*16+7 downto 2*16) => com_settings_addr_in,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+8) => open,
+ BUS_ADDR_OUT(3*16+8 downto 3*16) => jtag_cmd_m26c_addr_in2,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
+ BUS_ADDR_OUT(4*16+8 downto 4*16) => jtag_cmd_m26c_addr_in3,
+ BUS_ADDR_OUT(4*16+15 downto 4*16+9) => open,
+ --BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => jtag_cmd_m26c_data_in,
+ BUS_DATA_OUT(1*32+7 downto 1*32) => open,
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => com_settings_data_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => jtag_cmd_m26c_data_in2,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => jtag_cmd_m26c_data_in3,
+ BUS_READ_ENABLE_OUT(0) => jtag_cmd_m26c_read_enable_in,
+ BUS_READ_ENABLE_OUT(1) => open,
+ BUS_READ_ENABLE_OUT(2) => com_settings_read_enable_in,
+ BUS_READ_ENABLE_OUT(3) => jtag_cmd_m26c_read_enable_in2,
+ BUS_READ_ENABLE_OUT(4) => jtag_cmd_m26c_read_enable_in3,
+ BUS_WRITE_ENABLE_OUT(0) => jtag_cmd_m26c_write_enable_in,
+ BUS_WRITE_ENABLE_OUT(1) => open,
+ BUS_WRITE_ENABLE_OUT(2) => com_settings_write_enable_in,
+ BUS_WRITE_ENABLE_OUT(3) => jtag_cmd_m26c_write_enable_in2,
+ BUS_WRITE_ENABLE_OUT(4) => jtag_cmd_m26c_write_enable_in3,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => jtag_cmd_m26c_data_out,
+ BUS_DATA_IN(1*32+31 downto 1*32) => x"0000_0000",
+ BUS_DATA_IN(2*32+31 downto 2*32) => com_settings_data_out,
+ BUS_DATA_IN(3*32+31 downto 3*32) => jtag_cmd_m26c_data_out2,
+ BUS_DATA_IN(4*32+31 downto 4*32) => jtag_cmd_m26c_data_out3,
+ BUS_DATAREADY_IN(0) => jtag_cmd_m26c_dataready_out,
+ BUS_DATAREADY_IN(1) => '0',
+ BUS_DATAREADY_IN(2) => com_settings_dataready_out,
+ BUS_DATAREADY_IN(3) => jtag_cmd_m26c_dataready_out2,
+ BUS_DATAREADY_IN(4) => jtag_cmd_m26c_dataready_out3,
+ BUS_WRITE_ACK_IN(0) => jtag_cmd_m26c_write_ack_out,
+ BUS_WRITE_ACK_IN(1) => '0',
+ BUS_WRITE_ACK_IN(2) => com_settings_write_ack_out,
+ BUS_WRITE_ACK_IN(3) => jtag_cmd_m26c_write_ack_out2,
+ BUS_WRITE_ACK_IN(4) => jtag_cmd_m26c_write_ack_out3,
+ BUS_NO_MORE_DATA_IN(0) => jtag_cmd_m26c_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => com_settings_no_more_data_out,
+ BUS_NO_MORE_DATA_IN(3) => jtag_cmd_m26c_no_more_data_out2,
+ BUS_NO_MORE_DATA_IN(4) => jtag_cmd_m26c_no_more_data_out3,
+ BUS_UNKNOWN_ADDR_IN(0) => jtag_cmd_m26c_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => com_settings_unknown_addr_out,
+ BUS_UNKNOWN_ADDR_IN(3) => jtag_cmd_m26c_unknown_addr_out2,
+ BUS_UNKNOWN_ADDR_IN(4) => jtag_cmd_m26c_unknown_addr_out3,
+
+ STAT_DEBUG => open
+ );
+
+
+ the_jtag3_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms3,
+ JTAG_TCK_OUT => jtag_tck3,
+ JTAG_TDI_OUT => jtag_tdi3,
+ JTAG_TDO_IN => jtag_tdo_evtlinv3,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in3,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out3,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in3(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in3,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in3,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out3,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out3,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out3,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out3,
+
+ RUN_REQUEST_IN => run_jtag(2),
+ WRITE_ONCE_REQUEST_IN => trbnet_trigger_jtag_write_once(2),
+ MY_STATUS_OUT => open,
+ IDLE_OUT => idle_out3,
+ REQUEST_RESET_OUT => request_reset(2),
+ --BUS_TIMEOUT_IN : in std_logic;
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished3,
+
+ READ_ID_ERRORS_COUNT_OUT => jtag3cmd_READ_ID_ERRORS_COUNT_OUT,
+ WRITE_ERRORS_COUNT_OUT => jtag3cmd_WRITE_ERRORS_COUNT_OUT,
+ DATA_CHANGED_COUNT_OUT => jtag3cmd_DATA_CHANGED_COUNT_OUT,
+ SAMPLING_ERRORS_COUNT_OUT => jtag3cmd_SAMPLING_ERRORS_COUNT_OUT,
+ RUN_COUNTER_OUT => jtag3cmd_RUN_COUNTER_OUT,
+
+ STARTED_OUT => jtag3cmd_STARTED_OUT,
+ LAST_RUN_SUCCESSFUL_OUT => jtag3cmd_LAST_RUN_SUCCESSFUL_OUT,
+ LAST_DATA_CHANGED_OUT => jtag3cmd_LAST_DATA_CHANGED_OUT,
+ LAST_WRITE_ERRORS_OUT => jtag3cmd_LAST_WRITE_ERRORS_OUT,
+ LAST_READ_ERRORS_OUT => jtag3cmd_LAST_READ_ERRORS_OUT,
+ CRC_ERROR_OUT => jtag3cmd_CRC_ERROR_OUT
+
+ );
+
+ the_jtag2_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms2,
+ JTAG_TCK_OUT => jtag_tck2,
+ JTAG_TDI_OUT => jtag_tdi2,
+ JTAG_TDO_IN => jtag_tdo_evtlinv2,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in2,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out2,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in2(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in2,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in2,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out2,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out2,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out2,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out2,
+
+ RUN_REQUEST_IN => run_jtag(1),
+ WRITE_ONCE_REQUEST_IN => trbnet_trigger_jtag_write_once(1),
+ MY_STATUS_OUT => open,
+ IDLE_OUT => idle_out2,
+ REQUEST_RESET_OUT => request_reset(1),
+
+ --BUS_TIMEOUT_IN : in std_logic;
+
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished2,
+
+ READ_ID_ERRORS_COUNT_OUT => jtag2cmd_READ_ID_ERRORS_COUNT_OUT,
+ WRITE_ERRORS_COUNT_OUT => jtag2cmd_WRITE_ERRORS_COUNT_OUT,
+ DATA_CHANGED_COUNT_OUT => jtag2cmd_DATA_CHANGED_COUNT_OUT,
+ SAMPLING_ERRORS_COUNT_OUT => jtag2cmd_SAMPLING_ERRORS_COUNT_OUT,
+ RUN_COUNTER_OUT => jtag2cmd_RUN_COUNTER_OUT,
+
+ STARTED_OUT => jtag2cmd_STARTED_OUT,
+ LAST_RUN_SUCCESSFUL_OUT => jtag2cmd_LAST_RUN_SUCCESSFUL_OUT,
+ LAST_DATA_CHANGED_OUT => jtag2cmd_LAST_DATA_CHANGED_OUT,
+ LAST_WRITE_ERRORS_OUT => jtag2cmd_LAST_WRITE_ERRORS_OUT,
+ LAST_READ_ERRORS_OUT => jtag2cmd_LAST_READ_ERRORS_OUT,
+ CRC_ERROR_OUT => jtag2cmd_CRC_ERROR_OUT
+
+ );
+
+ the_jtag1_cmd_m26c : jtag_cmd_m26c
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+
+ JTAG_TMS_OUT => jtag_tms,
+ JTAG_TCK_OUT => jtag_tck,
+ JTAG_TDI_OUT => jtag_tdi,
+ JTAG_TDO_IN => jtag_tdo_evtlinv,
+
+ BUS_DATA_IN => jtag_cmd_m26c_data_in,
+ BUS_DATA_OUT => jtag_cmd_m26c_data_out,
+ BUS_ADDR_IN => jtag_cmd_m26c_addr_in(8 downto 0),
+ BUS_READ_IN => jtag_cmd_m26c_read_enable_in,
+ BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in,
+
+ BUS_DATAREADY_OUT => jtag_cmd_m26c_dataready_out,
+ BUS_NO_MORE_DATA_OUT => jtag_cmd_m26c_no_more_data_out,
+ BUS_WRITE_ACK_OUT => jtag_cmd_m26c_write_ack_out,
+ BUS_UNKNOWN_ADDR_OUT => jtag_cmd_m26c_unknown_addr_out,
+
+ RUN_REQUEST_IN => run_jtag(0),
+ WRITE_ONCE_REQUEST_IN => trbnet_trigger_jtag_write_once(0),
+ MY_STATUS_OUT => my_status,
+ IDLE_OUT => idle_out,
+ REQUEST_RESET_OUT => request_reset(0),
+ --BUS_TIMEOUT_IN : in std_logic;
+ PROG_JTAG_FINISHED_OUT => prog_jtag_finished,
+
+ READ_ID_ERRORS_COUNT_OUT => jtag1cmd_READ_ID_ERRORS_COUNT_OUT,
+ WRITE_ERRORS_COUNT_OUT => jtag1cmd_WRITE_ERRORS_COUNT_OUT,
+ DATA_CHANGED_COUNT_OUT => jtag1cmd_DATA_CHANGED_COUNT_OUT,
+ SAMPLING_ERRORS_COUNT_OUT => jtag1cmd_SAMPLING_ERRORS_COUNT_OUT,
+ RUN_COUNTER_OUT => jtag1cmd_RUN_COUNTER_OUT,
+
+ STARTED_OUT => jtag1cmd_STARTED_OUT,
+ LAST_RUN_SUCCESSFUL_OUT => jtag1cmd_LAST_RUN_SUCCESSFUL_OUT,
+ LAST_DATA_CHANGED_OUT => jtag1cmd_LAST_DATA_CHANGED_OUT,
+ LAST_WRITE_ERRORS_OUT => jtag1cmd_LAST_WRITE_ERRORS_OUT,
+ LAST_READ_ERRORS_OUT => jtag1cmd_LAST_READ_ERRORS_OUT,
+ CRC_ERROR_OUT => jtag1cmd_CRC_ERROR_OUT
+
+ );
+
+-- Reset Requests from JTAG_CMD_M26C entities are two clock cycles long pulses that is synchronized
+-- to 80 MHz clock
+SYNC_REQUEST_RESET : process (MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ request_reset_MAPS_CLK <= request_reset;
+ end if;
+end process;
+
+ --JTAG_TDO_TEST_OUT <= JTAG_TDO_IN;
+SYNC_TRBNET_TRIGGERS: process (MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ -- allchains_initialization_sequence
+ trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence;
+ trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK;
+ -- reset pulse
+ trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse;
+ trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK;
+
+ -- start pulse
+ trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK <= trbnet_trigger_allchains_start_pulse;
+ trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK <= trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK;
+
+ for i in 2 downto 0 loop
+ -- initialization_sequence s
+ trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) <=
+ trbnet_trigger_initialization_sequence(i);
+ trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i) <=
+ trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i);
+ -- reset pulse
+ trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) <= trbnet_trigger_reset_pulse(i);
+ trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i) <= trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i);
+ -- start pulse
+ trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) <= trbnet_trigger_start_pulse(i);
+ trbnet_trigger_start_pulse_sync2_MAPS_CLK(i) <= trbnet_trigger_start_pulse_sync1_MAPS_CLK(i);
+ -- jtag_run_noreset
+ trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset(i);
+ trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i);
+ end loop;
+
+
+ if(RESET='1') then
+ trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK <= '0';
+ trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK <= '0';
+ trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK <= '0';
+ trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK <= '0';
+ trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK <= '0';
+ trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK <= '0';
+ for i in 2 downto 0 loop
+ trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) <= '0';
+ trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i) <= '0';
+ -- reset pulse
+ trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) <= '0';
+ trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i) <= '0';
+ -- start pulse
+ trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) <= '0';
+ trbnet_trigger_start_pulse_sync2_MAPS_CLK(i) <= '0';
+ -- jtag_run_noreset
+ trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) <= '0';
+ trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i) <= '0';
+ end loop;
+ end if;
+ end if;
+end process;
+
+TRBNET_TRIGGERS_MAPS_CLK: process (trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK, trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK,
+trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK,
+trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK,
+trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK,
+trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK,
+trbnet_trigger_initialization_sequence_sync1_MAPS_CLK,
+trbnet_trigger_initialization_sequence_sync2_MAPS_CLK,
+trbnet_trigger_reset_pulse_sync1_MAPS_CLK,
+trbnet_trigger_reset_pulse_sync2_MAPS_CLK,
+trbnet_trigger_start_pulse_sync1_MAPS_CLK,
+trbnet_trigger_start_pulse_sync2_MAPS_CLK,
+trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK,
+trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK)
+begin
+ -- allchains_initialization_sequence
+ trbnet_trigger_allchains_initialization_sequence_MAPS_CLK <= trbnet_trigger_allchains_initialization_sequence_sync1_MAPS_CLK and not trbnet_trigger_allchains_initialization_sequence_sync2_MAPS_CLK;
+ -- allchains reset pulse
+ trbnet_trigger_allchains_reset_pulse_MAPS_CLK <= trbnet_trigger_allchains_reset_pulse_sync1_MAPS_CLK and not trbnet_trigger_allchains_reset_pulse_sync2_MAPS_CLK;
+ -- start pulse
+ trbnet_trigger_allchains_start_pulse_MAPS_CLK <= trbnet_trigger_allchains_start_pulse_sync1_MAPS_CLK and not trbnet_trigger_allchains_start_pulse_sync2_MAPS_CLK;
+ -- initialization_sequence s
+ for i in 2 downto 0 loop
+ trbnet_trigger_initialization_sequence_MAPS_CLK(i) <=
+ trbnet_trigger_initialization_sequence_sync1_MAPS_CLK(i) and not trbnet_trigger_initialization_sequence_sync2_MAPS_CLK(i);
+ -- reset pulse
+ trbnet_trigger_reset_pulse_MAPS_CLK(i) <= trbnet_trigger_reset_pulse_sync1_MAPS_CLK(i) and not trbnet_trigger_reset_pulse_sync2_MAPS_CLK(i);
+ -- start pulse
+ trbnet_trigger_start_pulse_MAPS_CLK(i) <= trbnet_trigger_start_pulse_sync1_MAPS_CLK(i) and not trbnet_trigger_start_pulse_sync2_MAPS_CLK(i);
+ trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_sync1_MAPS_CLK(i) and not trbnet_trigger_jtag_run_noreset_sync2_MAPS_CLK(i);
+ end loop;
+
+end process;
+
+MAPS_RESET_PULSE : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ for i in 2 downto 0 loop
+ if(to_integer(MAPS_reset_count(i)) = 0) then
+ MAPS_reset(i) <= '0';
+ else
+ MAPS_reset_count(i) <= MAPS_reset_count(i) - 1;
+ end if;
+
+ if(trbnet_trigger_reset_pulse_MAPS_CLK(i) = '1' or trigger_reset_pulse_MAPS_CLK(i) = '1' or trigger2_reset_pulse_MAPS_CLK(i) = '1'
+ or trbnet_trigger_allchains_reset_pulse_MAPS_CLK = '1') then --or trigger_allchains_reset_pulse_MAPS_CLK = '1') then
+ MAPS_reset_count(i) <= "1100100"; -- 101 clock cycles reset (on for 100,...,4,3,2,1,0)
+ MAPS_reset(i) <= '1';
+ end if;
+
+
+ if(RESET='1') then
+ MAPS_reset(i) <= '0';
+ MAPS_reset_count(i) <= (others => '0');
+ end if;
+ end loop;
+ end if;
+end process;
+
+MAPS_START_PULSE : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ for i in 2 downto 0 loop
+ if(to_integer(MAPS_start_count(i)) = 0) then
+ MAPS_start(i) <= '0';
+ else
+ MAPS_start_count(i) <= MAPS_start_count(i) - 1;
+ end if;
+
+ if(trbnet_trigger_start_pulse_MAPS_CLK(i) = '1' or trigger_start_pulse_MAPS_CLK(i) = '1'
+ or trbnet_trigger_allchains_start_pulse_MAPS_CLK = '1' or trigger_allchains_start_pulse_MAPS_CLK = '1') then
+ MAPS_start_count(i) <= "1000000"; -- 65 clock cycles start (on for 64,...,4,3,2,1,0)
+ MAPS_start(i) <= '1';
+ end if;
+
+ if(RESET='1') then
+ MAPS_start(i) <= '0';
+ MAPS_start_count(i) <= (others => '0');
+ end if;
+ end loop;
+ end if;
+end process;
+
+
+-- JTAG_RUN_NORESET : process(MAPS_CLK, RESET)
+-- begin
+-- if(rising_edge(MAPS_CLK)) then
+-- for i in 2 downto 0 loop
+-- -- wait for completion of potential copy ram request
+-- if(run_window_counter(i) = run_window_counter_zero) then
+-- run_jtag_MAPS_CLK(i) <= '0';
+-- else
+-- run_window_counter(i) <= run_window_counter(i) - 1;
+-- end if;
+--
+-- if(trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) = '1' or trigger_jtag_run_MAPS_CLK(i) = '1' or trigger_jtag_run2_MAPS_CLK(i) = '1') then
+-- run_jtag_MAPS_CLK(i) <= '1';
+-- run_window_counter(i) <= "111111111111";
+-- end if;
+-- end loop;
+-- if(RESET='1') then
+-- run_jtag_MAPS_CLK <= (others => '0');
+-- for i in 2 downto 0 loop
+-- run_window_counter(i) <= (others => '0');
+-- end loop;
+-- end if;
+-- end if;
+-- end process;
+--replaces process, because jtag_cmd_m26c internally saves request now
+JTAG_RUN_NORESET : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ for i in 2 downto 0 loop
+ run_jtag_MAPS_CLK(i) <= trbnet_trigger_jtag_run_noreset_MAPS_CLK(i) or trigger_jtag_run_MAPS_CLK(i) or trigger_jtag_run2_MAPS_CLK(i);
+ end loop;
+ end if;
+end process;
+
+
+RUN_JTAG_SYNC : process(CLK, RESET)
+begin
+ if(rising_edge(CLK)) then
+ run_jtag <= run_jtag_MAPS_CLK;
+ if(RESET='1') then
+ run_jtag <= (others => '0');
+ end if;
+ end if;
+end process;
+
+TRIGGER_INITIALIZATION_SEQUENCE_PULSE0 : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+-- for i in 2 downto 0 loop
+ trigger_start_pulse_MAPS_CLK(0) <= '0';
+ trigger_reset_pulse_MAPS_CLK(0) <= '0';
+ trigger_jtag_run_MAPS_CLK(0) <= '0';
+ case init_seq_MAPS_CLK_0 is
+ when isIDLE =>
+ when isRUN_JTAG_WAIT1 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT2;
+ when isRUN_JTAG_WAIT2 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT3;
+ when isRUN_JTAG_WAIT3 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT4;
+ when isRUN_JTAG_WAIT4 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT5;
+ when isRUN_JTAG_WAIT5 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT6;
+ when isRUN_JTAG_WAIT6 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT7;
+ when isRUN_JTAG_WAIT7 =>
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG;
+ when isRUN_JTAG =>
+ if(resetafterfirstwrite(0) = '1') then
+ if(request_reset(0) = '1') then
+ trigger_reset_pulse_MAPS_CLK(0) <= '1';
+ end if;
+ end if;
+ -- wait for completion of potential copy ram request and then finishing of run
+ if(idle_out_MAPS_CLK(0) = '1') then
+ init_seq_MAPS_CLK_0 <= isWAITBEFORESTART;
+ waitbeforestart_counter(0) <= waitbeforestart;
+ end if;
+ when isWAITBEFORESTART =>
+ waitbeforestart_counter(0) <= waitbeforestart_counter(0) -1;
+ if(waitbeforestart_counter(0) = waitbeforestart_counter_zero) then
+ trigger_start_pulse_MAPS_CLK(0) <= '1';
+ init_seq_MAPS_CLK_0 <= isIDLE;
+ end if;
+ end case;
+ if(trbnet_trigger_initialization_sequence_MAPS_CLK(0) = '1') then
+ if(resetbeforeinit(0) = '1') then
+ trigger_reset_pulse_MAPS_CLK(0) <= '1';
+ end if;
+ trigger_jtag_run_MAPS_CLK(0) <= '1';
+ init_seq_MAPS_CLK_0 <= isRUN_JTAG_WAIT1;
+ end if;
+ if(RESET = '1') then
+ init_seq_MAPS_CLK_0 <= isIDLE;
+ end if;
+-- end loop;
+ end if;
+end process;
+
+TRIGGER_INITIALIZATION_SEQUENCE_PULSE1 : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+-- for i in 2 downto 0 loop
+ trigger_start_pulse_MAPS_CLK(1) <= '0';
+ trigger_reset_pulse_MAPS_CLK(1) <= '0';
+ trigger_jtag_run_MAPS_CLK(1) <= '0';
+ case init_seq_MAPS_CLK_1 is
+ when isIDLE =>
+ when isRUN_JTAG_WAIT1 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT2;
+ when isRUN_JTAG_WAIT2 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT3;
+ when isRUN_JTAG_WAIT3 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT4;
+ when isRUN_JTAG_WAIT4 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT5;
+ when isRUN_JTAG_WAIT5 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT6;
+ when isRUN_JTAG_WAIT6 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT7;
+ when isRUN_JTAG_WAIT7 =>
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG;
+ when isRUN_JTAG =>
+ if(resetafterfirstwrite(1) = '1') then
+ if(request_reset(1) = '1') then
+ trigger_reset_pulse_MAPS_CLK(1) <= '1';
+ end if;
+ end if;
+ -- wait for completion of potential copy ram request and then finishing of run
+ if(idle_out_MAPS_CLK(1) = '1') then
+ init_seq_MAPS_CLK_1 <= isWAITBEFORESTART;
+ waitbeforestart_counter(1) <= waitbeforestart;
+ end if;
+ when isWAITBEFORESTART =>
+ waitbeforestart_counter(1) <= waitbeforestart_counter(1) -1;
+ if(waitbeforestart_counter(1) = waitbeforestart_counter_zero) then
+ trigger_start_pulse_MAPS_CLK(1) <= '1';
+ init_seq_MAPS_CLK_1 <= isIDLE;
+ end if;
+ end case;
+ if(trbnet_trigger_initialization_sequence_MAPS_CLK(1) = '1') then
+ if(resetbeforeinit(1) = '1') then
+ trigger_reset_pulse_MAPS_CLK(1) <= '1';
+ end if;
+ trigger_jtag_run_MAPS_CLK(1) <= '1';
+ init_seq_MAPS_CLK_1 <= isRUN_JTAG_WAIT1;
+ end if;
+ if(RESET = '1') then
+ init_seq_MAPS_CLK_1 <= isIDLE;
+ end if;
+-- end loop;
+ end if;
+end process;
+
+TRIGGER_INITIALIZATION_SEQUENCE_PULSE2 : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ --for i in 2 downto 0 loop
+ trigger_start_pulse_MAPS_CLK(2) <= '0';
+ trigger_reset_pulse_MAPS_CLK(2) <= '0';
+ trigger_jtag_run_MAPS_CLK(2) <= '0';
+ case init_seq_MAPS_CLK_2 is
+ when isIDLE =>
+ when isRUN_JTAG_WAIT1 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT2;
+ when isRUN_JTAG_WAIT2 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT3;
+ when isRUN_JTAG_WAIT3 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT4;
+ when isRUN_JTAG_WAIT4 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT5;
+ when isRUN_JTAG_WAIT5 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT6;
+ when isRUN_JTAG_WAIT6 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT7;
+ when isRUN_JTAG_WAIT7 =>
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG;
+ when isRUN_JTAG =>
+ if(resetafterfirstwrite(2) = '1') then
+ if(request_reset(2) = '1') then
+ trigger_reset_pulse_MAPS_CLK(2) <= '1';
+ end if;
+ end if;
+ -- wait for completion of potential copy ram request and then finishing of run
+ if(idle_out_MAPS_CLK(2) = '1') then
+ init_seq_MAPS_CLK_2 <= isWAITBEFORESTART;
+ waitbeforestart_counter(2) <= waitbeforestart;
+ end if;
+ when isWAITBEFORESTART =>
+ waitbeforestart_counter(2) <= waitbeforestart_counter(2) -1;
+ if(waitbeforestart_counter(2) = waitbeforestart_counter_zero) then
+ trigger_start_pulse_MAPS_CLK(2) <= '1';
+ init_seq_MAPS_CLK_2 <= isIDLE;
+ end if;
+ end case;
+ if(trbnet_trigger_initialization_sequence_MAPS_CLK(2) = '1') then
+ if(resetbeforeinit(2) = '1') then
+ trigger_reset_pulse_MAPS_CLK(2) <= '1';
+ end if;
+ trigger_jtag_run_MAPS_CLK(2) <= '1';
+ init_seq_MAPS_CLK_2 <= isRUN_JTAG_WAIT1;
+ end if;
+ if(RESET = '1') then
+ init_seq_MAPS_CLK_2 <= isIDLE;
+ end if;
+ -- end loop;
+ end if;
+end process;
+
+TRIGGER_ALLCHAINS_INITIALIZATION_SEQUENCE_PULSE : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ trigger2_reset_pulse_MAPS_CLK <= "000";
+ trigger_jtag_run2_MAPS_CLK <= "000";
+ trigger_allchains_start_pulse_MAPS_CLK <= '0';
+ case init_seq_allchains_MAPS_CLK is
+ when isIDLE =>
+ when isRUN_JTAG_WAIT1 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT2;
+ when isRUN_JTAG_WAIT2 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT3;
+ when isRUN_JTAG_WAIT3 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT4;
+ when isRUN_JTAG_WAIT4 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT5;
+ when isRUN_JTAG_WAIT5 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT6;
+ when isRUN_JTAG_WAIT6 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT7;
+ when isRUN_JTAG_WAIT7 =>
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG;
+ when isRUN_JTAG =>
+ for i in 2 downto 0 loop
+ if(resetafterfirstwrite(i) = '1') then
+ if(request_reset_MAPS_CLK(i) = '1') then
+ trigger2_reset_pulse_MAPS_CLK(i) <= '1';
+ end if;
+ end if;
+ end loop;
+ if(idle_out_MAPS_CLK(0) = '1' and idle_out_MAPS_CLK(1) = '1' and idle_out_MAPS_CLK(2) = '1') then
+ init_seq_allchains_MAPS_CLK <= isWAITBEFORESTART;
+ waitbeforestart_counter_allchains <= waitbeforestart;
+ end if;
+ when isWAITBEFORESTART =>
+ waitbeforestart_counter_allchains <= waitbeforestart_counter_allchains -1;
+ if(waitbeforestart_counter_allchains = waitbeforestart_counter_zero) then
+ trigger_allchains_start_pulse_MAPS_CLK <= '1';
+ init_seq_allchains_MAPS_CLK <= isIDLE;
+ end if;
+ end case;
+ if(trbnet_trigger_allchains_initialization_sequence_MAPS_CLK = '1') then
+ for i in 2 downto 0 loop
+ if(resetbeforeinit(i) = '1') then
+ trigger2_reset_pulse_MAPS_CLK(i) <= '1';
+ end if;
+ end loop;
+ trigger_jtag_run2_MAPS_CLK <= "111";
+ init_seq_allchains_MAPS_CLK <= isRUN_JTAG_WAIT1;
+ end if;
+
+ if(RESET = '1') then
+ init_seq_allchains_MAPS_CLK <= isIDLE;
+ end if;
+ end if;
+end process;
+
+
+
+-- spill trigger (MAPS_CLK)
+JTAG_CMD_M26C_MAPS_CLK : process(MAPS_CLK, RESET)
+begin
+ if(rising_edge(MAPS_CLK)) then
+ prog_jtag_finished_MAPS_CLK(0) <= prog_jtag_finished;
+ prog_jtag_finished_MAPS_CLK(1) <= prog_jtag_finished2;
+ prog_jtag_finished_MAPS_CLK(2) <= prog_jtag_finished3;
+ idle_out_MAPS_CLK(0) <= idle_out;
+ idle_out_MAPS_CLK(1) <= idle_out2;
+ idle_out_MAPS_CLK(2) <= idle_out3;
+ if(RESET='1') then
+ prog_jtag_finished_MAPS_CLK(0) <= '0';
+ prog_jtag_finished_MAPS_CLK(1) <= '0';
+ prog_jtag_finished_MAPS_CLK(2) <= '0';
+ idle_out_MAPS_CLK(0) <= '0';
+ idle_out_MAPS_CLK(1) <= '0';
+ idle_out_MAPS_CLK(2) <= '0';
+ end if;
+ end if;
+end process;
+
+
+
+
+-- the_IODELAY : IODELAY
+-- generic map (
+-- DELAY_SRC => "I", -- Specify which input port to be used
+-- -- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
+-- HIGH_PERFORMANCE_MODE => TRUE, -- TRUE specifies lower jitter
+-- -- at expense of more power
+-- IDELAY_TYPE => "DEFAULT", -- "DEFAULT", "FIXED" or "VARIABLE"
+-- IDELAY_VALUE => 0, -- 0 to 63 tap values
+-- ODELAY_VALUE => 0, -- 0 to 63 tap values
+-- REFCLK_FREQUENCY => 200.0, -- Frequency used for IDELAYCTRL
+-- -- 175.0 to 225.0
+-- SIGNAL_PATTERN => "DATA") -- Input signal type, "CLOCK" or "DATA"
+-- port map (
+-- DATAOUT => DATAOUT, -- 1-bit delayed data output
+-- C => C, -- 1-bit clock input
+-- CE => CE, -- 1-bit clock enable input
+-- DATAIN => DATAIN, -- 1-bit internal data input
+-- IDATAIN => IDATAIN, -- 1-bit input data input (connect to port)
+-- INC => INC, -- 1-bit increment/decrement input
+-- ODATAIN => ODATAIN, -- 1-bit output data input
+-- RST => RST, -- 1-bit active high, synch reset input
+-- T => T -- 1-bit 3-state control input
+-- );
+
+
+
+--*************************************************************************************************************************
+-- The LOGIC **************************************************************************************************************
+--*************************************************************************************************************************
+
+
+
+ -- LEDs
+ DGOOD <= not tlk_STAT_OP(9);
+ DBAD <= not (tlk_STAT(36)); -- no error, but not ERROR_OK
+ DINT <= counter(25);
+ DWAIT <= not (tlk_STAT_OP(10) or tlk_STAT_OP(11));
+--
+
+
+
+
+-- MAPS CLK output
+-- Inst_dcm3: dcm3 PORT MAP(
+-- CLKIN_IN => TLK_RX_CLK,
+-- RST_IN => '0',
+-- CLKFX_OUT => MAPS_CLK,
+-- CLK0_OUT => open,
+-- LOCKED_OUT => open
+-- );
+
+ Inst_dcm4: dcm4 PORT MAP(
+ CLKIN_IN => TLK_RX_CLK,
+ RST_IN => '0',
+ CLKFX_OUT => MAPS_CLK,
+ CLKIN_IBUFG_OUT => open,
+ CLK0_OUT => dcm4_CLK0_OUT,
+ LOCKED_OUT => open
+ );
+
+
+ --TEST_out <= jtag_tck;
+ --TEST_out <= prog_jtag_finished;
+ --TEST_out <= '0';
+ JTAG1_TCK_OUT <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
+ JTAG1_TMS_OUT <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
+ JTAG1_TDI_OUT <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
+ JTAG2_TCK_OUT <= (jtag_tck2 xor signals_invert2(6)) when signals_invert2(7) = '1' else signals_invert2(6);
+ JTAG2_TMS_OUT <= (jtag_tms2 xor signals_invert2(4)) when signals_invert2(5) = '1' else signals_invert2(4);
+ JTAG2_TDI_OUT <= (jtag_tdi2 xor signals_invert2(2)) when signals_invert2(3) = '1' else signals_invert2(2);
+ JTAG3_TCK_OUT <= (jtag_tck3 xor signals_invert3(6)) when signals_invert3(7) = '1' else signals_invert3(6);
+ JTAG3_TMS_OUT <= (jtag_tms3 xor signals_invert3(4)) when signals_invert3(5) = '1' else signals_invert3(4);
+ JTAG3_TDI_OUT <= (jtag_tdi3 xor signals_invert3(2)) when signals_invert3(3) = '1' else signals_invert3(2);
+ -- x1_saddr(3) <= (jtag_tck xor signals_invert(6)) when signals_invert(7) = '1' else signals_invert(6);
+ -- x1_saddr(2) <= (jtag_tms xor signals_invert(4)) when signals_invert(5) = '1' else signals_invert(4);
+ -- x1_saddr(1) <= (jtag_tdi xor signals_invert(2)) when signals_invert(3) = '1' else signals_invert(2);
+ -- x1_saddr(0) <= JTAG_TDO_IN;
+
+ jtag_tdo_evtlinv <= (JTAG1_TDO_IN xor signals_invert(0)) when signals_invert(1) = '1' else signals_invert(0);
+ jtag_tdo_evtlinv2 <= (JTAG2_TDO_IN xor signals_invert2(0)) when signals_invert2(1) = '1' else signals_invert2(0);
+ jtag_tdo_evtlinv3 <= (JTAG3_TDO_IN xor signals_invert3(0)) when signals_invert3(1) = '1' else signals_invert3(0);
+
+ MAPS_CLK1_out_int <= signals_invert(12);
+ MAPS_CLK1_out_int2 <= (not signals_invert(12)) when signals_invert(13) = '1' else signals_invert(12);
+ MAPS_CLK2_out_int <= signals_invert2(12);
+ MAPS_CLK2_out_int2 <= (not signals_invert2(12)) when signals_invert2(13) = '1' else signals_invert2(12);
+ MAPS_CLK3_out_int <= signals_invert3(12);
+ MAPS_CLK3_out_int2 <= (not signals_invert3(12)) when signals_invert3(13) = '1' else signals_invert3(12);
+
+ ODDR_MAPS_CLK1_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK1_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK1_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK1_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ ODDR_MAPS_CLK2_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK2_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK2_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK2_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ ODDR_MAPS_CLK3_out : ODDR
+ generic map(
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ port map (
+ Q => MAPS_CLK3_out, -- 1-bit DDR output
+ C => MAPS_CLK, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => MAPS_CLK3_out_int, -- 1-bit data input (positive edge) -- inverted output
+ D2 => MAPS_CLK3_out_int2, -- 1-bit data input (negative edge) -- inverted output
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+
+ -- MAPS_start_out
+ -- ODDR_MAPS_start_out : ODDR
+ -- generic map(
+ -- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ -- INIT => '0', -- Initial value for Q port ('1' or '0')
+ -- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ -- port map (
+ -- Q => MAPS_start_out, -- 1-bit DDR output
+ -- C => MAPS_CLK, -- 1-bit clock input
+ -- CE => '1', -- 1-bit clock enable input
+ -- D1 => not MAPS_start, -- 1-bit data input (positive edge) -- inverted output
+ -- D2 => not MAPS_start, -- 1-bit data input (negative edge) -- inverted output
+ -- R => '0', -- 1-bit reset input
+ -- S => '0' -- 1-bit set input
+ -- );
+ MAPS_start1_out <= (MAPS_start(0) xor signals_invert(8)) when signals_invert(9) = '1' else signals_invert(8); -- activated/deactivated and inverted/non-inverted
+ MAPS_start2_out <= (MAPS_start(1) xor signals_invert2(8)) when signals_invert2(9) = '1' else signals_invert2(8); -- activated/deactivated and inverted/non-inverted
+ MAPS_start3_out <= (MAPS_start(2) xor signals_invert3(8)) when signals_invert3(9) = '1' else signals_invert3(8); -- activated/deactivated and inverted/non-inverted
+-- -- DEBUG!!!! use three lines before for real
+-- MAPS_start1_out <= (MAPS_reset_count(0)(0) xor signals_invert(8)) when signals_invert(9) = '1' else signals_invert(8); -- activated/deactivated and inverted/non-inverted
+-- MAPS_start2_out <= (MAPS_reset_count(1)(0) xor signals_invert2(8)) when signals_invert2(9) = '1' else signals_invert2(8); -- activated/deactivated and inverted/non-inverted
+-- MAPS_start3_out <= (MAPS_reset_count(2)(0) xor signals_invert3(8)) when signals_invert3(9) = '1' else signals_invert3(8); -- activated/deactivated and inverted/non-inverted
+
+
+ -- MAPS_reset_out
+ -- ODDR_MAPS_reset_out : ODDR
+ -- generic map(
+ -- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ -- INIT => '0', -- Initial value for Q port ('1' or '0')
+ -- SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
+ -- port map (
+ -- Q => MAPS_reset_out, -- 1-bit DDR output
+ -- C => MAPS_CLK, -- 1-bit clock input
+ -- CE => '1', -- 1-bit clock enable input
+ -- D1 => not MAPS_reset, -- 1-bit data input (positive edge) -- inverted output
+ -- D2 => not MAPS_reset, -- 1-bit data input (negative edge) -- inverted output
+ -- R => '0', -- 1-bit reset input
+ -- S => '0' -- 1-bit set input
+ -- );
+ --MAPS_reset_out <= not MAPS_reset;
+ MAPS_reset1_out <= (MAPS_reset(0) xor signals_invert(10)) when signals_invert(11) = '1' else signals_invert(10);
+ MAPS_reset2_out <= (MAPS_reset(1) xor signals_invert2(10)) when signals_invert2(11) = '1' else signals_invert2(10);
+ MAPS_reset3_out <= (MAPS_reset(2) xor signals_invert3(10)) when signals_invert3(11) = '1' else signals_invert3(10);
+
+
+ com_settings_all : process
+ begin
+ wait until (CLK'event and CLK='1');
+ com_settings_write_ack_out <= '0';
+ com_settings_dataready_out <= '0';
+ com_settings_unknown_addr_out <= '0';
+ com_settings_no_more_data_out <= '0';
+ if(com_settings_write_enable_in_last = '0') then
+ -- reset triggers after 2 clock cycles at 100 MHz, to be able to sample at 80 MHz
+ trbnet_trigger_allchains_initialization_sequence <= '0';
+ trbnet_trigger_allchains_reset_pulse <= '0';
+ trbnet_trigger_allchains_start_pulse <= '0';
+ trbnet_trigger_initialization_sequence <= (others => '0');
+ trbnet_trigger_reset_pulse <= (others => '0');
+ trbnet_trigger_start_pulse <= (others => '0');
+ trbnet_trigger_jtag_run_noreset <= (others => '0');
+ trbnet_trigger_jtag_write_once <= (others => '0');
+ end if;
+ com_settings_write_enable_in_last <= com_settings_write_enable_in;
+ if(com_settings_write_enable_in = '1') then
+ if(com_settings_addr_in = x"01") then
+ --fet_counter_limit <= com_settings_data_in;
+ --com_settings_write_ack_out <= '1';
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"02") then
+ --jcounter_initvalue <= com_settings_data_in(28 downto 0);
+ --com_settings_write_ack_out <= '1';
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"03") then
+ trbnet_trigger_allchains_initialization_sequence <= '1';
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"06") then
+ signals_invert <= com_settings_data_in(13 downto 0); -- 13-12: MAPS_CLK, 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"07") then
+ waitbeforestart <= unsigned(com_settings_data_in(27 downto 0));
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"08") then
+ signals_invert2 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"09") then
+ signals_invert3 <= com_settings_data_in(13 downto 0); -- (13-12: MAPS_CLK), 11-10: RESET, 9-8: START, 7-6: TCK, 5-4: TMS, 3-2: TDI, 1-0: TDO
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0a") then
+ trbnet_trigger_allchains_reset_pulse <= com_settings_data_in(0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0b") then
+ trbnet_trigger_allchains_start_pulse <= com_settings_data_in(0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0c") then
+ trbnet_trigger_initialization_sequence <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0d") then
+ trbnet_trigger_reset_pulse <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0e") then
+ trbnet_trigger_start_pulse <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"0f") then
+ trbnet_trigger_jtag_run_noreset <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"10") then
+ resetbeforeinit <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"11") then
+ resetafterfirstwrite <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ elsif(com_settings_addr_in = x"14") then
+ trbnet_trigger_jtag_write_once <= com_settings_data_in(2 downto 0);
+ com_settings_write_ack_out <= '1';
+ end if;
+ elsif(com_settings_read_enable_in = '1') then
+ if(com_settings_addr_in = x"01") then
+ com_settings_data_out <= (others => '0');
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"02") then
+ com_settings_data_out <= (others => '0');
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"04") then
+ com_settings_data_out <= (others => '0');
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"05") then
+ com_settings_data_out <= (others => '0');
+ com_settings_unknown_addr_out <= '1';
+ elsif(com_settings_addr_in = x"06") then
+ com_settings_data_out(13 downto 0) <= signals_invert;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"07") then
+ com_settings_data_out(27 downto 0) <= std_logic_vector(waitbeforestart);
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"08") then
+ com_settings_data_out(13 downto 0) <= signals_invert2;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"09") then
+ com_settings_data_out(13 downto 0) <= signals_invert3;
+ com_settings_data_out(31 downto 14) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"10") then
+ com_settings_data_out(2 downto 0) <= resetbeforeinit;
+ com_settings_data_out(31 downto 3) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"11") then
+ com_settings_data_out(2 downto 0) <= resetafterfirstwrite;
+ com_settings_data_out(31 downto 3) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"12") then
+ com_settings_data_out(6 downto 0) <= std_logic_vector(MAPS_reset_count(0)(6 downto 0));
+ com_settings_data_out(31 downto 7) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ elsif(com_settings_addr_in = x"13") then
+ com_settings_data_out(6 downto 0) <= std_logic_vector(MAPS_start_count(0)(6 downto 0));
+ com_settings_data_out(31 downto 7) <= (others => '0');
+ com_settings_dataready_out <= '1';
+ end if;
+ end if;
+ if(RESET = '1') then
+ resetbeforeinit <= (others => '0');
+ resetafterfirstwrite <= (others => '0');
+ waitbeforestart <= (others => '0');
+
+ com_settings_data_out <= (others => '0');
+ com_settings_dataready_out <= '0';
+ com_settings_write_ack_out <= '0';
+ com_settings_write_enable_in_last <= '0';
+ com_settings_no_more_data_out <= '0';
+ com_settings_unknown_addr_out <= '0';
+
+
+ trbnet_trigger_allchains_initialization_sequence <= '0';
+ trbnet_trigger_allchains_reset_pulse <= '0';
+ trbnet_trigger_allchains_start_pulse <= '0';
+ trbnet_trigger_initialization_sequence <= (others => '0');
+ trbnet_trigger_reset_pulse <= (others => '0');
+ trbnet_trigger_start_pulse <= (others => '0');
+ trbnet_trigger_jtag_run_noreset <= (others => '0');
+ trbnet_trigger_jtag_write_once <= (others => '0');
+ end if;
+ end process;
+
+
+
+ FS_PB <= (others => '0');
+ ETRAX_IRQ <= '1';
+
+
+ ADO_JTTL_OUT(15 downto 8) <= (others => '0');
+ ADO_JTTL_OUT(7) <= '0';
+ ADO_JTTL_OUT(6) <= '0';
+ ADO_JTTL_OUT(5) <= '0';
+ ADO_JTTL_OUT(4) <= '0';
+ ADO_JTTL_OUT(3) <= sync_SYNC_OUT;
+ ADO_JTTL_OUT(2) <= sync_SYNC_OUT;
+ ADO_JTTL_OUT(1) <= sync_SYNC_OUT;
+ ADO_JTTL_OUT(0) <= sync_SYNC_OUT;
+
+ ADO_TTL1_OUT(0) <= '0';
+ ADO_TTL1_OUT(1) <= sync_SYNC_OUT;
+ ADO_TTL1_OUT(2) <= '0';
+ ADO_TTL1_OUT(3) <= sync_SYNC_OUT;
+ ADO_TTL2_OUT(0) <= '0';
+ ADO_TTL2_OUT(1) <= sync_SYNC_OUT;
+ ADO_TTL2_OUT(2) <= '0';
+ ADO_TTL2_OUT(3) <= sync_SYNC_OUT;
+
+
+ p_counter: process
+ begin
+ wait until rising_edge(CLK);
+ if RESET = '1' then
+ counter <= x"0000_0000";
+ else
+ counter <= std_logic_vector(unsigned(counter)+1);
+ end if;
+ end process;
+
+
+
+
+ SPILL_BREAK <= ADO_TTL1_IN(1);
+
+ p_spillbreak: process
+ begin
+ wait until rising_edge(CLK);
+ if RESET = '1' then
+ static_spill_reg <= '0';
+ pulsed_spill_reg <= '0';
+ else
+ if SPILL_BREAK = '1' then
+ static_spill_reg <= '1';
+ pulsed_spill_reg <= '1';
+ else
+ static_spill_reg <= '0';
+ end if;
+ if ipu_config(0) = '1' then
+ pulsed_spill_reg <= '0';
+ end if;
+ end if;
+ end process;
+
+
+
+
+
+end architecture basic;
jspc29 / jtag_mvd.git / commitdiff