--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.4
---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 16 -width 18 -depth 16 -rdata_width 18 -regout -no_enable -pe -1 -pf 7 -e
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 18 -depth 16 -rdata_width 18 -regout -no_enable -pe -1 -pf 7
--- Wed Jan 30 15:13:04 2013
+-- Fri Jan 23 17:47:08 2015
library IEEE;
use IEEE.std_logic_1164.all;
signal w_gdata_1: std_logic;
signal w_gdata_2: std_logic;
signal w_gdata_3: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
signal wptr_4: std_logic;
signal r_gdata_0: std_logic;
signal r_gdata_1: std_logic;
signal r_gdata_2: std_logic;
signal r_gdata_3: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
signal rptr_4: std_logic;
- signal edataout0: std_logic;
- signal edataout1: std_logic;
- signal edataout2: std_logic;
- signal edataout3: std_logic;
- signal edataout4: std_logic;
- signal edataout5: std_logic;
- signal edataout6: std_logic;
- signal edataout7: std_logic;
- signal edataout8: std_logic;
- signal edataout9: std_logic;
- signal edataout10: std_logic;
- signal edataout11: std_logic;
- signal edataout12: std_logic;
- signal edataout13: std_logic;
- signal edataout14: std_logic;
- signal edataout15: std_logic;
- signal edataout16: std_logic;
- signal edataout17: std_logic;
signal w_gcount_0: std_logic;
signal w_gcount_1: std_logic;
signal w_gcount_2: std_logic;
signal co0: std_logic;
signal iwcount_4: std_logic;
signal co2: std_logic;
- signal wcount_4: std_logic;
signal co1: std_logic;
+ signal wcount_4: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_gctr_ci: std_logic;
signal co0_1: std_logic;
signal ircount_4: std_logic;
signal co2_1: std_logic;
- signal rcount_4: std_logic;
signal co1_1: std_logic;
+ signal rcount_4: std_logic;
signal rden_i: std_logic;
signal cmp_ci: std_logic;
signal wcount_r0: std_logic;
signal co0_4: std_logic;
signal iaf_setcount_4: std_logic;
signal co2_2: std_logic;
- signal af_setcount_4: std_logic;
signal co1_4: std_logic;
+ signal af_setcount_4: std_logic;
signal wren_i: std_logic;
signal cmp_ci_2: std_logic;
signal rcount_w0: std_logic;
signal af_set_cmp_set: std_logic;
signal af_set: std_logic;
signal af_set_c: std_logic;
- signal rdataout17: std_logic;
- signal rdataout16: std_logic;
signal scuba_vlo: std_logic;
- signal rdataout15: std_logic;
- signal rdataout14: std_logic;
- signal rdataout13: std_logic;
- signal rdataout12: std_logic;
- signal rdataout11: std_logic;
- signal rdataout10: std_logic;
- signal rdataout9: std_logic;
- signal rdataout8: std_logic;
- signal rdataout7: std_logic;
- signal rdataout6: std_logic;
- signal rdataout5: std_logic;
- signal rdataout4: std_logic;
- signal rdataout3: std_logic;
- signal rdataout2: std_logic;
- signal rdataout1: std_logic;
- signal rdataout0: std_logic;
- signal rptr_3: std_logic;
- signal rptr_2: std_logic;
- signal rptr_1: std_logic;
- signal rptr_0: std_logic;
- signal dec0_wre3: std_logic;
- signal wptr_3: std_logic;
- signal wptr_2: std_logic;
- signal wptr_1: std_logic;
- signal wptr_0: std_logic;
-- local component declarations
component AGEB2
port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
- component DPR16X4C
- generic (INITVAL : in String);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; WCK: in std_logic; WRE: in std_logic;
- RAD0: in std_logic; RAD1: in std_logic;
- RAD2: in std_logic; RAD3: in std_logic;
- WAD0: in std_logic; WAD1: in std_logic;
- WAD2: in std_logic; WAD3: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic);
- end component;
component VHI
port (Z: out std_logic);
end component;
component XOR2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
- attribute GSR : string;
- attribute MEM_INIT_FILE : string;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
attribute MEM_LPC_FILE : string;
- attribute COMP : string;
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
attribute GSR of FF_57 : label is "ENABLED";
attribute GSR of FF_56 : label is "ENABLED";
attribute GSR of FF_55 : label is "ENABLED";
attribute GSR of FF_2 : label is "ENABLED";
attribute GSR of FF_1 : label is "ENABLED";
attribute GSR of FF_0 : label is "ENABLED";
- attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)";
- attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
- attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
- attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)";
- attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
- attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
- attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)";
- attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
- attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2";
- attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)";
- attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
- attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3";
- attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(16-17)";
- attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
- attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4";
attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
XOR2_t0: XOR2
port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
- LUT4_14: ROM16X1A
- generic map (initval=> X"8000")
- port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
- AD0=>scuba_vhi, DO0=>dec0_wre3);
-
LUT4_13: ROM16X1A
generic map (initval=> X"6996")
port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
AD0=>wptr_4, DO0=>af_set_cmp_clr);
- FF_93: FD1P3BX
+ pdp_ram_0_0_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>scuba_vlo, ADA9=>scuba_vlo,
+ ADA10=>scuba_vlo, ADA11=>scuba_vlo, ADA12=>scuba_vlo,
+ ADA13=>scuba_vlo, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3,
+ ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
+ ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
+ CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
+ DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8),
+ DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>Q(12),
+ DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), DOB16=>Q(16),
+ DOB17=>Q(17));
+
+ FF_57: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
Q=>wcount_0);
- FF_92: FD1P3DX
+ FF_56: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_1);
- FF_91: FD1P3DX
+ FF_55: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_2);
- FF_90: FD1P3DX
+ FF_54: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_3);
- FF_89: FD1P3DX
+ FF_53: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_4);
- FF_88: FD1P3DX
+ FF_52: FD1P3DX
port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_0);
- FF_87: FD1P3DX
+ FF_51: FD1P3DX
port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_1);
- FF_86: FD1P3DX
+ FF_50: FD1P3DX
port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_2);
- FF_85: FD1P3DX
+ FF_49: FD1P3DX
port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_3);
- FF_84: FD1P3DX
+ FF_48: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_4);
- FF_83: FD1P3DX
+ FF_47: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_0);
- FF_82: FD1P3DX
+ FF_46: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_1);
- FF_81: FD1P3DX
+ FF_45: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_2);
- FF_80: FD1P3DX
+ FF_44: FD1P3DX
port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_3);
- FF_79: FD1P3DX
+ FF_43: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_4);
- FF_78: FD1P3BX
+ FF_42: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
Q=>rcount_0);
- FF_77: FD1P3DX
+ FF_41: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_1);
- FF_76: FD1P3DX
+ FF_40: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_2);
- FF_75: FD1P3DX
+ FF_39: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_3);
- FF_74: FD1P3DX
+ FF_38: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_4);
- FF_73: FD1P3DX
+ FF_37: FD1P3DX
port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_0);
- FF_72: FD1P3DX
+ FF_36: FD1P3DX
port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_1);
- FF_71: FD1P3DX
+ FF_35: FD1P3DX
port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_2);
- FF_70: FD1P3DX
+ FF_34: FD1P3DX
port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_3);
- FF_69: FD1P3DX
+ FF_33: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_4);
- FF_68: FD1P3DX
+ FF_32: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_0);
- FF_67: FD1P3DX
+ FF_31: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_1);
- FF_66: FD1P3DX
+ FF_30: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_2);
- FF_65: FD1P3DX
+ FF_29: FD1P3DX
port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_3);
- FF_64: FD1P3DX
+ FF_28: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_4);
- FF_63: FD1P3DX
- port map (D=>edataout0, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(0));
-
- FF_62: FD1P3DX
- port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout0);
-
- FF_61: FD1P3DX
- port map (D=>edataout1, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(1));
-
- FF_60: FD1P3DX
- port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout1);
-
- FF_59: FD1P3DX
- port map (D=>edataout2, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(2));
-
- FF_58: FD1P3DX
- port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout2);
-
- FF_57: FD1P3DX
- port map (D=>edataout3, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(3));
-
- FF_56: FD1P3DX
- port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout3);
-
- FF_55: FD1P3DX
- port map (D=>edataout4, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(4));
-
- FF_54: FD1P3DX
- port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout4);
-
- FF_53: FD1P3DX
- port map (D=>edataout5, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(5));
-
- FF_52: FD1P3DX
- port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout5);
-
- FF_51: FD1P3DX
- port map (D=>edataout6, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(6));
-
- FF_50: FD1P3DX
- port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout6);
-
- FF_49: FD1P3DX
- port map (D=>edataout7, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(7));
-
- FF_48: FD1P3DX
- port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout7);
-
- FF_47: FD1P3DX
- port map (D=>edataout8, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(8));
-
- FF_46: FD1P3DX
- port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout8);
-
- FF_45: FD1P3DX
- port map (D=>edataout9, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(9));
-
- FF_44: FD1P3DX
- port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout9);
-
- FF_43: FD1P3DX
- port map (D=>edataout10, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(10));
-
- FF_42: FD1P3DX
- port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout10);
-
- FF_41: FD1P3DX
- port map (D=>edataout11, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(11));
-
- FF_40: FD1P3DX
- port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout11);
-
- FF_39: FD1P3DX
- port map (D=>edataout12, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(12));
-
- FF_38: FD1P3DX
- port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout12);
-
- FF_37: FD1P3DX
- port map (D=>edataout13, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(13));
-
- FF_36: FD1P3DX
- port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout13);
-
- FF_35: FD1P3DX
- port map (D=>edataout14, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(14));
-
- FF_34: FD1P3DX
- port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout14);
-
- FF_33: FD1P3DX
- port map (D=>edataout15, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(15));
-
- FF_32: FD1P3DX
- port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout15);
-
- FF_31: FD1P3DX
- port map (D=>edataout16, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(16));
-
- FF_30: FD1P3DX
- port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout16);
-
- FF_29: FD1P3DX
- port map (D=>edataout17, SP=>scuba_vhi, CK=>RdClock, CD=>rRst,
- Q=>Q(17));
-
- FF_28: FD1P3DX
- port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>edataout17);
-
FF_27: FD1S3DX
port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr,
B1=>scuba_vlo, CI=>co1_5, GE=>af_set_c);
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
a2: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
S1=>open);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- fifo_pfu_0_0: DPR16X4C
- generic map (initval=> "0x0000000000000000")
- port map (DI0=>Data(16), DI1=>Data(17), DI2=>scuba_vlo,
- DI3=>scuba_vlo, WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16,
- DO1=>rdataout17, DO2=>open, DO3=>open);
-
- fifo_pfu_0_1: DPR16X4C
- generic map (initval=> "0x0000000000000000")
- port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
- DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12,
- DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15);
-
- fifo_pfu_0_2: DPR16X4C
- generic map (initval=> "0x0000000000000000")
- port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
- DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
- RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
- WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8,
- DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11);
-
- fifo_pfu_0_3: DPR16X4C
- generic map (initval=> "0x0000000000000000")
- port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
- WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
- RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
- WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5,
- DO2=>rdataout6, DO3=>rdataout7);
-
- fifo_pfu_0_4: DPR16X4C
- generic map (initval=> "0x0000000000000000")
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
- RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
- WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1,
- DO2=>rdataout2, DO3=>rdataout3);
-
Empty <= empty_i;
Full <= full_i;
end Structure;
for all:INV use entity ecp3.INV(V); end for;
for all:OR2 use entity ecp3.OR2(V); end for;
for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for;
for all:VHI use entity ecp3.VHI(V); end for;
for all:VLO use entity ecp3.VLO(V); end for;
for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
end for;
end Structure_CON;
jspc29 / trbnet.git / commitdiff